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gem5
v21.1.0.2
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#include "base/inet.hh"#include "dev/io_device.hh"#include "dev/net/etherdevice.hh"#include "dev/net/etherint.hh"#include "dev/net/etherpkt.hh"#include "dev/net/ns_gige_reg.h"#include "dev/net/pktfifo.hh"#include "params/NSGigE.hh"#include "sim/eventq.hh"Go to the source code of this file.
Classes | |
| struct | gem5::dp_regs |
| Ethernet device registers. More... | |
| struct | gem5::dp_rom |
| class | gem5::NSGigE |
| NS DP83820 Ethernet device model. More... | |
| class | gem5::NSGigEInt |
Namespaces | |
| gem5 | |
| Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223. | |
Variables | |
| const uint16_t | gem5::FHASH_ADDR = 0x100 |
| const uint16_t | gem5::FHASH_SIZE = 0x100 |
| const uint8_t | gem5::EEPROM_READ = 0x2 |
| const uint8_t | gem5::EEPROM_SIZE = 64 |
| const uint8_t | gem5::EEPROM_PMATCH2_ADDR = 0xA |
| const uint8_t | gem5::EEPROM_PMATCH1_ADDR = 0xB |
| const uint8_t | gem5::EEPROM_PMATCH0_ADDR = 0xC |
Device module for modelling the National Semiconductor DP83820 ethernet controller
Definition in file ns_gige.hh.