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gem5
v21.1.0.2
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#include <cassert>#include <cstddef>#include "arch/vecregs.hh"#include "base/types.hh"#include "config/the_isa.hh"Go to the source code of this file.
Classes | |
| class | gem5::RegClassInfo |
| class | gem5::RegId |
| Register ID: describe an architectural register with its class and index. More... | |
| class | gem5::PhysRegId |
| Physical register ID. More... | |
| struct | std::hash< gem5::RegId > |
Namespaces | |
| gem5 | |
| Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223. | |
| std | |
| Overload hash function for BasicBlockRange type. | |
Typedefs | |
| using | gem5::PhysRegIdPtr = PhysRegId * |
Enumerations | |
| enum | gem5::RegClass { gem5::IntRegClass, gem5::FloatRegClass, gem5::VecRegClass, gem5::VecElemClass, gem5::VecPredRegClass, gem5::CCRegClass, gem5::MiscRegClass } |
| Enumerate the classes of registers. More... | |