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gem5
v21.1.0.2
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#include <string>#include <vector>Go to the source code of this file.
Namespaces | |
| gem5 | |
| Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223. | |
| gem5::RiscvISA | |
Variables | |
| const int | gem5::RiscvISA::NumIntArchRegs = 32 |
| const int | gem5::RiscvISA::NumMicroIntRegs = 1 |
| const int | gem5::RiscvISA::NumIntRegs = NumIntArchRegs + NumMicroIntRegs |
| const int | gem5::RiscvISA::ReturnAddrReg = 1 |
| const int | gem5::RiscvISA::StackPointerReg = 2 |
| const int | gem5::RiscvISA::ThreadPointerReg = 4 |
| const int | gem5::RiscvISA::ReturnValueReg = 10 |
| const std::vector< int > | gem5::RiscvISA::ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17} |
| const int | gem5::RiscvISA::AMOTempReg = 32 |
| const int | gem5::RiscvISA::SyscallNumReg = 17 |
| const std::vector< std::string > | gem5::RiscvISA::IntRegNames |