sve.hh File Reference

#include "arch/arm/insts/static_inst.hh"

Go to the source code of this file.

Classes
class	gem5::ArmISA::SveIndexIIOp
	Index generation instruction, immediate operands. More...
class	gem5::ArmISA::SveIndexIROp
class	gem5::ArmISA::SveIndexRIOp
class	gem5::ArmISA::SveIndexRROp
class	gem5::ArmISA::SvePredCountOp
class	gem5::ArmISA::SvePredCountPredOp
class	gem5::ArmISA::SveWhileOp
	While predicate generation SVE instruction. More...
class	gem5::ArmISA::SveCompTermOp
	Compare and terminate loop SVE instruction. More...
class	gem5::ArmISA::SveUnaryPredOp
	Unary, constructive, predicated (merging) SVE instruction. More...
class	gem5::ArmISA::SveUnaryUnpredOp
	Unary, constructive, unpredicated SVE instruction. More...
class	gem5::ArmISA::SveUnaryWideImmUnpredOp
	Unary with wide immediate, constructive, unpredicated SVE instruction. More...
class	gem5::ArmISA::SveUnaryWideImmPredOp
	Unary with wide immediate, constructive, predicated SVE instruction. More...
class	gem5::ArmISA::SveBinImmUnpredConstrOp
	Binary with immediate, destructive, unpredicated SVE instruction. More...
class	gem5::ArmISA::SveBinImmPredOp
	Binary with immediate, destructive, predicated (merging) SVE instruction. More...
class	gem5::ArmISA::SveBinWideImmUnpredOp
	Binary with wide immediate, destructive, unpredicated SVE instruction. More...
class	gem5::ArmISA::SveBinDestrPredOp
	Binary, destructive, predicated (merging) SVE instruction. More...
class	gem5::ArmISA::SveBinConstrPredOp
	Binary, constructive, predicated SVE instruction. More...
class	gem5::ArmISA::SveBinUnpredOp
	Binary, unpredicated SVE instruction with indexed operand. More...
class	gem5::ArmISA::SveBinIdxUnpredOp
	Binary, unpredicated SVE instruction. More...
class	gem5::ArmISA::SvePredLogicalOp
	Predicate logical instruction. More...
class	gem5::ArmISA::SvePredBinPermOp
	Predicate binary permute instruction. More...
class	gem5::ArmISA::SveCmpOp
	SVE compare instructions, predicated (zeroing). More...
class	gem5::ArmISA::SveCmpImmOp
	SVE compare-with-immediate instructions, predicated (zeroing). More...
class	gem5::ArmISA::SveTerPredOp
	Ternary, destructive, predicated (merging) SVE instruction. More...
class	gem5::ArmISA::SveTerImmUnpredOp
	Ternary with immediate, destructive, unpredicated SVE instruction. More...
class	gem5::ArmISA::SveReducOp
	SVE reductions. More...
class	gem5::ArmISA::SveOrdReducOp
	SVE ordered reductions. More...
class	gem5::ArmISA::SvePtrueOp
	PTRUE, PTRUES. More...
class	gem5::ArmISA::SveIntCmpOp
	Integer compare SVE instruction. More...
class	gem5::ArmISA::SveIntCmpImmOp
	Integer compare with immediate SVE instruction. More...
class	gem5::ArmISA::SveAdrOp
	ADR. More...
class	gem5::ArmISA::SveElemCountOp
	Element count SVE instruction. More...
class	gem5::ArmISA::SvePartBrkOp
	Partition break SVE instruction. More...
class	gem5::ArmISA::SvePartBrkPropOp
	Partition break with propagation SVE instruction. More...
class	gem5::ArmISA::SveSelectOp
	Scalar element select SVE instruction. More...
class	gem5::ArmISA::SveUnaryPredPredOp
	SVE unary operation on predicate (predicated) More...
class	gem5::ArmISA::SveTblOp
	SVE table lookup/permute using vector of element indices (TBL) More...
class	gem5::ArmISA::SveUnpackOp
	SVE unpack and widen predicate. More...
class	gem5::ArmISA::SvePredTestOp
	SVE predicate test. More...
class	gem5::ArmISA::SvePredUnaryWImplicitSrcOp
	SVE unary predicate instructions with implicit source operand. More...
class	gem5::ArmISA::SvePredUnaryWImplicitSrcPredOp
	SVE unary predicate instructions, predicated, with implicit source operand. More...
class	gem5::ArmISA::SvePredUnaryWImplicitDstOp
	SVE unary predicate instructions with implicit destination operand. More...
class	gem5::ArmISA::SveWImplicitSrcDstOp
	SVE unary predicate instructions with implicit destination operand. More...
class	gem5::ArmISA::SveBinImmUnpredDestrOp
	SVE vector - immediate binary operation. More...
class	gem5::ArmISA::SveBinImmIdxUnpredOp
	Binary with immediate index, destructive, unpredicated SVE instruction. More...
class	gem5::ArmISA::SveUnarySca2VecUnpredOp
	Unary unpredicated scalar to vector instruction. More...
class	gem5::ArmISA::SveDotProdIdxOp
	SVE dot product instruction (indexed) More...
class	gem5::ArmISA::SveDotProdOp
	SVE dot product instruction (vectors) More...
class	gem5::ArmISA::SveComplexOp
	SVE Complex Instructions (vectors) More...
class	gem5::ArmISA::SveComplexIdxOp
	SVE Complex Instructions (indexed) More...

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
	gem5::ArmISA

Enumerations
enum	gem5::ArmISA::SvePredType { gem5::ArmISA::SvePredType::NONE, gem5::ArmISA::SvePredType::MERGE, gem5::ArmISA::SvePredType::ZERO, gem5::ArmISA::SvePredType::SELECT }

Functions
const char *	gem5::ArmISA::svePredTypeToStr (SvePredType pt)
	Returns the specifier for the predication type pt as a string. More...
std::string	gem5::ArmISA::sveDisasmPredCountImm (uint8_t imm)
	Returns the symbolic name associated with pattern imm for PTRUE(S) instructions. More...
unsigned int	gem5::ArmISA::sveDecodePredCount (uint8_t imm, unsigned int num_elems)
	Returns the actual number of elements active for PTRUE(S) instructions. More...
uint64_t	gem5::ArmISA::sveExpandFpImmAddSub (uint8_t imm, uint8_t size)
	Expand 1-bit floating-point immediate to 0.5 or 1.0 (FADD, FSUB, FSUBR). More...
uint64_t	gem5::ArmISA::sveExpandFpImmMaxMin (uint8_t imm, uint8_t size)
	Expand 1-bit floating-point immediate to 0.0 or 1.0 (FMAX, FMAXNM, FMIN, FMINNM). More...
uint64_t	gem5::ArmISA::sveExpandFpImmMul (uint8_t imm, uint8_t size)
	Expand 1-bit floating-point immediate to 0.5 or 2.0 (FMUL). More...