| _status | gem5::BaseSimpleCPU | protected |
| activateContext(ThreadID thread_num) override | gem5::AtomicSimpleCPU | |
| activeThreads | gem5::BaseSimpleCPU | |
| advancePC(const Fault &fault) | gem5::BaseSimpleCPU | |
| amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override | gem5::AtomicSimpleCPU | virtual |
| AtomicSimpleCPU(const AtomicSimpleCPUParams ¶ms) | gem5::AtomicSimpleCPU | |
| BaseSimpleCPU(const BaseSimpleCPUParams ¶ms) | gem5::BaseSimpleCPU | |
| branchPred | gem5::BaseSimpleCPU | protected |
| checker | gem5::BaseSimpleCPU | |
| checkForInterrupts() | gem5::BaseSimpleCPU | |
| checkPcEventQueue() | gem5::BaseSimpleCPU | protected |
| countInst() | gem5::BaseSimpleCPU | |
| curMacroStaticInst | gem5::BaseSimpleCPU | |
| curStaticInst | gem5::BaseSimpleCPU | |
| curThread | gem5::BaseSimpleCPU | protected |
| data_amo_req | gem5::AtomicSimpleCPU | protected |
| data_read_req | gem5::AtomicSimpleCPU | protected |
| data_write_req | gem5::AtomicSimpleCPU | protected |
| dcache_access | gem5::AtomicSimpleCPU | protected |
| dcache_latency | gem5::AtomicSimpleCPU | protected |
| dcachePort | gem5::AtomicSimpleCPU | protected |
| DcacheRetry enum value | gem5::BaseSimpleCPU | protected |
| DcacheWaitResponse enum value | gem5::BaseSimpleCPU | protected |
| DcacheWaitSwitch enum value | gem5::BaseSimpleCPU | protected |
| drain() override | gem5::AtomicSimpleCPU | |
| drainResume() override | gem5::AtomicSimpleCPU | |
| DTBWaitResponse enum value | gem5::BaseSimpleCPU | protected |
| Faulting enum value | gem5::BaseSimpleCPU | protected |
| fetchInstMem() override | gem5::NonCachingSimpleCPU | protectedvirtual |
| genMemFragmentRequest(const RequestPtr &req, Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const | gem5::AtomicSimpleCPU | |
| getDataPort() override | gem5::AtomicSimpleCPU | inlineprotected |
| getInstPort() override | gem5::AtomicSimpleCPU | inlineprotected |
| haltContext(ThreadID thread_num) override | gem5::BaseSimpleCPU | |
| htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause) override | gem5::AtomicSimpleCPU | inline |
| icachePort | gem5::AtomicSimpleCPU | protected |
| IcacheRetry enum value | gem5::BaseSimpleCPU | protected |
| IcacheWaitResponse enum value | gem5::BaseSimpleCPU | protected |
| IcacheWaitSwitch enum value | gem5::BaseSimpleCPU | protected |
| Idle enum value | gem5::BaseSimpleCPU | protected |
| ifetch_req | gem5::AtomicSimpleCPU | protected |
| init() override | gem5::AtomicSimpleCPU | |
| initiateHtmCmd(Request::Flags flags) override | gem5::AtomicSimpleCPU | inlinevirtual |
| initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) | gem5::BaseSimpleCPU | inlinevirtual |
| initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) | gem5::BaseSimpleCPU | inlinevirtual |
| isCpuDrained() const | gem5::AtomicSimpleCPU | inlineprotected |
| ITBWaitResponse enum value | gem5::BaseSimpleCPU | protected |
| locked | gem5::AtomicSimpleCPU | protected |
| memBackdoors | gem5::NonCachingSimpleCPU | protected |
| NonCachingSimpleCPU(const NonCachingSimpleCPUParams &p) | gem5::NonCachingSimpleCPU | |
| postExecute() | gem5::BaseSimpleCPU | |
| ppCommit | gem5::AtomicSimpleCPU | protected |
| preExecute() | gem5::BaseSimpleCPU | |
| preExecuteTempPC | gem5::BaseSimpleCPU | protected |
| printAddr(Addr a) | gem5::AtomicSimpleCPU | |
| readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override | gem5::AtomicSimpleCPU | virtual |
| regProbePoints() override | gem5::AtomicSimpleCPU | |
| resetStats() override | gem5::BaseSimpleCPU | |
| Running enum value | gem5::BaseSimpleCPU | protected |
| sendPacket(RequestPort &port, const PacketPtr &pkt) override | gem5::NonCachingSimpleCPU | protectedvirtual |
| serializeThread(CheckpointOut &cp, ThreadID tid) const override | gem5::BaseSimpleCPU | |
| serviceInstCountEvents() | gem5::BaseSimpleCPU | |
| setupFetchRequest(const RequestPtr &req) | gem5::BaseSimpleCPU | |
| simulate_data_stalls | gem5::AtomicSimpleCPU | protected |
| simulate_inst_stalls | gem5::AtomicSimpleCPU | protected |
| Status enum name | gem5::BaseSimpleCPU | protected |
| suspendContext(ThreadID thread_num) override | gem5::AtomicSimpleCPU | |
| swapActiveThread() | gem5::BaseSimpleCPU | protected |
| switchOut() override | gem5::AtomicSimpleCPU | |
| takeOverFrom(BaseCPU *old_cpu) override | gem5::AtomicSimpleCPU | |
| threadInfo | gem5::BaseSimpleCPU | |
| threadSnoop(PacketPtr pkt, ThreadID sender) | gem5::AtomicSimpleCPU | protected |
| tick() | gem5::AtomicSimpleCPU | protected |
| tickEvent | gem5::AtomicSimpleCPU | protected |
| totalInsts() const override | gem5::BaseSimpleCPU | |
| totalOps() const override | gem5::BaseSimpleCPU | |
| traceData | gem5::BaseSimpleCPU | |
| traceFault() | gem5::BaseSimpleCPU | protected |
| tryCompleteDrain() | gem5::AtomicSimpleCPU | protected |
| unserializeThread(CheckpointIn &cp, ThreadID tid) override | gem5::BaseSimpleCPU | |
| verifyMemoryMode() const override | gem5::NonCachingSimpleCPU | |
| wakeup(ThreadID tid) override | gem5::BaseSimpleCPU | |
| width | gem5::AtomicSimpleCPU | protected |
| writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >()) override | gem5::AtomicSimpleCPU | virtual |
| zeroReg | gem5::BaseSimpleCPU | protected |
| ~AtomicSimpleCPU() | gem5::AtomicSimpleCPU | virtual |
| ~BaseSimpleCPU() | gem5::BaseSimpleCPU | virtual |