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gem5
v21.2.1.1
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This is the complete list of members for gem5::SimpleExecContext, including all inherited members.
| amoMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override | gem5::SimpleExecContext | inlinevirtual |
| armMonitor(Addr address) override | gem5::SimpleExecContext | inlinevirtual |
| cpu | gem5::SimpleExecContext | |
| demapPage(Addr vaddr, uint64_t asn) override | gem5::SimpleExecContext | inlinevirtual |
| execContextStats | gem5::SimpleExecContext | |
| fetchOffset | gem5::SimpleExecContext | |
| getAddrMonitor() override | gem5::SimpleExecContext | inlinevirtual |
| getHtmTransactionalDepth() const override | gem5::SimpleExecContext | inlinevirtual |
| getHtmTransactionUid() const override | gem5::SimpleExecContext | inlinevirtual |
| getWritableVecPredRegOperand(const StaticInst *si, int idx) override | gem5::SimpleExecContext | inlinevirtual |
| getWritableVecRegOperand(const StaticInst *si, int idx) override | gem5::SimpleExecContext | inlinevirtual |
| inHtmTransactionalState() const override | gem5::SimpleExecContext | inlinevirtual |
| initiateHtmCmd(Request::Flags flags) override | gem5::SimpleExecContext | inlinevirtual |
| initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override | gem5::SimpleExecContext | inlinevirtual |
| initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override | gem5::SimpleExecContext | inlinevirtual |
| lastDcacheStall | gem5::SimpleExecContext | |
| lastIcacheStall | gem5::SimpleExecContext | |
| mwait(PacketPtr pkt) override | gem5::SimpleExecContext | inlinevirtual |
| mwaitAtomic(ThreadContext *tc) override | gem5::SimpleExecContext | inlinevirtual |
| newHtmTransactionUid() const override | gem5::SimpleExecContext | inlinevirtual |
| numInst | gem5::SimpleExecContext | |
| numLoad | gem5::SimpleExecContext | |
| numOp | gem5::SimpleExecContext | |
| pcState() const override | gem5::SimpleExecContext | inlinevirtual |
| pcState(const PCStateBase &val) override | gem5::SimpleExecContext | inlinevirtual |
| predPC | gem5::SimpleExecContext | |
| readCCRegOperand(const StaticInst *si, int idx) override | gem5::SimpleExecContext | inlinevirtual |
| readFloatRegOperandBits(const StaticInst *si, int idx) override | gem5::SimpleExecContext | inlinevirtual |
| readIntRegOperand(const StaticInst *si, int idx) override | gem5::SimpleExecContext | inlinevirtual |
| readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override | gem5::SimpleExecContext | inlinevirtual |
| readMemAccPredicate() const override | gem5::SimpleExecContext | inlinevirtual |
| readMiscReg(int misc_reg) override | gem5::SimpleExecContext | inlinevirtual |
| readMiscRegOperand(const StaticInst *si, int idx) override | gem5::SimpleExecContext | inlinevirtual |
| readPredicate() const override | gem5::SimpleExecContext | inlinevirtual |
| readStCondFailures() const override | gem5::SimpleExecContext | inlinevirtual |
| readVecElemOperand(const StaticInst *si, int idx) const override | gem5::SimpleExecContext | inlinevirtual |
| readVecPredRegOperand(const StaticInst *si, int idx) const override | gem5::SimpleExecContext | inlinevirtual |
| readVecRegOperand(const StaticInst *si, int idx) const override | gem5::SimpleExecContext | inlinevirtual |
| setCCRegOperand(const StaticInst *si, int idx, RegVal val) override | gem5::SimpleExecContext | inlinevirtual |
| setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override | gem5::SimpleExecContext | inlinevirtual |
| setIntRegOperand(const StaticInst *si, int idx, RegVal val) override | gem5::SimpleExecContext | inlinevirtual |
| setMemAccPredicate(bool val) override | gem5::SimpleExecContext | inlinevirtual |
| setMiscReg(int misc_reg, RegVal val) override | gem5::SimpleExecContext | inlinevirtual |
| setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override | gem5::SimpleExecContext | inlinevirtual |
| setPredicate(bool val) override | gem5::SimpleExecContext | inlinevirtual |
| setStCondFailures(unsigned int sc_failures) override | gem5::SimpleExecContext | inlinevirtual |
| setVecElemOperand(const StaticInst *si, int idx, RegVal val) override | gem5::SimpleExecContext | inlinevirtual |
| setVecPredRegOperand(const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override | gem5::SimpleExecContext | inlinevirtual |
| setVecRegOperand(const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override | gem5::SimpleExecContext | inlinevirtual |
| SimpleExecContext(BaseSimpleCPU *_cpu, SimpleThread *_thread) | gem5::SimpleExecContext | inline |
| stayAtPC | gem5::SimpleExecContext | |
| tcBase() const override | gem5::SimpleExecContext | inlinevirtual |
| thread | gem5::SimpleExecContext | |
| writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override | gem5::SimpleExecContext | inlinevirtual |