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gem5
v21.2.1.1
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#include <vector>#include "arch/generic/mmu.hh"#include "base/named.hh"#include "cpu/base.hh"#include "cpu/minor/buffers.hh"#include "cpu/minor/cpu.hh"#include "cpu/minor/pipe_data.hh"#include "mem/packet.hh"Go to the source code of this file.
Classes | |
| class | gem5::minor::Fetch1 |
| A stage responsible for fetching "lines" from memory and passing them to Fetch2. More... | |
| class | gem5::minor::Fetch1::IcachePort |
| Exposable fetch port. More... | |
| class | gem5::minor::Fetch1::FetchRequest |
| Memory access queuing. More... | |
| struct | gem5::minor::Fetch1::Fetch1ThreadInfo |
| Stage cycle-by-cycle state. More... | |
Namespaces | |
| gem5 | |
| Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223. | |
| gem5::minor | |
Functions | |
| gem5::GEM5_DEPRECATED_NAMESPACE (Minor, minor) | |
Fetch1 is responsible for fetching "lines" from memory and passing them to Fetch2
Definition in file fetch1.hh.