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gem5
v21.2.1.1
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#include <vector>#include "arch/generic/isa.hh"#include "arch/riscv/pcstate.hh"#include "arch/riscv/types.hh"#include "base/types.hh"Go to the source code of this file.
Classes | |
| class | gem5::RiscvISA::ISA |
Namespaces | |
| gem5 | |
| Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223. | |
| gem5::RiscvISA | |
Enumerations | |
| enum | gem5::RiscvISA::PrivilegeMode { gem5::RiscvISA::PRV_U = 0, gem5::RiscvISA::PRV_S = 1, gem5::RiscvISA::PRV_M = 3 } |
| enum | gem5::RiscvISA::FPUStatus { gem5::RiscvISA::OFF = 0, gem5::RiscvISA::INITIAL = 1, gem5::RiscvISA::CLEAN = 2, gem5::RiscvISA::DIRTY = 3 } |