#include "arch/x86/regs/segment.hh"
#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"
#include "base/logging.hh"

Go to the source code of this file.

Classes
class	gem5::X86ISA::SegDescriptorLimit

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.

	gem5::X86ISA
	This is exposed globally, independent of the ISA.

	gem5::X86ISA::misc_reg

Enumerations
enum	gem5::X86ISA::CondFlagBit { gem5::X86ISA::CFBit = 1 << 0, gem5::X86ISA::PFBit = 1 << 2, gem5::X86ISA::ECFBit = 1 << 3, gem5::X86ISA::AFBit = 1 << 4, gem5::X86ISA::EZFBit = 1 << 5, gem5::X86ISA::ZFBit = 1 << 6, gem5::X86ISA::SFBit = 1 << 7, gem5::X86ISA::DFBit = 1 << 10, gem5::X86ISA::OFBit = 1 << 11 }

enum	gem5::X86ISA::RFLAGBit { gem5::X86ISA::TFBit = 1 << 8, gem5::X86ISA::IFBit = 1 << 9, gem5::X86ISA::NTBit = 1 << 14, gem5::X86ISA::RFBit = 1 << 16, gem5::X86ISA::VMBit = 1 << 17, gem5::X86ISA::ACBit = 1 << 18, gem5::X86ISA::VIFBit = 1 << 19, gem5::X86ISA::VIPBit = 1 << 20, gem5::X86ISA::IDBit = 1 << 21 }

enum	gem5::X86ISA::X87StatusBit { gem5::X86ISA::IEBit = 1 << 0, gem5::X86ISA::DEBit = 1 << 1, gem5::X86ISA::ZEBit = 1 << 2, gem5::X86ISA::OEBit = 1 << 3, gem5::X86ISA::UEBit = 1 << 4, gem5::X86ISA::PEBit = 1 << 5, gem5::X86ISA::StackFaultBit = 1 << 6, gem5::X86ISA::ErrSummaryBit = 1 << 7, gem5::X86ISA::CC0Bit = 1 << 8, gem5::X86ISA::CC1Bit = 1 << 9, gem5::X86ISA::CC2Bit = 1 << 10, gem5::X86ISA::CC3Bit = 1 << 14, gem5::X86ISA::BusyBit = 1 << 15 }

enum	: RegIndex { gem5::X86ISA::misc_reg::CrBase, gem5::X86ISA::misc_reg::Cr0 = CrBase, gem5::X86ISA::misc_reg::Cr1, gem5::X86ISA::misc_reg::Cr2, gem5::X86ISA::misc_reg::Cr3, gem5::X86ISA::misc_reg::Cr4, gem5::X86ISA::misc_reg::Cr5, gem5::X86ISA::misc_reg::Cr6, gem5::X86ISA::misc_reg::Cr7, gem5::X86ISA::misc_reg::Cr8, gem5::X86ISA::misc_reg::Cr9, gem5::X86ISA::misc_reg::Cr10, gem5::X86ISA::misc_reg::Cr11, gem5::X86ISA::misc_reg::Cr12, gem5::X86ISA::misc_reg::Cr13, gem5::X86ISA::misc_reg::Cr14, gem5::X86ISA::misc_reg::Cr15, gem5::X86ISA::misc_reg::DrBase = CrBase + NumCRegs, gem5::X86ISA::misc_reg::Dr0 = DrBase, gem5::X86ISA::misc_reg::Dr1, gem5::X86ISA::misc_reg::Dr2, gem5::X86ISA::misc_reg::Dr3, gem5::X86ISA::misc_reg::Dr4, gem5::X86ISA::misc_reg::Dr5, gem5::X86ISA::misc_reg::Dr6, gem5::X86ISA::misc_reg::Dr7, gem5::X86ISA::misc_reg::Rflags = DrBase + NumDRegs, gem5::X86ISA::misc_reg::M5Reg, gem5::X86ISA::misc_reg::Tsc, gem5::X86ISA::misc_reg::Mtrrcap, gem5::X86ISA::misc_reg::SysenterCs, gem5::X86ISA::misc_reg::SysenterEsp, gem5::X86ISA::misc_reg::SysenterEip, gem5::X86ISA::misc_reg::McgCap, gem5::X86ISA::misc_reg::McgStatus, gem5::X86ISA::misc_reg::McgCtl, gem5::X86ISA::misc_reg::DebugCtlMsr, gem5::X86ISA::misc_reg::LastBranchFromIp, gem5::X86ISA::misc_reg::LastBranchToIp, gem5::X86ISA::misc_reg::LastExceptionFromIp, gem5::X86ISA::misc_reg::LastExceptionToIp, gem5::X86ISA::misc_reg::MtrrPhysBaseBase, gem5::X86ISA::misc_reg::MtrrPhysBase0 = MtrrPhysBaseBase, gem5::X86ISA::misc_reg::MtrrPhysBase1, gem5::X86ISA::misc_reg::MtrrPhysBase2, gem5::X86ISA::misc_reg::MtrrPhysBase3, gem5::X86ISA::misc_reg::MtrrPhysBase4, gem5::X86ISA::misc_reg::MtrrPhysBase5, gem5::X86ISA::misc_reg::MtrrPhysBase6, gem5::X86ISA::misc_reg::MtrrPhysBase7, gem5::X86ISA::misc_reg::MtrrPhysBaseEnd, gem5::X86ISA::misc_reg::MtrrPhysMaskBase = MtrrPhysBaseEnd, gem5::X86ISA::misc_reg::MtrrPhysMask0 = MtrrPhysMaskBase, gem5::X86ISA::misc_reg::MtrrPhysMask1, gem5::X86ISA::misc_reg::MtrrPhysMask2, gem5::X86ISA::misc_reg::MtrrPhysMask3, gem5::X86ISA::misc_reg::MtrrPhysMask4, gem5::X86ISA::misc_reg::MtrrPhysMask5, gem5::X86ISA::misc_reg::MtrrPhysMask6, gem5::X86ISA::misc_reg::MtrrPhysMask7, gem5::X86ISA::misc_reg::MtrrPhysMaskEnd, gem5::X86ISA::misc_reg::MtrrFix64k00000 = MtrrPhysMaskEnd, gem5::X86ISA::misc_reg::MtrrFix16k80000, gem5::X86ISA::misc_reg::MtrrFix16kA0000, gem5::X86ISA::misc_reg::MtrrFix4kC0000, gem5::X86ISA::misc_reg::MtrrFix4kC8000, gem5::X86ISA::misc_reg::MtrrFix4kD0000, gem5::X86ISA::misc_reg::MtrrFix4kD8000, gem5::X86ISA::misc_reg::MtrrFix4kE0000, gem5::X86ISA::misc_reg::MtrrFix4kE8000, gem5::X86ISA::misc_reg::MtrrFix4kF0000, gem5::X86ISA::misc_reg::MtrrFix4kF8000, gem5::X86ISA::misc_reg::Pat, gem5::X86ISA::misc_reg::DefType, gem5::X86ISA::misc_reg::McCtlBase, gem5::X86ISA::misc_reg::Mc0Ctl = McCtlBase, gem5::X86ISA::misc_reg::Mc1Ctl, gem5::X86ISA::misc_reg::Mc2Ctl, gem5::X86ISA::misc_reg::Mc3Ctl, gem5::X86ISA::misc_reg::Mc4Ctl, gem5::X86ISA::misc_reg::Mc5Ctl, gem5::X86ISA::misc_reg::Mc6Ctl, gem5::X86ISA::misc_reg::Mc7Ctl, gem5::X86ISA::misc_reg::McCtlEnd, gem5::X86ISA::misc_reg::McStatusBase = McCtlEnd, gem5::X86ISA::misc_reg::Mc0Status = McStatusBase, gem5::X86ISA::misc_reg::Mc1Status, gem5::X86ISA::misc_reg::Mc2Status, gem5::X86ISA::misc_reg::Mc3Status, gem5::X86ISA::misc_reg::Mc4Status, gem5::X86ISA::misc_reg::Mc5Status, gem5::X86ISA::misc_reg::Mc6Status, gem5::X86ISA::misc_reg::Mc7Status, gem5::X86ISA::misc_reg::McStatusEnd, gem5::X86ISA::misc_reg::McAddrBase = McStatusEnd, gem5::X86ISA::misc_reg::Mc0Addr = McAddrBase, gem5::X86ISA::misc_reg::Mc1Addr, gem5::X86ISA::misc_reg::Mc2Addr, gem5::X86ISA::misc_reg::Mc3Addr, gem5::X86ISA::misc_reg::Mc4Addr, gem5::X86ISA::misc_reg::Mc5Addr, gem5::X86ISA::misc_reg::Mc6Addr, gem5::X86ISA::misc_reg::Mc7Addr, gem5::X86ISA::misc_reg::McAddrEnd, gem5::X86ISA::misc_reg::McMiscBase = McAddrEnd, gem5::X86ISA::misc_reg::Mc0Misc = McMiscBase, gem5::X86ISA::misc_reg::Mc1Misc, gem5::X86ISA::misc_reg::Mc2Misc, gem5::X86ISA::misc_reg::Mc3Misc, gem5::X86ISA::misc_reg::Mc4Misc, gem5::X86ISA::misc_reg::Mc5Misc, gem5::X86ISA::misc_reg::Mc6Misc, gem5::X86ISA::misc_reg::Mc7Misc, gem5::X86ISA::misc_reg::McMiscEnd, gem5::X86ISA::misc_reg::Efer = McMiscEnd, gem5::X86ISA::misc_reg::Star, gem5::X86ISA::misc_reg::Lstar, gem5::X86ISA::misc_reg::Cstar, gem5::X86ISA::misc_reg::SfMask, gem5::X86ISA::misc_reg::KernelGsBase, gem5::X86ISA::misc_reg::TscAux, gem5::X86ISA::misc_reg::PerfEvtSelBase, gem5::X86ISA::misc_reg::PerfEvtSel0 = PerfEvtSelBase, gem5::X86ISA::misc_reg::PerfEvtSel1, gem5::X86ISA::misc_reg::PerfEvtSel2, gem5::X86ISA::misc_reg::PerfEvtSel3, gem5::X86ISA::misc_reg::PerfEvtSelEnd, gem5::X86ISA::misc_reg::PerfEvtCtrBase = PerfEvtSelEnd, gem5::X86ISA::misc_reg::PerfEvtCtr0 = PerfEvtCtrBase, gem5::X86ISA::misc_reg::PerfEvtCtr1, gem5::X86ISA::misc_reg::PerfEvtCtr2, gem5::X86ISA::misc_reg::PerfEvtCtr3, gem5::X86ISA::misc_reg::PerfEvtCtrEnd, gem5::X86ISA::misc_reg::Syscfg = PerfEvtCtrEnd, gem5::X86ISA::misc_reg::IorrBaseBase, gem5::X86ISA::misc_reg::IorrBase0 = IorrBaseBase, gem5::X86ISA::misc_reg::IorrBase1, gem5::X86ISA::misc_reg::IorrBaseEnd, gem5::X86ISA::misc_reg::IorrMaskBase = IorrBaseEnd, gem5::X86ISA::misc_reg::IorrMask0 = IorrMaskBase, gem5::X86ISA::misc_reg::IorrMask1, gem5::X86ISA::misc_reg::IorrMaskEnd, gem5::X86ISA::misc_reg::TopMem = IorrMaskEnd, gem5::X86ISA::misc_reg::TopMem2, gem5::X86ISA::misc_reg::VmCr, gem5::X86ISA::misc_reg::Ignne, gem5::X86ISA::misc_reg::SmmCtl, gem5::X86ISA::misc_reg::VmHsavePa, gem5::X86ISA::misc_reg::SegSelBase, gem5::X86ISA::misc_reg::Es = SegSelBase, gem5::X86ISA::misc_reg::Cs, gem5::X86ISA::misc_reg::Ss, gem5::X86ISA::misc_reg::Ds, gem5::X86ISA::misc_reg::Fs, gem5::X86ISA::misc_reg::Gs, gem5::X86ISA::misc_reg::Hs, gem5::X86ISA::misc_reg::Tsl, gem5::X86ISA::misc_reg::Tsg, gem5::X86ISA::misc_reg::Ls, gem5::X86ISA::misc_reg::Ms, gem5::X86ISA::misc_reg::Tr, gem5::X86ISA::misc_reg::Idtr, gem5::X86ISA::misc_reg::SegBaseBase = SegSelBase + segment_idx::NumIdxs, gem5::X86ISA::misc_reg::EsBase = SegBaseBase, gem5::X86ISA::misc_reg::CsBase, gem5::X86ISA::misc_reg::SsBase, gem5::X86ISA::misc_reg::DsBase, gem5::X86ISA::misc_reg::FsBase, gem5::X86ISA::misc_reg::GsBase, gem5::X86ISA::misc_reg::HsBase, gem5::X86ISA::misc_reg::TslBase, gem5::X86ISA::misc_reg::TsgBase, gem5::X86ISA::misc_reg::LsBase, gem5::X86ISA::misc_reg::MsBase, gem5::X86ISA::misc_reg::TrBase, gem5::X86ISA::misc_reg::IdtrBase, gem5::X86ISA::misc_reg::SegEffBaseBase = SegBaseBase + segment_idx::NumIdxs, gem5::X86ISA::misc_reg::EsEffBase = SegEffBaseBase, gem5::X86ISA::misc_reg::CsEffBase, gem5::X86ISA::misc_reg::SsEffBase, gem5::X86ISA::misc_reg::DsEffBase, gem5::X86ISA::misc_reg::FsEffBase, gem5::X86ISA::misc_reg::GsEffBase, gem5::X86ISA::misc_reg::HsEffBase, gem5::X86ISA::misc_reg::TslEffBase, gem5::X86ISA::misc_reg::TsgEffBase, gem5::X86ISA::misc_reg::LsEffBase, gem5::X86ISA::misc_reg::MsEffBase, gem5::X86ISA::misc_reg::TrEffBase, gem5::X86ISA::misc_reg::IdtrEffBase, gem5::X86ISA::misc_reg::SegLimitBase = SegEffBaseBase + segment_idx::NumIdxs, gem5::X86ISA::misc_reg::EsLimit = SegLimitBase, gem5::X86ISA::misc_reg::CsLimit, gem5::X86ISA::misc_reg::SsLimit, gem5::X86ISA::misc_reg::DsLimit, gem5::X86ISA::misc_reg::FsLimit, gem5::X86ISA::misc_reg::GsLimit, gem5::X86ISA::misc_reg::HsLimit, gem5::X86ISA::misc_reg::TslLimit, gem5::X86ISA::misc_reg::TsgLimit, gem5::X86ISA::misc_reg::LsLimit, gem5::X86ISA::misc_reg::MsLimit, gem5::X86ISA::misc_reg::TrLimit, gem5::X86ISA::misc_reg::IdtrLimit, gem5::X86ISA::misc_reg::SegAttrBase = SegLimitBase + segment_idx::NumIdxs, gem5::X86ISA::misc_reg::EsAttr = SegAttrBase, gem5::X86ISA::misc_reg::CsAttr, gem5::X86ISA::misc_reg::SsAttr, gem5::X86ISA::misc_reg::DsAttr, gem5::X86ISA::misc_reg::FsAttr, gem5::X86ISA::misc_reg::GsAttr, gem5::X86ISA::misc_reg::HsAttr, gem5::X86ISA::misc_reg::TslAttr, gem5::X86ISA::misc_reg::TsgAttr, gem5::X86ISA::misc_reg::LsAttr, gem5::X86ISA::misc_reg::MsAttr, gem5::X86ISA::misc_reg::TrAttr, gem5::X86ISA::misc_reg::IdtrAttr, gem5::X86ISA::misc_reg::X87Top = SegAttrBase + segment_idx::NumIdxs, gem5::X86ISA::misc_reg::Mxcsr, gem5::X86ISA::misc_reg::Fcw, gem5::X86ISA::misc_reg::Fsw, gem5::X86ISA::misc_reg::Ftw, gem5::X86ISA::misc_reg::Ftag, gem5::X86ISA::misc_reg::Fiseg, gem5::X86ISA::misc_reg::Fioff, gem5::X86ISA::misc_reg::Foseg, gem5::X86ISA::misc_reg::Fooff, gem5::X86ISA::misc_reg::Fop, gem5::X86ISA::misc_reg::ApicBase, gem5::X86ISA::misc_reg::PciConfigAddress, gem5::X86ISA::misc_reg::NumRegs }

Functions
static bool	gem5::X86ISA::misc_reg::isValid (int index)

static RegIndex	gem5::X86ISA::misc_reg::cr (int index)

static RegIndex	gem5::X86ISA::misc_reg::dr (int index)

static RegIndex	gem5::X86ISA::misc_reg::mtrrPhysBase (int index)

static RegIndex	gem5::X86ISA::misc_reg::mtrrPhysMask (int index)

static RegIndex	gem5::X86ISA::misc_reg::mcCtl (int index)

static RegIndex	gem5::X86ISA::misc_reg::mcStatus (int index)

static RegIndex	gem5::X86ISA::misc_reg::mcAddr (int index)

static RegIndex	gem5::X86ISA::misc_reg::mcMisc (int index)

static RegIndex	gem5::X86ISA::misc_reg::perfEvtSel (int index)

static RegIndex	gem5::X86ISA::misc_reg::perfEvtCtr (int index)

static RegIndex	gem5::X86ISA::misc_reg::iorrBase (int index)

static RegIndex	gem5::X86ISA::misc_reg::iorrMask (int index)

static RegIndex	gem5::X86ISA::misc_reg::segSel (int index)

static RegIndex	gem5::X86ISA::misc_reg::segBase (int index)

static RegIndex	gem5::X86ISA::misc_reg::segEffBase (int index)

static RegIndex	gem5::X86ISA::misc_reg::segLimit (int index)

static RegIndex	gem5::X86ISA::misc_reg::segAttr (int index)

	gem5::X86ISA::BitUnion64 (CCFlagBits) Bitfield< 11 > of
	A type to describe the condition code bits of the RFLAGS register, plus two flags, EZF and ECF, which are only visible to microcode. More...

	gem5::X86ISA::EndBitUnion (CCFlagBits) BitUnion64(RFLAGS) Bitfield< 21 > id
	RFLAGS. More...

	gem5::X86ISA::EndBitUnion (RFLAGS) BitUnion64(HandyM5Reg) Bitfield< 0 > mode

	gem5::X86ISA::EndBitUnion (HandyM5Reg) BitUnion64(CR0) Bitfield< 31 > pg
	Control registers. More...

	gem5::X86ISA::EndBitUnion (CR0) BitUnion64(CR2) Bitfield< 31

	gem5::X86ISA::EndBitUnion (CR2) BitUnion64(CR3) Bitfield< 51

	gem5::X86ISA::EndBitUnion (CR3) BitUnion64(CR4) Bitfield< 18 > osxsave

	gem5::X86ISA::EndBitUnion (CR4) BitUnion64(CR8) Bitfield< 3

	gem5::X86ISA::EndBitUnion (CR8) BitUnion64(DR6) Bitfield< 0 > b0

	gem5::X86ISA::EndBitUnion (DR6) BitUnion64(DR7) Bitfield< 0 > l0

	gem5::X86ISA::EndBitUnion (DR7) BitUnion64(MTRRcap) Bitfield< 7

	gem5::X86ISA::EndBitUnion (MTRRcap) BitUnion64(SysenterCS) Bitfield< 15
	SYSENTER configuration registers. More...

	gem5::X86ISA::EndBitUnion (SysenterCS) BitUnion64(SysenterESP) Bitfield< 31

	gem5::X86ISA::EndBitUnion (SysenterESP) BitUnion64(SysenterEIP) Bitfield< 31

	gem5::X86ISA::EndBitUnion (SysenterEIP) BitUnion64(McgCap) Bitfield< 7
	Global machine check registers. More...

	gem5::X86ISA::EndBitUnion (McgCap) BitUnion64(McgStatus) Bitfield< 0 > ripv

	gem5::X86ISA::EndBitUnion (McgStatus) BitUnion64(DebugCtlMsr) Bitfield< 0 > lbr

	gem5::X86ISA::EndBitUnion (DebugCtlMsr) BitUnion64(MtrrPhysBase) Bitfield< 7

	gem5::X86ISA::EndBitUnion (MtrrPhysBase) BitUnion64(MtrrPhysMask) Bitfield< 11 > valid

	gem5::X86ISA::EndBitUnion (MtrrPhysMask) BitUnion64(MtrrFixed) EndBitUnion(MtrrFixed) BitUnion64(Pat) EndBitUnion(Pat) BitUnion64(MtrrDefType) Bitfield< 7

	gem5::X86ISA::EndBitUnion (MtrrDefType) BitUnion64(McStatus) Bitfield< 15
	Machine check. More...

	gem5::X86ISA::EndBitUnion (McStatus) BitUnion64(McCtl) EndBitUnion(McCtl) BitUnion64(Efer) Bitfield< 0 > sce

	gem5::X86ISA::EndBitUnion (Efer) BitUnion64(Star) Bitfield< 31

	gem5::X86ISA::EndBitUnion (Star) BitUnion64(SfMask) Bitfield< 31

	gem5::X86ISA::EndBitUnion (SfMask) BitUnion64(PerfEvtSel) Bitfield< 7

	gem5::X86ISA::EndBitUnion (PerfEvtSel) BitUnion32(Syscfg) Bitfield< 18 > mfde

	gem5::X86ISA::EndBitUnion (Syscfg) BitUnion64(IorrBase) Bitfield< 3 > wr

	gem5::X86ISA::EndBitUnion (IorrBase) BitUnion64(IorrMask) Bitfield< 11 > v

	gem5::X86ISA::EndBitUnion (IorrMask) BitUnion64(Tom) Bitfield< 51

	gem5::X86ISA::EndBitUnion (Tom) BitUnion64(VmCrMsr) Bitfield< 0 > dpd

	gem5::X86ISA::EndBitUnion (VmCrMsr) BitUnion64(IgnneMsr) Bitfield< 0 > ignne

	gem5::X86ISA::EndBitUnion (IgnneMsr) BitUnion64(SmmCtlMsr) Bitfield< 0 > dismiss

	gem5::X86ISA::EndBitUnion (SmmCtlMsr) BitUnion64(SegSelector) Bitfield< 63
	Segment Selector. More...

	gem5::X86ISA::EndBitUnion (SegSelector) class SegDescriptorBase
	Segment Descriptors. More...

	gem5::X86ISA::BitUnion64 (SegDescriptor) Bitfield< 63

	gem5::X86ISA::SubBitUnion (type, 43, 40) Bitfield< 43 > codeOrData

	gem5::X86ISA::EndSubBitUnion (type) EndBitUnion(SegDescriptor) BitUnion64(TSSlow) Bitfield< 63
	TSS Descriptor (long mode - 128 bits) the lower 64 bits. More...

	gem5::X86ISA::EndBitUnion (TSShigh) BitUnion64(SegAttr) Bitfield< 1

	gem5::X86ISA::EndBitUnion (SegAttr) BitUnion64(GateDescriptor) Bitfield< 63

	gem5::X86ISA::EndBitUnion (GateDescriptor) BitUnion64(GateDescriptorLow) Bitfield< 63
	Long Mode Gate Descriptor. More...

	gem5::X86ISA::EndBitUnion (GateDescriptorLow) BitUnion64(GateDescriptorHigh) Bitfield< 31

	gem5::X86ISA::EndBitUnion (GateDescriptorHigh) BitUnion64(GDTR) EndBitUnion(GDTR) BitUnion64(IDTR) EndBitUnion(IDTR) BitUnion64(LDTR) EndBitUnion(LDTR) BitUnion64(TR) EndBitUnion(TR) BitUnion64(LocalApicBase) Bitfield< 51
	Descriptor-Table Registers. More...

Variables
constexpr uint32_t	gem5::X86ISA::CfofMask = CFBit \| OFBit

constexpr uint32_t	gem5::X86ISA::CcFlagMask = PFBit \| AFBit \| ZFBit \| SFBit

Bitfield< 7 >	gem5::X86ISA::sf

Bitfield< 6 >	gem5::X86ISA::zf

Bitfield< 5 >	gem5::X86ISA::ezf

Bitfield< 4 >	gem5::X86ISA::af

Bitfield< 3 >	gem5::X86ISA::ecf

Bitfield< 2 >	gem5::X86ISA::pf

Bitfield< 0 >	gem5::X86ISA::cf

Bitfield< 20 >	gem5::X86ISA::vip

Bitfield< 19 >	gem5::X86ISA::vif

Bitfield< 18 >	gem5::X86ISA::ac

Bitfield< 17 >	gem5::X86ISA::vm

Bitfield< 16 >	gem5::X86ISA::rf

Bitfield< 14 >	gem5::X86ISA::nt

Bitfield< 13, 12 >	gem5::X86ISA::iopl

Bitfield< 11 >	gem5::X86ISA::of

Bitfield< 10 >	gem5::X86ISA::df

Bitfield< 9 >	gem5::X86ISA::intf

Bitfield< 8 >	gem5::X86ISA::tf

Bitfield< 3, 1 >	gem5::X86ISA::submode

Bitfield< 5, 4 >	gem5::X86ISA::cpl

Bitfield< 6 >	gem5::X86ISA::paging

Bitfield< 7 >	gem5::X86ISA::prot

Bitfield< 9, 8 >	gem5::X86ISA::defOp

Bitfield< 11, 10 >	gem5::X86ISA::altOp

Bitfield< 13, 12 >	gem5::X86ISA::defAddr

Bitfield< 15, 14 >	gem5::X86ISA::altAddr

Bitfield< 17, 16 >	gem5::X86ISA::stack

Bitfield< 30 >	gem5::X86ISA::cd

Bitfield< 29 >	gem5::X86ISA::nw

Bitfield< 18 >	gem5::X86ISA::am

Bitfield< 16 >	gem5::X86ISA::wp

Bitfield< 5 >	gem5::X86ISA::ne

Bitfield< 4 >	gem5::X86ISA::et

Bitfield< 3 >	gem5::X86ISA::ts

Bitfield< 2 >	gem5::X86ISA::em

Bitfield< 1 >	gem5::X86ISA::mp

Bitfield< 0 >	gem5::X86ISA::pe

	gem5::X86ISA::legacy

	gem5::X86ISA::longPdtb

Bitfield< 31, 12 >	gem5::X86ISA::pdtb

Bitfield< 31, 5 >	gem5::X86ISA::paePdtb

Bitfield< 16 >	gem5::X86ISA::fsgsbase

Bitfield< 10 >	gem5::X86ISA::osxmmexcpt

Bitfield< 9 >	gem5::X86ISA::osfxsr

Bitfield< 8 >	gem5::X86ISA::pce

Bitfield< 7 >	gem5::X86ISA::pge

Bitfield< 6 >	gem5::X86ISA::mce

Bitfield< 5 >	gem5::X86ISA::pae

Bitfield< 4 >	gem5::X86ISA::pse

Bitfield< 3 >	gem5::X86ISA::de

Bitfield< 2 >	gem5::X86ISA::tsd

Bitfield< 1 >	gem5::X86ISA::pvi

Bitfield< 0 >	gem5::X86ISA::vme

	gem5::X86ISA::tpr

Bitfield< 1 >	gem5::X86ISA::b1

Bitfield< 2 >	gem5::X86ISA::b2

Bitfield< 3 >	gem5::X86ISA::b3

Bitfield< 13 >	gem5::X86ISA::bd

Bitfield< 14 >	gem5::X86ISA::bs

Bitfield< 15 >	gem5::X86ISA::bt

Bitfield< 1 >	gem5::X86ISA::g0

Bitfield< 2 >	gem5::X86ISA::l1

Bitfield< 3 >	gem5::X86ISA::g1

Bitfield< 4 >	gem5::X86ISA::l2

Bitfield< 5 >	gem5::X86ISA::g2

Bitfield< 6 >	gem5::X86ISA::l3

Bitfield< 7 >	gem5::X86ISA::g3

Bitfield< 8 >	gem5::X86ISA::le

Bitfield< 9 >	gem5::X86ISA::ge

Bitfield< 13 >	gem5::X86ISA::gd

Bitfield< 17, 16 >	gem5::X86ISA::rw0

Bitfield< 19, 18 >	gem5::X86ISA::len0

Bitfield< 21, 20 >	gem5::X86ISA::rw1

Bitfield< 23, 22 >	gem5::X86ISA::len1

Bitfield< 25, 24 >	gem5::X86ISA::rw2

Bitfield< 27, 26 >	gem5::X86ISA::len2

Bitfield< 29, 28 >	gem5::X86ISA::rw3

Bitfield< 31, 30 >	gem5::X86ISA::len3

	gem5::X86ISA::vcnt

Bitfield< 8 >	gem5::X86ISA::fix

Bitfield< 10 >	gem5::X86ISA::wc

	gem5::X86ISA::targetCS

	gem5::X86ISA::targetESP

	gem5::X86ISA::targetEIP

	gem5::X86ISA::count

Bitfield< 8 >	gem5::X86ISA::MCGCP

Bitfield< 1 >	gem5::X86ISA::eipv

Bitfield< 2 >	gem5::X86ISA::mcip

Bitfield< 1 >	gem5::X86ISA::btf

Bitfield< 2 >	gem5::X86ISA::pb0

Bitfield< 3 >	gem5::X86ISA::pb1

Bitfield< 4 >	gem5::X86ISA::pb2

Bitfield< 5 >	gem5::X86ISA::pb3

	gem5::X86ISA::type

Bitfield< 51, 12 >	gem5::X86ISA::physbase

Bitfield< 51, 12 >	gem5::X86ISA::physmask

Bitfield< 10 >	gem5::X86ISA::fe

Bitfield< 11 >	gem5::X86ISA::e

	gem5::X86ISA::mcaErrorCode

Bitfield< 31, 16 >	gem5::X86ISA::modelSpecificCode

Bitfield< 56, 32 >	gem5::X86ISA::otherInfo

Bitfield< 57 >	gem5::X86ISA::pcc

Bitfield< 58 >	gem5::X86ISA::addrv

Bitfield< 59 >	gem5::X86ISA::miscv

Bitfield< 60 >	gem5::X86ISA::en

Bitfield< 61 >	gem5::X86ISA::uc

Bitfield< 62 >	gem5::X86ISA::over

Bitfield< 63 >	gem5::X86ISA::val

Bitfield< 8 >	gem5::X86ISA::lme

Bitfield< 10 >	gem5::X86ISA::lma

Bitfield< 11 >	gem5::X86ISA::nxe

Bitfield< 12 >	gem5::X86ISA::svme

Bitfield< 14 >	gem5::X86ISA::ffxsr

	gem5::X86ISA::targetEip

Bitfield< 47, 32 >	gem5::X86ISA::syscallCsAndSs

Bitfield< 63, 48 >	gem5::X86ISA::sysretCsAndSs

	gem5::X86ISA::mask

	gem5::X86ISA::eventMask

Bitfield< 15, 8 >	gem5::X86ISA::unitMask

Bitfield< 16 >	gem5::X86ISA::usr

Bitfield< 17 >	gem5::X86ISA::os

Bitfield< 19 >	gem5::X86ISA::pc

Bitfield< 20 >	gem5::X86ISA::intEn

Bitfield< 23 >	gem5::X86ISA::inv

Bitfield< 31, 24 >	gem5::X86ISA::counterMask

Bitfield< 19 >	gem5::X86ISA::mfdm

Bitfield< 20 >	gem5::X86ISA::mvdm

Bitfield< 21 >	gem5::X86ISA::tom2

Bitfield< 4 >	gem5::X86ISA::rd

	gem5::X86ISA::physAddr

Bitfield< 1 >	gem5::X86ISA::rInit

Bitfield< 2 >	gem5::X86ISA::disA20M

Bitfield< 1 >	gem5::X86ISA::enter

Bitfield< 2 >	gem5::X86ISA::smiCycle

Bitfield< 3 >	gem5::X86ISA::exit

Bitfield< 4 >	gem5::X86ISA::rsmCycle

	gem5::X86ISA::esi

Bitfield< 15, 3 >	gem5::X86ISA::si

Bitfield< 2 >	gem5::X86ISA::ti

Bitfield< 1, 0 >	gem5::X86ISA::rpl

	gem5::X86ISA::baseHigh

Bitfield< 39, 16 >	gem5::X86ISA::baseLow

Bitfield< 54 >	gem5::X86ISA::b

Bitfield< 53 >	gem5::X86ISA::l

Bitfield< 51, 48 >	gem5::X86ISA::limitHigh

Bitfield< 15, 0 >	gem5::X86ISA::limitLow

BitfieldType< SegDescriptorLimit >	gem5::X86ISA::limit

Bitfield< 46, 45 >	gem5::X86ISA::dpl

Bitfield< 44 >	gem5::X86ISA::s

Bitfield< 42 >	gem5::X86ISA::c

Bitfield< 41 >	gem5::X86ISA::r

Bitfield< 2 >	gem5::X86ISA::unusable

Bitfield< 3 >	gem5::X86ISA::defaultSize

Bitfield< 4 >	gem5::X86ISA::longMode

Bitfield< 6 >	gem5::X86ISA::granularity

Bitfield< 7 >	gem5::X86ISA::present

Bitfield< 12 >	gem5::X86ISA::writable

Bitfield< 13 >	gem5::X86ISA::readable

Bitfield< 14 >	gem5::X86ISA::expandDown

Bitfield< 15 >	gem5::X86ISA::system

	gem5::X86ISA::offsetHigh

Bitfield< 15, 0 >	gem5::X86ISA::offsetLow

Bitfield< 31, 16 >	gem5::X86ISA::selector

Bitfield< 35, 32 >	gem5::X86ISA::IST

	gem5::X86ISA::offset

Bitfield< 11 >	gem5::X86ISA::enable

Bitfield< 8 >	gem5::X86ISA::bsp

Classes

Namespaces

Enumerations

Functions

Variables