int.hh File Reference

#include <cassert>
#include "arch/arm/types.hh"
#include "base/logging.hh"
#include "cpu/reg_class.hh"
#include "sim/core.hh"

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Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
	gem5::ArmISA

Functions
	gem5::ArmISA::BitUnion32 (PackedIntReg) Bitfield< 31
	gem5::ArmISA::EndBitUnion (PackedIntReg) namespace int_reg
static int	gem5::ArmISA::flattenIntRegModeIndex (int reg)
static RegIndex	gem5::ArmISA::makeSP (RegIndex reg)
static bool	gem5::ArmISA::couldBeSP (RegIndex reg)
static bool	gem5::ArmISA::isSP (RegIndex reg)
static bool	gem5::ArmISA::couldBeZero (RegIndex reg)
static bool	gem5::ArmISA::isZero (RegIndex reg)
static RegIndex	gem5::ArmISA::makeZero (RegIndex reg)

Variables
	gem5::ArmISA::uh1
Bitfield< 15, 0 >	gem5::ArmISA::uh0
SignedBitfield< 31, 16 >	gem5::ArmISA::sh1
SignedBitfield< 15, 0 >	gem5::ArmISA::sh0
Bitfield< 31, 0 >	gem5::ArmISA::uw
SignedBitfield< 31, 0 >	gem5::ArmISA::sw
constexpr size_t	gem5::ArmISA::NumArgumentRegs = 4
constexpr size_t	gem5::ArmISA::NumArgumentRegs64 = 8
constexpr auto &	gem5::ArmISA::ReturnValueReg = int_reg::X0
constexpr auto &	gem5::ArmISA::ReturnValueReg1 = int_reg::X1
constexpr auto &	gem5::ArmISA::ArgumentReg0 = int_reg::X0
constexpr auto &	gem5::ArmISA::ArgumentReg1 = int_reg::X1
constexpr auto &	gem5::ArmISA::ArgumentReg2 = int_reg::X2
constexpr auto &	gem5::ArmISA::FramePointerReg = int_reg::X11
constexpr auto &	gem5::ArmISA::StackPointerReg = int_reg::Sp
constexpr auto &	gem5::ArmISA::ReturnAddressReg = int_reg::Lr
constexpr auto &	gem5::ArmISA::SyscallNumReg = ReturnValueReg
constexpr auto &	gem5::ArmISA::SyscallPseudoReturnReg = ReturnValueReg
constexpr auto &	gem5::ArmISA::SyscallSuccessReg = ReturnValueReg