gem5  v22.0.0.2
gem5::CheckerThreadContext< TC > Member List

This is the complete list of members for gem5::CheckerThreadContext< TC >, including all inherited members.

activate() overridegem5::CheckerThreadContext< TC >inlinevirtual
Active enum valuegem5::ThreadContext
actualTCgem5::CheckerThreadContext< TC >private
checkerCPUgem5::CheckerThreadContext< TC >private
checkerTCgem5::CheckerThreadContext< TC >private
CheckerThreadContext(TC *actual_tc, CheckerCPU *checker_cpu)gem5::CheckerThreadContext< TC >inline
clearArchRegs() overridegem5::CheckerThreadContext< TC >inlinevirtual
compare(ThreadContext *one, ThreadContext *two)gem5::ThreadContextstatic
connectMemPorts(ThreadContext *tc)gem5::CheckerThreadContext< TC >inline
contextId() const overridegem5::CheckerThreadContext< TC >inlinevirtual
copyArchRegs(ThreadContext *tc) overridegem5::CheckerThreadContext< TC >inlinevirtual
cpuId() const overridegem5::CheckerThreadContext< TC >inlinevirtual
DefaultFloatResultgem5::ThreadContextstatic
DefaultIntResultgem5::ThreadContextstatic
descheduleInstCountEvent(Event *event) overridegem5::CheckerThreadContext< TC >inlinevirtual
exit()gem5::ThreadContextinlinevirtual
flattenRegId(const RegId &regId) const overridegem5::CheckerThreadContext< TC >inlinevirtual
floatResultgem5::ThreadContext
floatsgem5::ThreadContextstatic
getCheckerCpuPtr() overridegem5::CheckerThreadContext< TC >inlinevirtual
getCpuPtr() overridegem5::CheckerThreadContext< TC >inlinevirtual
getCurrentInstCount() overridegem5::CheckerThreadContext< TC >inlinevirtual
getDecoderPtr() overridegem5::CheckerThreadContext< TC >inlinevirtual
getHtmCheckpointPtr() overridegem5::CheckerThreadContext< TC >inlinevirtual
getIsaPtr() const overridegem5::CheckerThreadContext< TC >inlinevirtual
getMMUPtr() overridegem5::CheckerThreadContext< TC >inlinevirtual
getProcessPtr() overridegem5::CheckerThreadContext< TC >inlinevirtual
getReg(const RegId &reg) const overridegem5::CheckerThreadContext< TC >inlinevirtual
getReg(const RegId &reg, void *val) const overridegem5::CheckerThreadContext< TC >inlinevirtual
getRegFlat(const RegId &reg) const overridegem5::CheckerThreadContext< TC >inlinevirtual
getRegFlat(const RegId &reg, void *val) const overridegem5::CheckerThreadContext< TC >inlinevirtual
getSystemPtr() overridegem5::CheckerThreadContext< TC >inlinevirtual
getUseForClone()gem5::ThreadContextinline
getWritableReg(const RegId &reg) overridegem5::CheckerThreadContext< TC >inlinevirtual
getWritableRegFlat(const RegId &reg) overridegem5::CheckerThreadContext< TC >inlinevirtual
getWritableVecReg(const RegId &reg)gem5::ThreadContextinline
getWritableVecRegFlat(RegIndex idx)gem5::ThreadContextinline
halt() overridegem5::CheckerThreadContext< TC >inlinevirtual
Halted enum valuegem5::ThreadContext
Halting enum valuegem5::ThreadContext
htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) overridegem5::CheckerThreadContext< TC >inlinevirtual
intOffsetgem5::ThreadContext
intResultgem5::ThreadContext
intsgem5::ThreadContextstatic
pcState() const overridegem5::CheckerThreadContext< TC >inlinevirtual
pcState(const PCStateBase &val) overridegem5::CheckerThreadContext< TC >inlinevirtual
gem5::ThreadContext::pcState(Addr addr)gem5::ThreadContextinline
pcStateNoRecord(const PCStateBase &val) overridegem5::CheckerThreadContext< TC >inlinevirtual
quiesce()gem5::ThreadContext
quiesceTick(Tick resume)gem5::ThreadContext
readCCReg(RegIndex reg_idx) constgem5::ThreadContextinline
readCCRegFlat(RegIndex idx) constgem5::ThreadContextinline
readFloatReg(RegIndex reg_idx) constgem5::ThreadContextinline
readFloatRegFlat(RegIndex idx) constgem5::ThreadContextinline
readIntReg(RegIndex reg_idx) constgem5::ThreadContextinline
readIntRegFlat(RegIndex idx) constgem5::ThreadContextinline
readLastActivate() overridegem5::CheckerThreadContext< TC >inlinevirtual
readLastSuspend() overridegem5::CheckerThreadContext< TC >inlinevirtual
readMiscReg(RegIndex misc_reg) overridegem5::CheckerThreadContext< TC >inlinevirtual
readMiscRegNoEffect(RegIndex misc_reg) const overridegem5::CheckerThreadContext< TC >inlinevirtual
readStCondFailures() const overridegem5::CheckerThreadContext< TC >inlinevirtual
readVecElem(const RegId &reg) constgem5::ThreadContextinline
readVecElemFlat(RegIndex idx) constgem5::ThreadContextinline
readVecReg(const RegId &reg) constgem5::ThreadContextinline
readVecRegFlat(RegIndex idx) constgem5::ThreadContextinline
regStats(const std::string &name) overridegem5::CheckerThreadContext< TC >inlinevirtual
remove(PCEvent *e) overridegem5::CheckerThreadContext< TC >inlinevirtual
schedule(PCEvent *e) overridegem5::CheckerThreadContext< TC >inlinevirtual
scheduleInstCountEvent(Event *event, Tick count) overridegem5::CheckerThreadContext< TC >inlinevirtual
sendFunctional(PacketPtr pkt)gem5::ThreadContextvirtual
setCCReg(RegIndex reg_idx, RegVal val)gem5::ThreadContextinline
setCCRegFlat(RegIndex idx, RegVal val)gem5::ThreadContextinline
setContextId(ContextID id) overridegem5::CheckerThreadContext< TC >inlinevirtual
setFloatReg(RegIndex reg_idx, RegVal val)gem5::ThreadContextinline
setFloatRegFlat(RegIndex idx, RegVal val)gem5::ThreadContextinline
setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) overridegem5::CheckerThreadContext< TC >inlinevirtual
setIntReg(RegIndex reg_idx, RegVal val)gem5::ThreadContextinline
setIntRegFlat(RegIndex idx, RegVal val)gem5::ThreadContextinline
setMiscReg(RegIndex misc_reg, RegVal val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setMiscRegNoEffect(RegIndex misc_reg, RegVal val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setProcessPtr(Process *p) overridegem5::CheckerThreadContext< TC >inlinevirtual
setReg(const RegId &reg, RegVal val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setReg(const RegId &reg, const void *val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setRegFlat(const RegId &reg, RegVal val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setRegFlat(const RegId &reg, const void *val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setStatus(Status new_status) overridegem5::CheckerThreadContext< TC >inlinevirtual
setStCondFailures(unsigned sc_failures) overridegem5::CheckerThreadContext< TC >inlinevirtual
setThreadId(int id) overridegem5::CheckerThreadContext< TC >inlinevirtual
setUseForClone(bool new_val)gem5::ThreadContextinline
setVecElem(const RegId &reg, RegVal val)gem5::ThreadContextinline
setVecElemFlat(RegIndex idx, RegVal val)gem5::ThreadContextinline
setVecReg(const RegId &reg, const TheISA::VecRegContainer &val)gem5::ThreadContextinline
setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer &val)gem5::ThreadContextinline
socketId() const overridegem5::CheckerThreadContext< TC >inlinevirtual
status() const overridegem5::CheckerThreadContext< TC >inlinevirtual
Status enum namegem5::ThreadContext
suspend() overridegem5::CheckerThreadContext< TC >inlinevirtual
Suspended enum valuegem5::ThreadContext
takeOverFrom(ThreadContext *oldContext) overridegem5::CheckerThreadContext< TC >inlinevirtual
threadId() const overridegem5::CheckerThreadContext< TC >inlinevirtual
useForClonegem5::ThreadContextprotected
~ThreadContext()gem5::ThreadContextinlinevirtual

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