gem5  v22.0.0.2
gem5::MipsISA::ISA Member List

This is the complete list of members for gem5::MipsISA::ISA, including all inherited members.

_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
_regClassesgem5::BaseISAprotected
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
BankType enum namegem5::MipsISA::ISAprotected
bankTypegem5::MipsISA::ISAprotected
clear()gem5::MipsISA::ISA
configCP()gem5::MipsISA::ISA
copyRegsFrom(ThreadContext *src) overridegem5::MipsISA::ISAvirtual
CP0 typedefgem5::MipsISA::ISA
CP0EventType enum namegem5::MipsISA::ISA
cp0Updatedgem5::MipsISA::ISA
currentSection()gem5::Serializablestatic
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
drain() overridegem5::SimObjectinlinevirtual
Drainable()gem5::Drainableprotected
drainResume()gem5::Drainableinlineprotectedvirtual
drainState() constgem5::Drainableinline
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
filterCP0Write(int misc_reg, int reg_sel, RegVal val)gem5::MipsISA::ISA
find(const char *name)gem5::SimObjectstatic
flattenCCIndex(int reg) constgem5::MipsISA::ISAinline
flattenFloatIndex(int reg) constgem5::MipsISA::ISAinline
flattenIntIndex(int reg) constgem5::MipsISA::ISAinline
flattenMiscIndex(int reg) constgem5::MipsISA::ISAinline
flattenRegId(const RegId &regId) constgem5::MipsISA::ISAinline
flattenVecElemIndex(int reg) constgem5::MipsISA::ISAinline
flattenVecIndex(int reg) constgem5::MipsISA::ISAinline
flattenVecPredIndex(int reg) constgem5::MipsISA::ISAinline
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
getExecutingAsid() constgem5::BaseISAinlinevirtual
getPort(const std::string &if_name, PortID idx=InvalidPortID)gem5::SimObjectvirtual
getProbeManager()gem5::SimObject
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
getVPENum(ThreadID tid) constgem5::MipsISA::ISAinline
globalClearExclusive()gem5::BaseISAinlinevirtual
globalClearExclusive(ExecContext *xc)gem5::BaseISAinlinevirtual
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
handleLockedRead(const RequestPtr &req)gem5::BaseISAinlinevirtual
handleLockedRead(ExecContext *xc, const RequestPtr &req)gem5::BaseISAinlinevirtual
handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask)gem5::BaseISAinlinevirtual
handleLockedSnoop(ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask)gem5::BaseISAinlinevirtual
handleLockedSnoopHit()gem5::BaseISAinlinevirtual
handleLockedSnoopHit(ExecContext *xc)gem5::BaseISAinlinevirtual
handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask)gem5::BaseISAinlinevirtual
handleLockedWrite(ExecContext *xc, const RequestPtr &req, Addr cacheBlockMask)gem5::BaseISAinlinevirtual
init()gem5::SimObjectvirtual
initState()gem5::SimObjectvirtual
inUserMode() const overridegem5::MipsISA::ISAinlinevirtual
ISA(const Params &p)gem5::MipsISA::ISA
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
memInvalidate()gem5::SimObjectinlinevirtual
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
miscRegFilegem5::MipsISA::ISAprotected
miscRegFile_WriteMaskgem5::MipsISA::ISAprotected
miscRegNamesgem5::MipsISA::ISAstatic
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
newPCState(Addr new_inst_addr=0) const overridegem5::MipsISA::ISAinlinevirtual
notifyFork()gem5::Drainableinlinevirtual
numThreadsgem5::MipsISA::ISAprotected
numVpesgem5::MipsISA::ISAprotected
operator=(const Group &)=deletegem5::statistics::Group
Params typedefgem5::MipsISA::ISA
params() constgem5::SimObjectinline
pathgem5::Serializableprivatestatic
perProcessor enum valuegem5::MipsISA::ISAprotected
perThreadContext enum valuegem5::MipsISA::ISAprotected
perVirtProcessor enum valuegem5::MipsISA::ISAprotected
preDumpStats()gem5::statistics::Groupvirtual
probeManagergem5::SimObjectprivate
processCP0Event(BaseCPU *cpu, CP0EventType)gem5::MipsISA::ISA
readMiscReg(int misc_reg, ThreadID tid=0)gem5::MipsISA::ISA
readMiscRegNoEffect(int misc_reg, ThreadID tid=0) constgem5::MipsISA::ISA
RegClasses typedefgem5::BaseISA
regClasses() constgem5::BaseISAinline
regProbeListeners()gem5::SimObjectvirtual
regProbePoints()gem5::SimObjectvirtual
regStats()gem5::statistics::Groupvirtual
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
scheduleCP0Update(BaseCPU *cpu, Cycles delay=Cycles(0))gem5::MipsISA::ISA
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::SimObjectinlinevirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setCurTick(Tick newVal)gem5::EventManagerinline
setMiscReg(int misc_reg, RegVal val, ThreadID tid=0)gem5::MipsISA::ISA
setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0)gem5::MipsISA::ISA
setRegMask(int misc_reg, RegVal val, ThreadID tid=0)gem5::MipsISA::ISA
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
setThreadContext(ThreadContext *_tc)gem5::BaseISAinlinevirtual
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::BaseISAprotected
gem5::SimObject::SimObject(const Params &p)gem5::SimObject
simObjectListgem5::SimObjectprivatestatic
SimObjectList typedefgem5::SimObjectprivate
startup()gem5::SimObjectvirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::statistics::Groupprivate
takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)gem5::BaseISAinlinevirtual
tcgem5::BaseISAprotected
unserialize(CheckpointIn &cp) overridegem5::SimObjectinlinevirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
UpdateCP0 enum valuegem5::MipsISA::ISA
updateCP0ReadView(int misc_reg, ThreadID tid)gem5::MipsISA::ISAinline
updateCPU(BaseCPU *cpu)gem5::MipsISA::ISA
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual
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