gem5::ThreadContext Member List

This is the complete list of members for gem5::ThreadContext, including all inherited members.

activate()=0	gem5::ThreadContext	pure virtual
Active enum value	gem5::ThreadContext
clearArchRegs()=0	gem5::ThreadContext	pure virtual
compare(ThreadContext *one, ThreadContext *two)	gem5::ThreadContext	static
contextId() const =0	gem5::ThreadContext	pure virtual
copyArchRegs(ThreadContext *tc)=0	gem5::ThreadContext	pure virtual
cpuId() const =0	gem5::ThreadContext	pure virtual
DefaultFloatResult	gem5::ThreadContext	static
DefaultIntResult	gem5::ThreadContext	static
descheduleInstCountEvent(Event *event)=0	gem5::ThreadContext	pure virtual
exit()	gem5::ThreadContext	inlinevirtual
flattenRegId(const RegId &reg_id) const =0	gem5::ThreadContext	pure virtual
floatResult	gem5::ThreadContext
floats	gem5::ThreadContext	static
getCheckerCpuPtr()=0	gem5::ThreadContext	pure virtual
getCpuPtr()=0	gem5::ThreadContext	pure virtual
getCurrentInstCount()=0	gem5::ThreadContext	pure virtual
getDecoderPtr()=0	gem5::ThreadContext	pure virtual
getHtmCheckpointPtr()=0	gem5::ThreadContext	pure virtual
getIsaPtr() const =0	gem5::ThreadContext	pure virtual
getMMUPtr()=0	gem5::ThreadContext	pure virtual
getProcessPtr()=0	gem5::ThreadContext	pure virtual
getReg(const RegId &reg) const	gem5::ThreadContext	virtual
getReg(const RegId &reg, void *val) const	gem5::ThreadContext	virtual
getRegFlat(const RegId &reg) const	gem5::ThreadContext	virtual
getRegFlat(const RegId &reg, void *val) const =0	gem5::ThreadContext	pure virtual
getSystemPtr()=0	gem5::ThreadContext	pure virtual
getUseForClone()	gem5::ThreadContext	inline
getWritableReg(const RegId &reg)	gem5::ThreadContext	virtual
getWritableRegFlat(const RegId &reg)=0	gem5::ThreadContext	pure virtual
getWritableVecReg(const RegId &reg)	gem5::ThreadContext	inline
getWritableVecRegFlat(RegIndex idx)	gem5::ThreadContext	inline
halt()=0	gem5::ThreadContext	pure virtual
Halted enum value	gem5::ThreadContext
Halting enum value	gem5::ThreadContext
htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause)=0	gem5::ThreadContext	pure virtual
intOffset	gem5::ThreadContext
intResult	gem5::ThreadContext
ints	gem5::ThreadContext	static
pcState() const =0	gem5::ThreadContext	pure virtual
pcState(const PCStateBase &val)=0	gem5::ThreadContext	pure virtual
pcState(Addr addr)	gem5::ThreadContext	inline
pcStateNoRecord(const PCStateBase &val)=0	gem5::ThreadContext	pure virtual
quiesce()	gem5::ThreadContext
quiesceTick(Tick resume)	gem5::ThreadContext
readCCReg(RegIndex reg_idx) const	gem5::ThreadContext	inline
readCCRegFlat(RegIndex idx) const	gem5::ThreadContext	inline
readFloatReg(RegIndex reg_idx) const	gem5::ThreadContext	inline
readFloatRegFlat(RegIndex idx) const	gem5::ThreadContext	inline
readIntReg(RegIndex reg_idx) const	gem5::ThreadContext	inline
readIntRegFlat(RegIndex idx) const	gem5::ThreadContext	inline
readLastActivate()=0	gem5::ThreadContext	pure virtual
readLastSuspend()=0	gem5::ThreadContext	pure virtual
readMiscReg(RegIndex misc_reg)=0	gem5::ThreadContext	pure virtual
readMiscRegNoEffect(RegIndex misc_reg) const =0	gem5::ThreadContext	pure virtual
readStCondFailures() const =0	gem5::ThreadContext	pure virtual
readVecElem(const RegId &reg) const	gem5::ThreadContext	inline
readVecElemFlat(RegIndex idx) const	gem5::ThreadContext	inline
readVecReg(const RegId &reg) const	gem5::ThreadContext	inline
readVecRegFlat(RegIndex idx) const	gem5::ThreadContext	inline
regStats(const std::string &name)	gem5::ThreadContext	inlinevirtual
remove(PCEvent *event)=0	gem5::PCEventScope	pure virtual
schedule(PCEvent *event)=0	gem5::PCEventScope	pure virtual
scheduleInstCountEvent(Event *event, Tick count)=0	gem5::ThreadContext	pure virtual
sendFunctional(PacketPtr pkt)	gem5::ThreadContext	virtual
setCCReg(RegIndex reg_idx, RegVal val)	gem5::ThreadContext	inline
setCCRegFlat(RegIndex idx, RegVal val)	gem5::ThreadContext	inline
setContextId(ContextID id)=0	gem5::ThreadContext	pure virtual
setFloatReg(RegIndex reg_idx, RegVal val)	gem5::ThreadContext	inline
setFloatRegFlat(RegIndex idx, RegVal val)	gem5::ThreadContext	inline
setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt)=0	gem5::ThreadContext	pure virtual
setIntReg(RegIndex reg_idx, RegVal val)	gem5::ThreadContext	inline
setIntRegFlat(RegIndex idx, RegVal val)	gem5::ThreadContext	inline
setMiscReg(RegIndex misc_reg, RegVal val)=0	gem5::ThreadContext	pure virtual
setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0	gem5::ThreadContext	pure virtual
setProcessPtr(Process *p)=0	gem5::ThreadContext	pure virtual
setReg(const RegId &reg, RegVal val)	gem5::ThreadContext	virtual
setReg(const RegId &reg, const void *val)	gem5::ThreadContext	virtual
setRegFlat(const RegId &reg, RegVal val)	gem5::ThreadContext	virtual
setRegFlat(const RegId &reg, const void *val)=0	gem5::ThreadContext	pure virtual
setStatus(Status new_status)=0	gem5::ThreadContext	pure virtual
setStCondFailures(unsigned sc_failures)=0	gem5::ThreadContext	pure virtual
setThreadId(int id)=0	gem5::ThreadContext	pure virtual
setUseForClone(bool new_val)	gem5::ThreadContext	inline
setVecElem(const RegId &reg, RegVal val)	gem5::ThreadContext	inline
setVecElemFlat(RegIndex idx, RegVal val)	gem5::ThreadContext	inline
setVecReg(const RegId &reg, const TheISA::VecRegContainer &val)	gem5::ThreadContext	inline
setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer &val)	gem5::ThreadContext	inline
socketId() const =0	gem5::ThreadContext	pure virtual
status() const =0	gem5::ThreadContext	pure virtual
Status enum name	gem5::ThreadContext
suspend()=0	gem5::ThreadContext	pure virtual
Suspended enum value	gem5::ThreadContext
takeOverFrom(ThreadContext *old_context)=0	gem5::ThreadContext	pure virtual
threadId() const =0	gem5::ThreadContext	pure virtual
useForClone	gem5::ThreadContext	protected
~ThreadContext()	gem5::ThreadContext	inlinevirtual