gem5::o3::CPU Member List

This is the complete list of members for gem5::o3::CPU, including all inherited members.

_status	gem5::o3::CPU
activateContext(ThreadID tid) override	gem5::o3::CPU
activateStage(const StageIdx idx)	gem5::o3::CPU	inline
activateThread(ThreadID tid)	gem5::o3::CPU
activeThreads	gem5::o3::CPU	protected
activityRec	gem5::o3::CPU	private
activityThisCycle()	gem5::o3::CPU	inline
addInst(const DynInstPtr &inst)	gem5::o3::CPU
addThreadToExitingList(ThreadID tid)	gem5::o3::CPU
Blocked enum value	gem5::o3::CPU
checker	gem5::o3::CPU
cleanUpRemovedInsts()	gem5::o3::CPU
commit	gem5::o3::CPU	protected
commitDrained(ThreadID tid)	gem5::o3::CPU
CommitIdx enum value	gem5::o3::CPU
commitRenameMap	gem5::o3::CPU	protected
CPU(const BaseO3CPUParams &params)	gem5::o3::CPU
cpuStats	gem5::o3::CPU
cpuWaitList	gem5::o3::CPU
deactivateStage(const StageIdx idx)	gem5::o3::CPU	inline
deactivateThread(ThreadID tid)	gem5::o3::CPU
decode	gem5::o3::CPU	protected
DecodeIdx enum value	gem5::o3::CPU
decodeQueue	gem5::o3::CPU
demapPage(Addr vaddr, uint64_t asn)	gem5::o3::CPU	inline
drain() override	gem5::o3::CPU
drainResume() override	gem5::o3::CPU
drainSanityCheck() const	gem5::o3::CPU	private
dumpInsts()	gem5::o3::CPU
exitingThreads	gem5::o3::CPU	protected
exitThreads()	gem5::o3::CPU
fetch	gem5::o3::CPU	protected
FetchIdx enum value	gem5::o3::CPU
fetchQueue	gem5::o3::CPU
freeList	gem5::o3::CPU	protected
getAndIncrementInstSeq()	gem5::o3::CPU	inline
getArchReg(const RegId &reg, ThreadID tid)	gem5::o3::CPU
getArchReg(const RegId &reg, void *val, ThreadID tid)	gem5::o3::CPU
getDataPort() override	gem5::o3::CPU	inline
getFreeTid()	gem5::o3::CPU
getInstPort() override	gem5::o3::CPU	inline
getInterrupts()	gem5::o3::CPU
getReg(PhysRegIdPtr phys_reg)	gem5::o3::CPU
getReg(PhysRegIdPtr phys_reg, void *val)	gem5::o3::CPU
getWritableArchReg(const RegId &reg, ThreadID tid)	gem5::o3::CPU
getWritableReg(PhysRegIdPtr phys_reg)	gem5::o3::CPU
globalSeqNum	gem5::o3::CPU
halt()	gem5::o3::CPU	inline
haltContext(ThreadID tid) override	gem5::o3::CPU
Halted enum value	gem5::o3::CPU
htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause) override	gem5::o3::CPU
Idle enum value	gem5::o3::CPU
iew	gem5::o3::CPU	protected
IEWIdx enum value	gem5::o3::CPU
iewQueue	gem5::o3::CPU
init() override	gem5::o3::CPU
insertThread(ThreadID tid)	gem5::o3::CPU
instcount	gem5::o3::CPU
instDone(ThreadID tid, const DynInstPtr &inst)	gem5::o3::CPU
instList	gem5::o3::CPU
isa	gem5::o3::CPU	protected
isCpuDrained() const	gem5::o3::CPU	private
isDraining() const	gem5::o3::CPU	inline
isThreadExiting(ThreadID tid) const	gem5::o3::CPU
lastActivatedCycle	gem5::o3::CPU
lastRunningCycle	gem5::o3::CPU
ListIt typedef	gem5::o3::CPU
LSQRequest typedef	gem5::o3::CPU
mmu	gem5::o3::CPU
numActiveThreads()	gem5::o3::CPU	inline
NumStages enum value	gem5::o3::CPU
pcState(const PCStateBase &new_pc_state, ThreadID tid)	gem5::o3::CPU
pcState(ThreadID tid)	gem5::o3::CPU
ppDataAccessComplete	gem5::o3::CPU
ppInstAccessComplete	gem5::o3::CPU
processInterrupts(const Fault &interrupt)	gem5::o3::CPU
pushRequest(const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op=nullptr, const std::vector< bool > &byte_enable=std::vector< bool >())	gem5::o3::CPU	inline
readMiscReg(int misc_reg, ThreadID tid)	gem5::o3::CPU
readMiscRegNoEffect(int misc_reg, ThreadID tid) const	gem5::o3::CPU
regFile	gem5::o3::CPU	protected
regProbePoints() override	gem5::o3::CPU
removeFrontInst(const DynInstPtr &inst)	gem5::o3::CPU
removeInstsNotInROB(ThreadID tid)	gem5::o3::CPU
removeInstsThisCycle	gem5::o3::CPU
removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)	gem5::o3::CPU
removeList	gem5::o3::CPU
removeThread(ThreadID tid)	gem5::o3::CPU
rename	gem5::o3::CPU	protected
RenameIdx enum value	gem5::o3::CPU
renameMap	gem5::o3::CPU	protected
renameQueue	gem5::o3::CPU
rob	gem5::o3::CPU	protected
Running enum value	gem5::o3::CPU
scheduleThreadExitEvent(ThreadID tid)	gem5::o3::CPU
scheduleTickEvent(Cycles delay)	gem5::o3::CPU	inlineprivate
scoreboard	gem5::o3::CPU	protected
serializeThread(CheckpointOut &cp, ThreadID tid) const override	gem5::o3::CPU
setArchReg(const RegId &reg, RegVal val, ThreadID tid)	gem5::o3::CPU
setArchReg(const RegId &reg, const void *val, ThreadID tid)	gem5::o3::CPU
setMiscReg(int misc_reg, RegVal val, ThreadID tid)	gem5::o3::CPU
setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)	gem5::o3::CPU
setReg(PhysRegIdPtr phys_reg, RegVal val)	gem5::o3::CPU
setReg(PhysRegIdPtr phys_reg, const void *val)	gem5::o3::CPU
squashFromTC(ThreadID tid)	gem5::o3::CPU
squashInstIt(const ListIt &instIt, ThreadID tid)	gem5::o3::CPU
StageIdx enum name	gem5::o3::CPU
startup() override	gem5::o3::CPU
Status enum name	gem5::o3::CPU
suspendContext(ThreadID tid) override	gem5::o3::CPU
SwitchedOut enum value	gem5::o3::CPU
switchOut() override	gem5::o3::CPU
system	gem5::o3::CPU
takeOverFrom(BaseCPU *oldCPU) override	gem5::o3::CPU
tcBase(ThreadID tid)	gem5::o3::CPU	inline
thread	gem5::o3::CPU
ThreadContext class	gem5::o3::CPU	friend
threadExitEvent	gem5::o3::CPU	private
threadMap	gem5::o3::CPU
tick()	gem5::o3::CPU
tickEvent	gem5::o3::CPU	private
tids	gem5::o3::CPU
timeBuffer	gem5::o3::CPU
totalInsts() const override	gem5::o3::CPU
totalOps() const override	gem5::o3::CPU
trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)	gem5::o3::CPU
tryDrain()	gem5::o3::CPU	private
unscheduleTickEvent()	gem5::o3::CPU	inlineprivate
unserializeThread(CheckpointIn &cp, ThreadID tid) override	gem5::o3::CPU
updateThreadPriority()	gem5::o3::CPU
verifyMemoryMode() const override	gem5::o3::CPU
wakeCPU()	gem5::o3::CPU
wakeup(ThreadID tid) override	gem5::o3::CPU	virtual