gem5  v22.1.0.0
gem5::Gicv3CPUInterface Member List

This is the complete list of members for gem5::Gicv3CPUInterface, including all inherited members.

A3Vgem5::Gicv3CPUInterfaceprotected
A3Vgem5::Gicv3CPUInterface
ArmISA::ISA classgem5::Gicv3CPUInterfacefriend
assertWakeRequest(void)gem5::Gicv3CPUInterface
BaseISADevice()gem5::ArmISA::BaseISADevice
BitUnion32(ICH_LRC) Bitfield< 31gem5::Gicv3CPUInterface
BitUnion64(ICC_CTLR_EL1) Bitfield< 63gem5::Gicv3CPUInterfaceprotected
BitUnion64(ICH_HCR_EL2) Bitfield< 63gem5::Gicv3CPUInterface
bpr1(Gicv3::GroupId group)gem5::Gicv3CPUInterface
CBPRgem5::Gicv3CPUInterfaceprotected
CBPR_EL1NSgem5::Gicv3CPUInterfaceprotected
CBPR_EL1Sgem5::Gicv3CPUInterfaceprotected
clearPendingInterrupts(void)gem5::Gicv3CPUInterface
copy(Gicv3Registers *from, Gicv3Registers *to)gem5::Gicv3CPUInterface
cpuIdgem5::Gicv3CPUInterfaceprotected
currEL() constgem5::Gicv3CPUInterface
currentSection()gem5::Serializablestatic
deactivateIRQ(uint32_t intid, Gicv3::GroupId group)gem5::Gicv3CPUInterface
deassertWakeRequest(void)gem5::Gicv3CPUInterface
DFBgem5::Gicv3CPUInterfaceprotected
DIBgem5::Gicv3CPUInterfaceprotected
distributorgem5::Gicv3CPUInterfaceprotected
dropPriority(Gicv3::GroupId group)gem5::Gicv3CPUInterface
Engem5::Gicv3CPUInterface
Enablegem5::Gicv3CPUInterfaceprotected
Enablegem5::Gicv3CPUInterfaceprotected
EnableGrp1NSgem5::Gicv3CPUInterfaceprotected
EnableGrp1Sgem5::Gicv3CPUInterfaceprotected
EndBitUnion(ICC_CTLR_EL1) BitUnion64(ICC_CTLR_EL3) Bitfield< 63gem5::Gicv3CPUInterfaceprotected
EndBitUnion(ICC_CTLR_EL3) BitUnion64(ICC_IGRPEN0_EL1) Bitfield< 63gem5::Gicv3CPUInterfaceprotected
EndBitUnion(ICC_IGRPEN0_EL1) BitUnion64(ICC_IGRPEN1_EL1) Bitfield< 63gem5::Gicv3CPUInterfaceprotected
EndBitUnion(ICC_IGRPEN1_EL1) BitUnion64(ICC_IGRPEN1_EL3) Bitfield< 63gem5::Gicv3CPUInterfaceprotected
EndBitUnion(ICC_IGRPEN1_EL3) BitUnion64(ICC_SRE_EL1) Bitfield< 63gem5::Gicv3CPUInterfaceprotected
EndBitUnion(ICC_SRE_EL1) BitUnion64(ICC_SRE_EL2) Bitfield< 63gem5::Gicv3CPUInterfaceprotected
EndBitUnion(ICC_SRE_EL2) BitUnion64(ICC_SRE_EL3) Bitfield< 63gem5::Gicv3CPUInterfaceprotected
EndBitUnion(ICC_SRE_EL3) static const uint8_t PRIORITY_BITSgem5::Gicv3CPUInterfaceprotected
EndBitUnion(ICH_LR_EL2) static const uint64_t ICH_LR_EL2_STATE_INVALID=0gem5::Gicv3CPUInterfacepure virtual
EndBitUnion(ICH_LRC) BitUnion64(ICH_MISR_EL2) Bitfield< 63gem5::Gicv3CPUInterface
EndBitUnion(ICH_MISR_EL2) BitUnion64(ICH_VMCR_EL2) Bitfield< 63gem5::Gicv3CPUInterface
EndBitUnion(ICH_VMCR_EL2) BitUnion64(ICH_VTR_EL2) Bitfield< 63gem5::Gicv3CPUInterface
EndBitUnion(ICH_VTR_EL2) BitUnion64(ICV_CTLR_EL1) Bitfield< 63gem5::Gicv3CPUInterface
EOIgem5::Gicv3CPUInterface
EOIgem5::Gicv3CPUInterface
EOIgem5::Gicv3CPUInterface
EOIcountgem5::Gicv3CPUInterface
eoiMaintenanceInterruptStatus() constgem5::Gicv3CPUInterface
EOImodegem5::Gicv3CPUInterfaceprotected
EOImode_EL1NSgem5::Gicv3CPUInterfaceprotected
EOImode_EL1Sgem5::Gicv3CPUInterfaceprotected
EOImode_EL3gem5::Gicv3CPUInterfaceprotected
ExtRangegem5::Gicv3CPUInterfaceprotected
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
generateSGI(RegVal val, Gicv3::GroupId group)gem5::Gicv3CPUInterface
getHCREL2FMO() constgem5::Gicv3CPUInterface
getHCREL2IMO() constgem5::Gicv3CPUInterface
getHPPIR0() constgem5::Gicv3CPUInterface
getHPPIR1() constgem5::Gicv3CPUInterface
getHPPVILR() constgem5::Gicv3CPUInterface
gicgem5::Gicv3CPUInterfaceprotected
GIC_MIN_BPRgem5::Gicv3CPUInterfaceprotectedstatic
GIC_MIN_BPR_NSgem5::Gicv3CPUInterfaceprotectedstatic
GIC_MIN_VBPRgem5::Gicv3CPUInterfaceprotectedstatic
GICC_ABPR enum valuegem5::Gicv3CPUInterfaceprotected
GICC_AEOIR enum valuegem5::Gicv3CPUInterfaceprotected
GICC_AHPPIR enum valuegem5::Gicv3CPUInterfaceprotected
GICC_AIAR enum valuegem5::Gicv3CPUInterfaceprotected
GICC_APRgem5::Gicv3CPUInterfaceprotectedstatic
GICC_BPR enum valuegem5::Gicv3CPUInterfaceprotected
GICC_CTLR enum valuegem5::Gicv3CPUInterfaceprotected
GICC_EOIR enum valuegem5::Gicv3CPUInterfaceprotected
GICC_HPPI enum valuegem5::Gicv3CPUInterfaceprotected
GICC_IAR enum valuegem5::Gicv3CPUInterfaceprotected
GICC_IIDR enum valuegem5::Gicv3CPUInterfaceprotected
GICC_NSAPRgem5::Gicv3CPUInterfaceprotectedstatic
GICC_PMR enum valuegem5::Gicv3CPUInterfaceprotected
GICC_RPR enum valuegem5::Gicv3CPUInterfaceprotected
GICC_STATUSR enum valuegem5::Gicv3CPUInterfaceprotected
GICH_APRgem5::Gicv3CPUInterfaceprotectedstatic
GICH_EISR enum valuegem5::Gicv3CPUInterfaceprotected
GICH_ELRSR enum valuegem5::Gicv3CPUInterfaceprotected
GICH_HCR enum valuegem5::Gicv3CPUInterfaceprotected
GICH_LRgem5::Gicv3CPUInterfaceprotectedstatic
GICH_MISR enum valuegem5::Gicv3CPUInterfaceprotected
GICH_VMCR enum valuegem5::Gicv3CPUInterfaceprotected
GICH_VTR enum valuegem5::Gicv3CPUInterfaceprotected
Gicv3CPUInterface(Gicv3 *gic, ThreadContext *tc)gem5::Gicv3CPUInterface
Gicv3Distributor classgem5::Gicv3CPUInterfacefriend
Gicv3Redistributor classgem5::Gicv3CPUInterfacefriend
Groupgem5::Gicv3CPUInterface
Groupgem5::Gicv3CPUInterface
groupEnabled(Gicv3::GroupId group) constgem5::Gicv3CPUInterface
groupPriorityMask(Gicv3::GroupId group)gem5::Gicv3CPUInterface
haveEL(ArmISA::ExceptionLevel el) constgem5::Gicv3CPUInterface
havePendingInterrupts(void) constgem5::Gicv3CPUInterface
highestActiveGroup() constgem5::Gicv3CPUInterface
highestActivePriority() constgem5::Gicv3CPUInterface
hppigem5::Gicv3CPUInterfaceprotected
hppiCanPreempt()gem5::Gicv3CPUInterface
hppviCanPreempt(int lrIdx) constgem5::Gicv3CPUInterface
HWgem5::Gicv3CPUInterface
HWgem5::Gicv3CPUInterface
ICH_LR_EL2_STATE_ACTIVEgem5::Gicv3CPUInterfacestatic
ICH_LR_EL2_STATE_ACTIVE_PENDINGgem5::Gicv3CPUInterfacestatic
ICH_LR_EL2_STATE_PENDINGgem5::Gicv3CPUInterfacestatic
IDbitsgem5::Gicv3CPUInterfaceprotected
IDbitsgem5::Gicv3CPUInterface
init()gem5::Gicv3CPUInterface
inSecureState() constgem5::Gicv3CPUInterface
intSignalType(Gicv3::GroupId group) constgem5::Gicv3CPUInterface
isagem5::ArmISA::BaseISADeviceprotected
isAA64() constgem5::Gicv3CPUInterface
isEL3OrMon() constgem5::Gicv3CPUInterface
isEOISplitMode() constgem5::Gicv3CPUInterface
isSecureBelowEL3() constgem5::Gicv3CPUInterface
ListRegsgem5::Gicv3CPUInterface
LRENPgem5::Gicv3CPUInterface
LRENPIEgem5::Gicv3CPUInterface
maintenanceInterruptgem5::Gicv3CPUInterfaceprotected
maintenanceInterruptStatus() constgem5::Gicv3CPUInterface
nDSgem5::Gicv3CPUInterfaceprotected
NPgem5::Gicv3CPUInterface
NPIEgem5::Gicv3CPUInterface
pathgem5::Serializableprivatestatic
pINTIDgem5::Gicv3CPUInterface
pINTIDgem5::Gicv3CPUInterface
PMHEgem5::Gicv3CPUInterfaceprotected
PREbitsgem5::Gicv3CPUInterface
PRIbitsgem5::Gicv3CPUInterfaceprotected
PRIbitsgem5::Gicv3CPUInterface
Prioritygem5::Gicv3CPUInterface
Prioritygem5::Gicv3CPUInterface
readBankedMiscReg(ArmISA::MiscRegIndex misc_reg) constgem5::Gicv3CPUInterface
readMiscReg(int misc_reg) overridegem5::Gicv3CPUInterfacevirtual
redistributorgem5::Gicv3CPUInterfaceprotected
res0gem5::Gicv3CPUInterfaceprotected
res0_0gem5::Gicv3CPUInterfaceprotected
res0_0gem5::Gicv3CPUInterfaceprotected
res0_0gem5::Gicv3CPUInterface
res0_0gem5::Gicv3CPUInterface
res0_0gem5::Gicv3CPUInterface
res0_0gem5::Gicv3CPUInterface
res0_0gem5::Gicv3CPUInterface
res0_0gem5::Gicv3CPUInterface
res0_1gem5::Gicv3CPUInterfaceprotected
res0_1gem5::Gicv3CPUInterfaceprotected
res0_1gem5::Gicv3CPUInterface
res0_1gem5::Gicv3CPUInterface
res0_1gem5::Gicv3CPUInterface
res0_1gem5::Gicv3CPUInterface
res0_1gem5::Gicv3CPUInterface
res0_1gem5::Gicv3CPUInterface
res0_2gem5::Gicv3CPUInterfaceprotected
res0_2gem5::Gicv3CPUInterfaceprotected
res0_3gem5::Gicv3CPUInterfaceprotected
res1gem5::Gicv3CPUInterface
resetHppi(uint32_t intid)gem5::Gicv3CPUInterface
RMgem5::Gicv3CPUInterfaceprotected
RSSgem5::Gicv3CPUInterfaceprotected
SEISgem5::Gicv3CPUInterfaceprotected
SEISgem5::Gicv3CPUInterface
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::Gicv3CPUInterfacevirtual
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) constgem5::Gicv3CPUInterface
setISA(ISA *isa)gem5::ArmISA::BaseISADevicevirtual
setMiscReg(int misc_reg, RegVal val) overridegem5::Gicv3CPUInterfacevirtual
setThreadContext(ThreadContext *tc) overridegem5::Gicv3CPUInterfacevirtual
SREgem5::Gicv3CPUInterfaceprotected
Stategem5::Gicv3CPUInterface
TALL0gem5::Gicv3CPUInterface
TALL1gem5::Gicv3CPUInterface
TCgem5::Gicv3CPUInterface
tcgem5::Gicv3CPUInterfaceprotected
TDIRgem5::Gicv3CPUInterface
TDSgem5::Gicv3CPUInterface
TSEIgem5::Gicv3CPUInterface
Ugem5::Gicv3CPUInterface
UIEgem5::Gicv3CPUInterface
unserialize(CheckpointIn &cp) overridegem5::Gicv3CPUInterfacevirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
update()gem5::Gicv3CPUInterface
updateDistributor()gem5::Gicv3CPUInterface
VAckCtlgem5::Gicv3CPUInterface
VBPR0gem5::Gicv3CPUInterface
VBPR1gem5::Gicv3CPUInterface
VCBPRgem5::Gicv3CPUInterface
VENG0gem5::Gicv3CPUInterface
VENG1gem5::Gicv3CPUInterface
VEOIMgem5::Gicv3CPUInterface
VFIQEngem5::Gicv3CPUInterface
VGrp0Dgem5::Gicv3CPUInterface
VGrp0DIEgem5::Gicv3CPUInterface
VGrp0Egem5::Gicv3CPUInterface
VGrp0EIEgem5::Gicv3CPUInterface
VGrp1Dgem5::Gicv3CPUInterface
VGrp1DIEgem5::Gicv3CPUInterface
VGrp1Egem5::Gicv3CPUInterface
VGrp1EIEgem5::Gicv3CPUInterface
vINTIDgem5::Gicv3CPUInterface
VIRTUAL_NUM_LIST_REGSgem5::Gicv3CPUInterfaceprotectedstatic
VIRTUAL_PREEMPTION_BITSgem5::Gicv3CPUInterfaceprotectedstatic
VIRTUAL_PRIORITY_BITSgem5::Gicv3CPUInterfaceprotectedstatic
virtualActivateIRQ(uint32_t lrIdx)gem5::Gicv3CPUInterface
virtualDeactivateIRQ(int lrIdx)gem5::Gicv3CPUInterface
virtualDropPriority()gem5::Gicv3CPUInterface
virtualFindActive(uint32_t intid) constgem5::Gicv3CPUInterface
virtualGroupPriorityMask(Gicv3::GroupId group) constgem5::Gicv3CPUInterface
virtualHighestActivePriority() constgem5::Gicv3CPUInterface
virtualIncrementEOICount()gem5::Gicv3CPUInterface
virtualIsEOISplitMode() constgem5::Gicv3CPUInterface
virtualUpdate()gem5::Gicv3CPUInterface
VPMRgem5::Gicv3CPUInterface
~BaseISADevice()gem5::ArmISA::BaseISADeviceinlinevirtual
~Serializable()gem5::Serializablevirtual
Generated on Wed Dec 21 2022 10:23:17 for gem5 by doxygen 1.9.1