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gem5
v22.1.0.0
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#include <cmath>#include <cstdint>#include <sstream>#include <string>#include "arch/riscv/regs/float.hh"#include "arch/riscv/regs/int.hh"#include "base/types.hh"#include "cpu/reg_class.hh"#include "cpu/static_inst.hh"#include "cpu/thread_context.hh"#include "rvk.hh"Go to the source code of this file.
Namespaces | |
| gem5 | |
| Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223. | |
| gem5::RiscvISA | |
Functions | |
| template<typename T > | |
| bool | gem5::RiscvISA::isquietnan (T val) |
| template<> | |
| bool | gem5::RiscvISA::isquietnan< float > (float val) |
| template<> | |
| bool | gem5::RiscvISA::isquietnan< double > (double val) |
| template<typename T > | |
| bool | gem5::RiscvISA::issignalingnan (T val) |
| template<> | |
| bool | gem5::RiscvISA::issignalingnan< float > (float val) |
| template<> | |
| bool | gem5::RiscvISA::issignalingnan< double > (double val) |
| std::string | gem5::RiscvISA::registerName (RegId reg) |