vec_pred_reg.hh File Reference

#include <array>
#include <cassert>
#include <cstdint>
#include <string>
#include <type_traits>
#include <vector>
#include "base/cprintf.hh"
#include "base/types.hh"
#include "sim/serialize_handlers.hh"

Go to the source code of this file.

Classes
class	gem5::VecPredRegT< VecElem, NumElems, Packed, Const >
	Predicate register view. More...
class	gem5::VecPredRegContainer< NumBits, Packed >
	Generic predicate register container. More...
struct	gem5::ParseParam< VecPredRegContainer< NumBits, Packed > >
struct	gem5::ShowParam< VecPredRegContainer< NumBits, Packed > >
struct	gem5::DummyVecPredRegContainer
	Dummy type aliases and constants for architectures that do not implement vector predicate registers. More...
struct	gem5::ParseParam< DummyVecPredRegContainer >

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.

Functions
static std::ostream &	gem5::operator<< (std::ostream &os, const DummyVecPredRegContainer &d)