faults.hh File Reference

#include "cpu/null_static_inst.hh"
#include "cpu/static_inst.hh"
#include "sim/faults.hh"

Go to the source code of this file.

Classes
class	gem5::SparcISA::SparcFaultBase
struct	gem5::SparcISA::SparcFaultBase::FaultVals
class	gem5::SparcISA::SparcFault< T >
class	gem5::SparcISA::PowerOnReset
class	gem5::SparcISA::WatchDogReset
class	gem5::SparcISA::ExternallyInitiatedReset
class	gem5::SparcISA::SoftwareInitiatedReset
class	gem5::SparcISA::REDStateException
class	gem5::SparcISA::StoreError
class	gem5::SparcISA::InstructionAccessException
class	gem5::SparcISA::InstructionAccessError
class	gem5::SparcISA::IllegalInstruction
class	gem5::SparcISA::PrivilegedOpcode
class	gem5::SparcISA::FpDisabled
class	gem5::SparcISA::VecDisabled
class	gem5::SparcISA::FpExceptionIEEE754
class	gem5::SparcISA::FpExceptionOther
class	gem5::SparcISA::TagOverflow
class	gem5::SparcISA::CleanWindow
class	gem5::SparcISA::DivisionByZero
class	gem5::SparcISA::InternalProcessorError
class	gem5::SparcISA::InstructionInvalidTSBEntry
class	gem5::SparcISA::DataInvalidTSBEntry
class	gem5::SparcISA::DataAccessException
class	gem5::SparcISA::DataAccessError
class	gem5::SparcISA::DataAccessProtection
class	gem5::SparcISA::MemAddressNotAligned
class	gem5::SparcISA::LDDFMemAddressNotAligned
class	gem5::SparcISA::STDFMemAddressNotAligned
class	gem5::SparcISA::PrivilegedAction
class	gem5::SparcISA::LDQFMemAddressNotAligned
class	gem5::SparcISA::STQFMemAddressNotAligned
class	gem5::SparcISA::InstructionRealTranslationMiss
class	gem5::SparcISA::DataRealTranslationMiss
class	gem5::SparcISA::EnumeratedFault< T >
class	gem5::SparcISA::InterruptLevelN
class	gem5::SparcISA::HstickMatch
class	gem5::SparcISA::TrapLevelZero
class	gem5::SparcISA::InterruptVector
class	gem5::SparcISA::PAWatchpoint
class	gem5::SparcISA::VAWatchpoint
class	gem5::SparcISA::FastInstructionAccessMMUMiss
class	gem5::SparcISA::FastDataAccessMMUMiss
class	gem5::SparcISA::FastDataAccessProtection
class	gem5::SparcISA::InstructionBreakpoint
class	gem5::SparcISA::CpuMondo
class	gem5::SparcISA::DevMondo
class	gem5::SparcISA::ResumableError
class	gem5::SparcISA::SpillNNormal
class	gem5::SparcISA::SpillNOther
class	gem5::SparcISA::FillNNormal
class	gem5::SparcISA::FillNOther
class	gem5::SparcISA::TrapInstruction

Namespaces
namespace	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
namespace	gem5::SparcISA

Typedefs
typedef uint32_t	gem5::SparcISA::TrapType
typedef uint32_t	gem5::SparcISA::FaultPriority

Functions
void	gem5::SparcISA::enterREDState (ThreadContext *tc)
	This causes the thread context to enter RED state.
void	gem5::SparcISA::doREDFault (ThreadContext *tc, TrapType tt)
	This sets everything up for a RED state trap except for actually jumping to the handler.
void	gem5::SparcISA::doNormalFault (ThreadContext *tc, TrapType tt, bool gotoHpriv)
	This sets everything up for a normal trap except for actually jumping to the handler.
void	gem5::SparcISA::getREDVector (RegVal TT, Addr &PC, Addr &NPC)
void	gem5::SparcISA::getHyperVector (ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT)
void	gem5::SparcISA::getPrivVector (ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT, RegVal TL)