interrupt_handler.hh File Reference

#include <bitset>
#include <iostream>
#include <queue>
#include <vector>
#include "base/addr_range.hh"
#include "base/flags.hh"
#include "base/types.hh"
#include "dev/amdgpu/amdgpu_device.hh"
#include "dev/dma_device.hh"
#include "params/AMDGPUInterruptHandler.hh"

Go to the source code of this file.

Classes
struct	gem5::AMDGPUInterruptCookie
struct	gem5::AMDGPUIHRegs
	Struct to contain all interrupt handler related registers. More...
class	gem5::AMDGPUInterruptHandler
class	gem5::AMDGPUInterruptHandler::DmaEvent
struct	gem5::AMDGPUInterruptHandler::SenderState

Namespaces
namespace	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.

Enumerations
enum	gem5::soc15_ih_clientid {   gem5::SOC15_IH_CLIENTID_RLC = 0x07 , gem5::SOC15_IH_CLIENTID_SDMA0 = 0x08 , gem5::SOC15_IH_CLIENTID_SDMA1 = 0x09 , gem5::SOC15_IH_CLIENTID_SDMA2 = 0x01 ,   gem5::SOC15_IH_CLIENTID_SDMA3 = 0x04 , gem5::SOC15_IH_CLIENTID_SDMA4 = 0x05 , gem5::SOC15_IH_CLIENTID_SDMA5 = 0x11 , gem5::SOC15_IH_CLIENTID_SDMA6 = 0x13 ,   gem5::SOC15_IH_CLIENTID_SDMA7 = 0x18 , gem5::SOC15_IH_CLIENTID_GRBM_CP = 0x14 }
	Defines from driver code. More...
enum	gem5::ihSourceId { gem5::CP_EOP = 181 , gem5::TRAP_ID = 224 }

Variables
constexpr uint32_t	gem5::INTR_COOKIE_SIZE = 32
	MSI-style interrupts.