utility.hh File Reference

#include <cmath>
#include <cstdint>
#include <sstream>
#include <string>
#include "arch/riscv/regs/float.hh"
#include "arch/riscv/regs/int.hh"
#include "base/types.hh"
#include "cpu/reg_class.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "enums/RiscvType.hh"
#include "rvk.hh"

Go to the source code of this file.

Namespaces
namespace	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
namespace	gem5::RiscvISA

Functions
template<typename T >
bool	gem5::RiscvISA::isquietnan (T val)
template<>
bool	gem5::RiscvISA::isquietnan< float > (float val)
template<>
bool	gem5::RiscvISA::isquietnan< double > (double val)
template<typename T >
bool	gem5::RiscvISA::issignalingnan (T val)
template<>
bool	gem5::RiscvISA::issignalingnan< float > (float val)
template<>
bool	gem5::RiscvISA::issignalingnan< double > (double val)
std::string	gem5::RiscvISA::registerName (RegId reg)
uint32_t	gem5::RiscvISA::mulhu_32 (uint32_t rs1, uint32_t rs2)
uint64_t	gem5::RiscvISA::mulhu_64 (uint64_t rs1, uint64_t rs2)
int32_t	gem5::RiscvISA::mulh_32 (int32_t rs1, int32_t rs2)
int64_t	gem5::RiscvISA::mulh_64 (int64_t rs1, int64_t rs2)
int32_t	gem5::RiscvISA::mulhsu_32 (int32_t rs1, uint32_t rs2)
int64_t	gem5::RiscvISA::mulhsu_64 (int64_t rs1, uint64_t rs2)
template<typename T >
T	gem5::RiscvISA::div (T rs1, T rs2)
template<typename T >
T	gem5::RiscvISA::divu (T rs1, T rs2)
template<typename T >
T	gem5::RiscvISA::rem (T rs1, T rs2)
template<typename T >
T	gem5::RiscvISA::remu (T rs1, T rs2)