int.hh File Reference

#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"
#include "base/logging.hh"
#include "cpu/reg_class.hh"
#include "debug/IntRegs.hh"

Go to the source code of this file.

Classes
class	gem5::X86ISA::FlatIntRegClassOps
class	gem5::X86ISA::IntRegClassOps

Namespaces
namespace	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
namespace	gem5::X86ISA
	This is exposed globally, independent of the ISA.
namespace	gem5::X86ISA::int_reg

Functions
	gem5::X86ISA::BitUnion64 (X86IntReg) Bitfield< 63
	gem5::X86ISA::EndBitUnion (X86IntReg) namespace int_reg
static constexpr RegId	gem5::X86ISA::intRegMicro (int index)
static constexpr RegId	gem5::X86ISA::intRegFolded (RegIndex index, RegIndex foldBit)

Variables
	gem5::X86ISA::R
SignedBitfield< 63, 0 >	gem5::X86ISA::SR
Bitfield< 31, 0 >	gem5::X86ISA::E
SignedBitfield< 31, 0 >	gem5::X86ISA::SE
Bitfield< 15, 0 >	gem5::X86ISA::X
SignedBitfield< 15, 0 >	gem5::X86ISA::SX
Bitfield< 15, 8 >	gem5::X86ISA::H
SignedBitfield< 15, 8 >	gem5::X86ISA::SH
Bitfield< 7, 0 >	gem5::X86ISA::L
SignedBitfield< 7, 0 >	gem5::X86ISA::SL
constexpr FlatIntRegClassOps	gem5::X86ISA::flatIntRegClassOps
constexpr RegClass	gem5::X86ISA::flatIntRegClass
constexpr IntRegClassOps	gem5::X86ISA::intRegClassOps
constexpr RegClass	gem5::X86ISA::intRegClass
constexpr RegId	gem5::X86ISA::int_reg::Rax = intRegClass[_RaxIdx]
constexpr RegId	gem5::X86ISA::int_reg::Rcx = intRegClass[_RcxIdx]
constexpr RegId	gem5::X86ISA::int_reg::Rdx = intRegClass[_RdxIdx]
constexpr RegId	gem5::X86ISA::int_reg::Rbx = intRegClass[_RbxIdx]
constexpr RegId	gem5::X86ISA::int_reg::Rsp = intRegClass[_RspIdx]
constexpr RegId	gem5::X86ISA::int_reg::Rbp = intRegClass[_RbpIdx]
constexpr RegId	gem5::X86ISA::int_reg::Rsi = intRegClass[_RsiIdx]
constexpr RegId	gem5::X86ISA::int_reg::Rdi = intRegClass[_RdiIdx]
constexpr RegId	gem5::X86ISA::int_reg::R8 = intRegClass[_R8Idx]
constexpr RegId	gem5::X86ISA::int_reg::R9 = intRegClass[_R9Idx]
constexpr RegId	gem5::X86ISA::int_reg::R10 = intRegClass[_R10Idx]
constexpr RegId	gem5::X86ISA::int_reg::R11 = intRegClass[_R11Idx]
constexpr RegId	gem5::X86ISA::int_reg::R12 = intRegClass[_R12Idx]
constexpr RegId	gem5::X86ISA::int_reg::R13 = intRegClass[_R13Idx]
constexpr RegId	gem5::X86ISA::int_reg::R14 = intRegClass[_R14Idx]
constexpr RegId	gem5::X86ISA::int_reg::R15 = intRegClass[_R15Idx]
constexpr RegId	gem5::X86ISA::int_reg::T0 = intRegClass[_T0Idx]
constexpr RegId	gem5::X86ISA::int_reg::Prodlow = intRegClass[_ProdlowIdx]
constexpr RegId	gem5::X86ISA::int_reg::Prodhi = intRegClass[_ProdhiIdx]
constexpr RegId	gem5::X86ISA::int_reg::Quotient = intRegClass[_QuotientIdx]
constexpr RegId	gem5::X86ISA::int_reg::Remainder = intRegClass[_RemainderIdx]
constexpr RegId	gem5::X86ISA::int_reg::Divisor = intRegClass[_DivisorIdx]
constexpr RegId	gem5::X86ISA::int_reg::Doublebits = intRegClass[_DoublebitsIdx]
constexpr auto &	gem5::X86ISA::int_reg::Eax = Rax
constexpr auto &	gem5::X86ISA::int_reg::Ax = Rax
constexpr auto &	gem5::X86ISA::int_reg::Al = Rax
constexpr auto &	gem5::X86ISA::int_reg::Ecx = Rcx
constexpr auto &	gem5::X86ISA::int_reg::Cx = Rcx
constexpr auto &	gem5::X86ISA::int_reg::Cl = Rcx
constexpr auto &	gem5::X86ISA::int_reg::Edx = Rdx
constexpr auto &	gem5::X86ISA::int_reg::Dx = Rdx
constexpr auto &	gem5::X86ISA::int_reg::Dl = Rdx
constexpr auto &	gem5::X86ISA::int_reg::Ebx = Rbx
constexpr auto &	gem5::X86ISA::int_reg::Bx = Rbx
constexpr auto &	gem5::X86ISA::int_reg::Bl = Rbx
constexpr auto &	gem5::X86ISA::int_reg::Esp = Rsp
constexpr auto &	gem5::X86ISA::int_reg::Sp = Rsp
constexpr auto &	gem5::X86ISA::int_reg::Spl = Rsp
constexpr auto &	gem5::X86ISA::int_reg::Ah = Rsp
constexpr auto &	gem5::X86ISA::int_reg::Ebp = Rbp
constexpr auto &	gem5::X86ISA::int_reg::Bp = Rbp
constexpr auto &	gem5::X86ISA::int_reg::Bpl = Rbp
constexpr auto &	gem5::X86ISA::int_reg::Ch = Rbp
constexpr auto &	gem5::X86ISA::int_reg::Esi = Rsi
constexpr auto &	gem5::X86ISA::int_reg::Si = Rsi
constexpr auto &	gem5::X86ISA::int_reg::Sil = Rsi
constexpr auto &	gem5::X86ISA::int_reg::Dh = Rsi
constexpr auto &	gem5::X86ISA::int_reg::Edi = Rdi
constexpr auto &	gem5::X86ISA::int_reg::Di = Rdi
constexpr auto &	gem5::X86ISA::int_reg::Dil = Rdi
constexpr auto &	gem5::X86ISA::int_reg::Bh = Rdi
constexpr auto &	gem5::X86ISA::int_reg::R8d = R8
constexpr auto &	gem5::X86ISA::int_reg::R8w = R8
constexpr auto &	gem5::X86ISA::int_reg::R8b = R8
constexpr auto &	gem5::X86ISA::int_reg::R9d = R9
constexpr auto &	gem5::X86ISA::int_reg::R9w = R9
constexpr auto &	gem5::X86ISA::int_reg::R9b = R9
constexpr auto &	gem5::X86ISA::int_reg::R10d = R10
constexpr auto &	gem5::X86ISA::int_reg::R10w = R10
constexpr auto &	gem5::X86ISA::int_reg::R10b = R10
constexpr auto &	gem5::X86ISA::int_reg::R11d = R11
constexpr auto &	gem5::X86ISA::int_reg::R11w = R11
constexpr auto &	gem5::X86ISA::int_reg::R11b = R11
constexpr auto &	gem5::X86ISA::int_reg::R12d = R12
constexpr auto &	gem5::X86ISA::int_reg::R12w = R12
constexpr auto &	gem5::X86ISA::int_reg::R12b = R12
constexpr auto &	gem5::X86ISA::int_reg::R13d = R13
constexpr auto &	gem5::X86ISA::int_reg::R13w = R13
constexpr auto &	gem5::X86ISA::int_reg::R13b = R13
constexpr auto &	gem5::X86ISA::int_reg::R14d = R14
constexpr auto &	gem5::X86ISA::int_reg::R14w = R14
constexpr auto &	gem5::X86ISA::int_reg::R14b = R14
constexpr auto &	gem5::X86ISA::int_reg::R15d = R15
constexpr auto &	gem5::X86ISA::int_reg::R15w = R15
constexpr auto &	gem5::X86ISA::int_reg::R15b = R15
constexpr RegIndex	gem5::X86ISA::IntFoldBit = 1 << 6