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arch
amdgpu
vega
pagetable.cc
Go to the documentation of this file.
1
/*
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* Copyright (c) 2021 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
arch/amdgpu/vega/pagetable.hh
"
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#include "
sim/serialize.hh
"
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namespace
gem5
37
{
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namespace
VegaISA
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{
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void
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VegaTlbEntry::serialize
(
CheckpointOut
&cp)
const
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{
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SERIALIZE_SCALAR
(paddr);
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SERIALIZE_SCALAR
(
vaddr
);
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SERIALIZE_SCALAR
(logBytes);
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SERIALIZE_SCALAR
(vmid);
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SERIALIZE_SCALAR
(pte);
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SERIALIZE_SCALAR
(lruSeq);
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}
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60
void
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VegaTlbEntry::unserialize
(CheckpointIn &cp)
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{
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UNSERIALIZE_SCALAR
(paddr);
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UNSERIALIZE_SCALAR
(
vaddr
);
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UNSERIALIZE_SCALAR
(logBytes);
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UNSERIALIZE_SCALAR
(vmid);
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UNSERIALIZE_SCALAR
(pte);
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UNSERIALIZE_SCALAR
(lruSeq);
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}
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}
// namespace VegaISA
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}
// namespace gem5
gem5::unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition:
thread_context.cc:222
serialize.hh
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition:
serialize.hh:575
gem5::serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition:
thread_context.cc:194
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition:
serialize.hh:568
pagetable.hh
gem5::CheckpointOut
std::ostream CheckpointOut
Definition:
serialize.hh:66
gem5::MipsISA::vaddr
vaddr
Definition:
pra_constants.hh:278
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition:
gpu_translation_state.hh:37
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