inst_util.hh File Reference

#include <cmath>
#include "arch/amdgpu/gcn3/gpu_registers.hh"

Go to the source code of this file.

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
	gem5::Gcn3ISA
	classes that represnt vector/scalar operands in GCN3 ISA.

Enumerations
enum	gem5::SDWASelVals : int {   gem5::SDWA_BYTE_0 = 0, gem5::SDWA_BYTE_1 = 1, gem5::SDWA_BYTE_2 = 2, gem5::SDWA_BYTE_3 = 3,   gem5::SDWA_WORD_0 = 4, gem5::SDWA_WORD_1 = 5, gem5::SDWA_DWORD = 6, gem5::SDWA_BYTE_0 = 0,   gem5::SDWA_BYTE_1 = 1, gem5::SDWA_BYTE_2 = 2, gem5::SDWA_BYTE_3 = 3, gem5::SDWA_WORD_0 = 4,   gem5::SDWA_WORD_1 = 5, gem5::SDWA_DWORD = 6 }
enum	gem5::SDWADstVals : int {   gem5::SDWA_UNUSED_PAD = 0, gem5::SDWA_UNUSED_SEXT = 1, gem5::SDWA_UNUSED_PRESERVE = 2, gem5::SDWA_UNUSED_PAD = 0,   gem5::SDWA_UNUSED_SEXT = 1, gem5::SDWA_UNUSED_PRESERVE = 2 }
enum	gem5::SqDPPVals : int {   gem5::SQ_DPP_QUAD_PERM_MAX = 0xFF, gem5::SQ_DPP_RESERVED = 0x100, gem5::SQ_DPP_ROW_SL1 = 0x101, gem5::SQ_DPP_ROW_SL15 = 0x10F,   gem5::SQ_DPP_ROW_SR1 = 0x111, gem5::SQ_DPP_ROW_SR15 = 0x11F, gem5::SQ_DPP_ROW_RR1 = 0x121, gem5::SQ_DPP_ROW_RR15 = 0x12F,   gem5::SQ_DPP_WF_SL1 = 0x130, gem5::SQ_DPP_WF_RL1 = 0x134, gem5::SQ_DPP_WF_SR1 = 0x138, gem5::SQ_DPP_WF_RR1 = 0x13C,   gem5::SQ_DPP_ROW_MIRROR = 0x140, gem5::SQ_DPP_ROW_HALF_MIRROR = 0x141, gem5::SQ_DPP_ROW_BCAST15 = 0x142, gem5::SQ_DPP_ROW_BCAST31 = 0x143,   gem5::SQ_DPP_QUAD_PERM_MAX = 0xFF, gem5::SQ_DPP_RESERVED = 0x100, gem5::SQ_DPP_ROW_SL1 = 0x101, gem5::SQ_DPP_ROW_SL15 = 0x10F,   gem5::SQ_DPP_ROW_SR1 = 0x111, gem5::SQ_DPP_ROW_SR15 = 0x11F, gem5::SQ_DPP_ROW_RR1 = 0x121, gem5::SQ_DPP_ROW_RR15 = 0x12F,   gem5::SQ_DPP_WF_SL1 = 0x130, gem5::SQ_DPP_WF_RL1 = 0x134, gem5::SQ_DPP_WF_SR1 = 0x138, gem5::SQ_DPP_WF_RR1 = 0x13C,   gem5::SQ_DPP_ROW_MIRROR = 0x140, gem5::SQ_DPP_ROW_HALF_MIRROR = 0x141, gem5::SQ_DPP_ROW_BCAST15 = 0x142, gem5::SQ_DPP_ROW_BCAST31 = 0x143 }

Functions
template<typename T >
T	gem5::Gcn3ISA::wholeQuadMode (T val)
template<typename T >
T	gem5::Gcn3ISA::quadMask (T val)
template<typename T >
ScalarRegI32	gem5::Gcn3ISA::countZeroBits (T val)
template<typename T >
ScalarRegI32	gem5::Gcn3ISA::findFirstZero (T val)
template<typename T >
ScalarRegI32	gem5::Gcn3ISA::findFirstOne (T val)
template<typename T >
ScalarRegI32	gem5::Gcn3ISA::findFirstOneMsb (T val)
template<typename T >
ScalarRegI32	gem5::Gcn3ISA::countZeroBitsMsb (T val)
ScalarRegI32	gem5::Gcn3ISA::firstOppositeSignBit (ScalarRegI32 val)
ScalarRegI32	gem5::Gcn3ISA::firstOppositeSignBit (ScalarRegI64 val)
template<typename T >
T	gem5::Gcn3ISA::median (T val_0, T val_1, T val_2)
template<typename T >
T	gem5::Gcn3ISA::roundNearestEven (T val)
VecElemU32	gem5::Gcn3ISA::muladd (VecElemU64 &dst, VecElemU32 val_0, VecElemU32 val_1, VecElemU64 val_2)
VecElemU32	gem5::Gcn3ISA::muladd (VecElemI64 &dst, VecElemI32 val_0, VecElemI32 val_1, VecElemI64 val_2)
int	gem5::Gcn3ISA::dppInstImpl (SqDPPVals dppCtrl, int currLane, int rowNum, int rowOffset, bool &outOfBounds)
	dppInstImpl is a helper function that performs the inputted operation on the inputted vector register lane. More...
template<typename T >
void	gem5::Gcn3ISA::processDPP (GPUDynInstPtr gpuDynInst, InFmt_VOP_DPP dppInst, T &src0)
	processDPP is a helper function for implementing Data Parallel Primitive instructions. More...
template<typename T >
void	gem5::Gcn3ISA::processDPP (GPUDynInstPtr gpuDynInst, InFmt_VOP_DPP dppInst, T &src0, T &src1)
	processDPP is a helper function for implementing Data Parallel Primitive instructions. More...
template<typename T >
T	gem5::Gcn3ISA::sdwaInstSrcImpl_helper (T currOperVal, const T origOperVal, const SDWASelVals sel, const bool signExt)
	sdwaInstSrcImpl_helper contains the per-lane code for selecting the appropriate bytes/words of the lane and doing the appropriate masking/padding/sign extending. More...
template<typename T >
void	gem5::Gcn3ISA::sdwaInstSrcImpl (T &currOper, T &origCurrOper, const SDWASelVals sel, const bool signExt)
	sdwaInstSrcImpl is a helper function that selects the appropriate bits/bytes for each lane of the inputted source operand of an SDWA instruction, does the appropriate masking/padding/sign extending for the non-selected bits/bytes, and updates the operands values with the resultant value. More...
template<typename T >
T	gem5::Gcn3ISA::sdwaInstDstImpl_helper (T currDstVal, const T origDstVal, const bool clamp, const SDWASelVals sel, const SDWADstVals unusedBits_format)
	sdwaInstDstImpl_helper contains the per-lane code for selecting the appropriate bytes/words of the lane and doing the appropriate masking/padding/sign extending. More...
template<typename T >
void	gem5::Gcn3ISA::sdwaInstDstImpl (T &dstOper, T &origDstOper, const bool clamp, const SDWASelVals sel, const SDWADstVals unusedBits_format)
	sdwaInstDestImpl is a helper function that selects the appropriate bits/bytes for the inputted dest operand of an SDWA instruction, does the appropriate masking/padding/sign extending for the non-selected bits/bytes, and updates the operands values with the resultant value. More...
template<typename T >
void	gem5::Gcn3ISA::processSDWA_src_helper (T &currSrc, T &origCurrSrc, const SDWASelVals src_sel, const bool src_signExt, const bool src_abs, const bool src_neg)
	processSDWA_srcHelper is a helper function for implementing sub d-word addressing instructions for the src operands. More...
template<typename T >
void	gem5::Gcn3ISA::processSDWA_src (InFmt_VOP_SDWA sdwaInst, T &src0, T &origSrc0)
	processSDWA_src is a helper function for implementing sub d-word addressing instructions for the src operands. More...
template<typename T >
void	gem5::Gcn3ISA::processSDWA_src (InFmt_VOP_SDWA sdwaInst, T &src0, T &origSrc0, T &src1, T &origSrc1)
	processSDWA_src is a helper function for implementing sub d-word addressing instructions. More...
template<typename T >
void	gem5::Gcn3ISA::processSDWA_dst (InFmt_VOP_SDWA sdwaInst, T &dst, T &origDst)
	processSDWA_dst is a helper function for implementing sub d-word addressing instructions for the dst operand. More...

Variables
static const int	gem5::ROW_SIZE = 16
static const int	gem5::NUM_BANKS = 4