gem5
[DEVELOP-FOR-23.0]
|
Public Attributes | |
uint16_t | fcw |
uint16_t | fsw |
uint8_t | ftwx |
uint8_t | pad0 |
uint16_t | last_opcode |
union { | |
struct { | |
uint32_t fpu_ip | |
uint16_t fpu_cs | |
uint16_t pad1 | |
uint32_t fpu_dp | |
uint16_t fpu_ds | |
uint16_t pad2 | |
} ctrl32 | |
struct { | |
uint64_t fpu_ip | |
uint64_t fpu_dp | |
} ctrl64 | |
}; | |
uint32_t | mxcsr |
uint32_t | mxcsr_mask |
uint8_t | fpr [8][16] |
uint8_t | xmm [16][16] |
uint64_t | reserved [12] |
Definition at line 76 of file x86_cpu.cc.
union { ... } |
struct { ... } gem5::FXSave::ctrl32 |
struct { ... } gem5::FXSave::ctrl64 |
Referenced by gem5::X86KvmCPU::updateThreadContextXSave().
uint16_t gem5::FXSave::fcw |
Definition at line 78 of file x86_cpu.cc.
uint8_t gem5::FXSave::fpr[8][16] |
Definition at line 104 of file x86_cpu.cc.
uint16_t gem5::FXSave::fpu_cs |
Definition at line 88 of file x86_cpu.cc.
uint32_t gem5::FXSave::fpu_dp |
Definition at line 90 of file x86_cpu.cc.
uint64_t gem5::FXSave::fpu_dp |
Definition at line 98 of file x86_cpu.cc.
uint16_t gem5::FXSave::fpu_ds |
Definition at line 91 of file x86_cpu.cc.
uint32_t gem5::FXSave::fpu_ip |
Definition at line 87 of file x86_cpu.cc.
uint64_t gem5::FXSave::fpu_ip |
Definition at line 97 of file x86_cpu.cc.
uint16_t gem5::FXSave::fsw |
Definition at line 79 of file x86_cpu.cc.
uint8_t gem5::FXSave::ftwx |
Definition at line 80 of file x86_cpu.cc.
uint16_t gem5::FXSave::last_opcode |
Definition at line 82 of file x86_cpu.cc.
uint32_t gem5::FXSave::mxcsr |
Definition at line 101 of file x86_cpu.cc.
uint32_t gem5::FXSave::mxcsr_mask |
Definition at line 102 of file x86_cpu.cc.
uint8_t gem5::FXSave::pad0 |
Definition at line 81 of file x86_cpu.cc.
uint16_t gem5::FXSave::pad1 |
Definition at line 89 of file x86_cpu.cc.
uint16_t gem5::FXSave::pad2 |
Definition at line 92 of file x86_cpu.cc.
uint64_t gem5::FXSave::reserved[12] |
Definition at line 107 of file x86_cpu.cc.
uint8_t gem5::FXSave::xmm[16][16] |
Definition at line 105 of file x86_cpu.cc.