gem5  v22.1.0.0
stimulus.h
Go to the documentation of this file.
1 /*****************************************************************************
2 
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements. See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License. You may obtain a copy of the License at
9 
10  http://www.apache.org/licenses/LICENSE-2.0
11 
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied. See the License for the specific language governing
16  permissions and limitations under the License.
17 
18  *****************************************************************************/
19 
20 /*****************************************************************************
21 
22  stimulus.h --
23 
24  Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 
39 #include "common.h"
40 
41 SC_MODULE( stimulus )
42 {
43  SC_HAS_PROCESS( stimulus );
44 
45  sc_in_clk clk;
46 
47  sc_signal<bool>& reset ;
48  sc_signal_bool_vector2& out_value1; // Output port
49  sc_signal_bool_vector2& out_value2; // Output port
50  sc_signal_bool_vector3& out_value3; // Output port
51  sc_signal_bool_vector3& out_value4; // Output port
52  sc_signal<bool>& out_valid; // Output port
53  const sc_signal<bool>& in_ack;
54 
55  //
56  // Constructor
57  //
58 
59  stimulus(
60  sc_module_name NAME, // reference name
61  sc_clock& CLK, // clock
62  sc_signal<bool>& RESET,
63  sc_signal_bool_vector2& OUT_VALUE1,
64  sc_signal_bool_vector2& OUT_VALUE2,
65  sc_signal_bool_vector3& OUT_VALUE3,
66  sc_signal_bool_vector3& OUT_VALUE4,
67  sc_signal<bool>& OUT_VALID,
68  const sc_signal<bool>& IN_ACK
69  )
70  :
71  reset (RESET),
72  out_value1 (OUT_VALUE1),
73  out_value2 (OUT_VALUE2),
74  out_value3 (OUT_VALUE3),
75  out_value4 (OUT_VALUE4),
76  out_valid (OUT_VALID),
77  in_ack (IN_ACK)
78  {
79  clk (CLK);
80  SC_CTHREAD( entry, clk.pos() );
81  };
82  void entry();
83 };
84 // EOF
SC_MODULE(stimulus)
Definition: stimulus.h:40
sc_signal< sc_bv< 3 > > sc_signal_bool_vector3
Definition: common.h:44
sc_signal< sc_bv< 2 > > sc_signal_bool_vector2
Definition: common.h:43
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:323
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:301

Generated on Wed Dec 21 2022 10:22:45 for gem5 by doxygen 1.9.1