gem5  v21.1.0.2
gem5::CheckerThreadContext< TC > Member List

This is the complete list of members for gem5::CheckerThreadContext< TC >, including all inherited members.

activate() overridegem5::CheckerThreadContext< TC >inlinevirtual
Active enum valuegem5::ThreadContext
actualTCgem5::CheckerThreadContext< TC >private
checkerCPUgem5::CheckerThreadContext< TC >private
checkerTCgem5::CheckerThreadContext< TC >private
CheckerThreadContext(TC *actual_tc, CheckerCPU *checker_cpu)gem5::CheckerThreadContext< TC >inline
clearArchRegs() overridegem5::CheckerThreadContext< TC >inlinevirtual
compare(ThreadContext *one, ThreadContext *two)gem5::ThreadContextstatic
connectMemPorts(ThreadContext *tc)gem5::CheckerThreadContext< TC >inline
contextId() const overridegem5::CheckerThreadContext< TC >inlinevirtual
copyArchRegs(ThreadContext *tc) overridegem5::CheckerThreadContext< TC >inlinevirtual
cpuId() const overridegem5::CheckerThreadContext< TC >inlinevirtual
DefaultFloatResultgem5::ThreadContextstatic
DefaultIntResultgem5::ThreadContextstatic
descheduleInstCountEvent(Event *event) overridegem5::CheckerThreadContext< TC >inlinevirtual
exit()gem5::ThreadContextinlinevirtual
flattenRegId(const RegId &regId) const overridegem5::CheckerThreadContext< TC >inlinevirtual
floatResultgem5::ThreadContext
floatsgem5::ThreadContextstatic
getCheckerCpuPtr() overridegem5::CheckerThreadContext< TC >inlinevirtual
getCpuPtr() overridegem5::CheckerThreadContext< TC >inlinevirtual
getCurrentInstCount() overridegem5::CheckerThreadContext< TC >inlinevirtual
getDecoderPtr() overridegem5::CheckerThreadContext< TC >inlinevirtual
getHtmCheckpointPtr() overridegem5::CheckerThreadContext< TC >inlinevirtual
getIsaPtr() overridegem5::CheckerThreadContext< TC >inlinevirtual
getMMUPtr() overridegem5::CheckerThreadContext< TC >inlinevirtual
getProcessPtr() overridegem5::CheckerThreadContext< TC >inlinevirtual
getSystemPtr() overridegem5::CheckerThreadContext< TC >inlinevirtual
getUseForClone()gem5::ThreadContextinline
getVirtProxy() overridegem5::CheckerThreadContext< TC >inlinevirtual
getWritableVecPredReg(const RegId &reg) overridegem5::CheckerThreadContext< TC >inlinevirtual
getWritableVecPredRegFlat(RegIndex idx) overridegem5::CheckerThreadContext< TC >inlinevirtual
getWritableVecReg(const RegId &reg) overridegem5::CheckerThreadContext< TC >inlinevirtual
getWritableVecRegFlat(RegIndex idx) overridegem5::CheckerThreadContext< TC >inlinevirtual
halt() overridegem5::CheckerThreadContext< TC >inlinevirtual
Halted enum valuegem5::ThreadContext
Halting enum valuegem5::ThreadContext
htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) overridegem5::CheckerThreadContext< TC >inlinevirtual
initMemProxies(ThreadContext *tc) overridegem5::CheckerThreadContext< TC >inlinevirtual
instAddr() const overridegem5::CheckerThreadContext< TC >inlinevirtual
intOffsetgem5::ThreadContext
intResultgem5::ThreadContext
intsgem5::ThreadContextstatic
microPC() const overridegem5::CheckerThreadContext< TC >inlinevirtual
nextInstAddr() const overridegem5::CheckerThreadContext< TC >inlinevirtual
pcState() const overridegem5::CheckerThreadContext< TC >inlinevirtual
pcState(const TheISA::PCState &val) overridegem5::CheckerThreadContext< TC >inlinevirtual
pcStateNoRecord(const TheISA::PCState &val) overridegem5::CheckerThreadContext< TC >inlinevirtual
quiesce()gem5::ThreadContext
quiesceTick(Tick resume)gem5::ThreadContext
readCCReg(RegIndex reg_idx) const overridegem5::CheckerThreadContext< TC >inlinevirtual
readCCRegFlat(RegIndex idx) const overridegem5::CheckerThreadContext< TC >inlinevirtual
readFloatReg(RegIndex reg_idx) const overridegem5::CheckerThreadContext< TC >inlinevirtual
readFloatRegFlat(RegIndex idx) const overridegem5::CheckerThreadContext< TC >inlinevirtual
readIntReg(RegIndex reg_idx) const overridegem5::CheckerThreadContext< TC >inlinevirtual
readIntRegFlat(RegIndex idx) const overridegem5::CheckerThreadContext< TC >inlinevirtual
readLastActivate() overridegem5::CheckerThreadContext< TC >inlinevirtual
readLastSuspend() overridegem5::CheckerThreadContext< TC >inlinevirtual
readMiscReg(RegIndex misc_reg) overridegem5::CheckerThreadContext< TC >inlinevirtual
readMiscRegNoEffect(RegIndex misc_reg) const overridegem5::CheckerThreadContext< TC >inlinevirtual
readStCondFailures() const overridegem5::CheckerThreadContext< TC >inlinevirtual
readVecElem(const RegId &reg) const overridegem5::CheckerThreadContext< TC >inlinevirtual
readVecElemFlat(RegIndex idx, const ElemIndex &elem_idx) const overridegem5::CheckerThreadContext< TC >inlinevirtual
readVecPredReg(const RegId &reg) const overridegem5::CheckerThreadContext< TC >inlinevirtual
readVecPredRegFlat(RegIndex idx) const overridegem5::CheckerThreadContext< TC >inlinevirtual
readVecReg(const RegId &reg) const overridegem5::CheckerThreadContext< TC >inlinevirtual
readVecRegFlat(RegIndex idx) const overridegem5::CheckerThreadContext< TC >inlinevirtual
regStats(const std::string &name) overridegem5::CheckerThreadContext< TC >inlinevirtual
remove(PCEvent *e) overridegem5::CheckerThreadContext< TC >inlinevirtual
schedule(PCEvent *e) overridegem5::CheckerThreadContext< TC >inlinevirtual
scheduleInstCountEvent(Event *event, Tick count) overridegem5::CheckerThreadContext< TC >inlinevirtual
sendFunctional(PacketPtr pkt)gem5::ThreadContextvirtual
setCCReg(RegIndex reg_idx, RegVal val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setCCRegFlat(RegIndex idx, RegVal val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setContextId(ContextID id) overridegem5::CheckerThreadContext< TC >inlinevirtual
setFloatReg(RegIndex reg_idx, RegVal val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setFloatRegFlat(RegIndex idx, RegVal val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) overridegem5::CheckerThreadContext< TC >inlinevirtual
setIntReg(RegIndex reg_idx, RegVal val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setIntRegFlat(RegIndex idx, RegVal val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setMiscReg(RegIndex misc_reg, RegVal val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setMiscRegNoEffect(RegIndex misc_reg, RegVal val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setNPC(Addr val)gem5::CheckerThreadContext< TC >inline
setProcessPtr(Process *p) overridegem5::CheckerThreadContext< TC >inlinevirtual
setStatus(Status new_status) overridegem5::CheckerThreadContext< TC >inlinevirtual
setStCondFailures(unsigned sc_failures) overridegem5::CheckerThreadContext< TC >inlinevirtual
setThreadId(int id) overridegem5::CheckerThreadContext< TC >inlinevirtual
setUseForClone(bool new_val)gem5::ThreadContextinline
setVecElem(const RegId &reg, const TheISA::VecElem &val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setVecElemFlat(RegIndex idx, const ElemIndex &elem_idx, const TheISA::VecElem &val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setVecPredRegFlat(RegIndex idx, const TheISA::VecPredRegContainer &val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setVecReg(const RegId &reg, const TheISA::VecRegContainer &val) overridegem5::CheckerThreadContext< TC >inlinevirtual
setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer &val) overridegem5::CheckerThreadContext< TC >inlinevirtual
socketId() const overridegem5::CheckerThreadContext< TC >inlinevirtual
Status enum namegem5::ThreadContext
status() const overridegem5::CheckerThreadContext< TC >inlinevirtual
suspend() overridegem5::CheckerThreadContext< TC >inlinevirtual
Suspended enum valuegem5::ThreadContext
takeOverFrom(ThreadContext *oldContext) overridegem5::CheckerThreadContext< TC >inlinevirtual
threadId() const overridegem5::CheckerThreadContext< TC >inlinevirtual
useForClonegem5::ThreadContextprotected
~ThreadContext()gem5::ThreadContextinlinevirtual

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