gem5 Namespace Reference

Copyright (c) 2024 Arm Limited All rights reserved. More...

Namespaces
namespace	AMBA
namespace	AMDGPU
namespace	ArmISA
namespace	ArmISAInst
namespace	auxv
namespace	backdoor_manager_test
namespace	bitfield_backend
namespace	bloom_filter
namespace	branch_prediction
namespace	compression
namespace	context_switch_task_id
	Special TaskIds that are used for per-context-switch stats dumps and Cache Occupancy.
namespace	copy_engine_reg
namespace	cp
namespace	debug
namespace	decode_cache
namespace	fastmodel
namespace	free_bsd
namespace	Gem5Internal
namespace	GenericISA
namespace	guest_abi
namespace	igbreg
namespace	Iris
namespace	linux
namespace	loader
namespace	memory
namespace	minor
namespace	MipsISA
namespace	mpam
namespace	networking
namespace	NullISA
namespace	o3
namespace	partitioning_policy
namespace	PowerISA
namespace	prefetch
namespace	probing
	Name space containing shared probe point declarations.
namespace	ps2
namespace	pseudo_inst
namespace	QARMA
namespace	qemu
namespace	replacement_policy
namespace	RiscvISA
namespace	ruby
namespace	scmi
namespace	sim_clock
	These are variables that are set based on the simulator frequency.
namespace	sinic
namespace	SparcISA
namespace	statistics
namespace	stl_helpers
namespace	tlm
namespace	trace
namespace	VegaISA
	classes that represnt vector/scalar operands in VEGA ISA.
namespace	X86ISA
	This is exposed globally, independent of the ISA.
namespace	X86ISAInst

Classes
class	__SchedulingPolicy
	Intermediate class that derives from the i-face class, and implements its API. More...
struct	_amd_queue_t
struct	_hsa_agent_dispatch_packet_t
struct	_hsa_barrier_and_packet_t
struct	_hsa_barrier_or_packet_t
struct	_hsa_dispatch_packet_t
struct	_hsa_generic_vendor_pkt
struct	_hsa_queue_t
struct	_hsa_signal_t
class	A9SCU
struct	Aapcs32
struct	Aapcs32Vfp
struct	Aapcs64
class	AbstractNVM
	This is an interface between the disk interface (which will handle the disk data transactions) and the timing model. More...
class	ActivityRecorder
	ActivityRecorder helper class that informs the CPU if it can switch over to being idle or not. More...
class	AddressManager
struct	AddressMonitor
class	AddrMapper
	An address mapper changes the packet addresses in going from the response port side of the mapper to the request port side. More...
class	AddrRange
	The AddrRange class encapsulates an address range, and supports a number of tests to check if two ranges intersect, if a range contains a specific address etc. More...
class	AddrRangeMap
	The AddrRangeMap uses an STL map to implement an interval tree for address decoding. More...
class	AddrTypes
class	AmbaDevice
class	AmbaDmaDevice
class	AmbaFake
class	AmbaIntDevice
class	AmbaPioDevice
struct	amd_event_t
struct	amd_signal_s
class	AMDGPUDevice
	Device model for an AMD GPU. More...
class	AMDGPUGfx
struct	AMDGPUIHRegs
	Struct to contain all interrupt handler related registers. More...
struct	AMDGPUInterruptCookie
class	AMDGPUInterruptHandler
class	AMDGPUMemoryManager
class	AMDGPUNbio
class	AMDGPUSystemHub
	This class handles reads from the system/host memory space from the shader. More...
class	AMDGPUVM
class	AMDMMIOReader
	Helper class to read Linux kernel MMIO trace from amdgpu modprobes. More...
class	Ap2ScpDoorbell
struct	ApertureRegister
class	AQLRingBuffer
	Internal ring buffer which is used to prefetch/store copies of the in-memory HSA ring buffer. More...
class	ArchTimer
	Per-CPU architected timer. More...
class	ArchTimerKvm
class	ARMArchTLB
class	ArmFreebsd
class	ArmFreebsd32
class	ArmFreebsd64
class	ArmInterruptPin
	Generic representation of an Arm interrupt pin. More...
class	ArmInterruptPinGen
	This SimObject is instantiated in the python world and serves as an ArmInterruptPin generator. More...
class	ArmKvmCPU
	ARM implementation of a KVM-based hardware virtualized CPU. More...
class	ArmLinux
class	ArmLinux32
class	ArmLinux64
class	ArmLinuxProcess32
	A process with emulated Arm/Linux syscalls. More...
class	ArmLinuxProcess64
	A process with emulated Arm/Linux syscalls. More...
class	ArmPPI
class	ArmPPIGen
	Private Peripheral Interrupt Generator Since PPIs are banked in the GIC, this class is capable of generating more than one interrupt (one per ContextID). More...
class	ArmProcess
class	ArmProcess32
class	ArmProcess64
class	ArmRelease
class	ArmSemihosting
	Semihosting for AArch32 and AArch64. More...
class	ArmSigInterruptPin
class	ArmSigInterruptPinGen
class	ArmSPI
class	ArmSPIGen
	Shared Peripheral Interrupt Generator It is capable of generating one interrupt only: it maintains a pointer to it and returns it every time it is asked for it (via the get metod) More...
class	ArmSystem
class	ArmV8KvmCPU
	This is an implementation of a KVM-based ARMv8-compatible CPU. More...
class	AssociativeCache
class	AtagCmdline
class	AtagCore
class	AtagHeader
class	AtagMem
class	AtagNone
class	AtagRev
class	AtagSerial
class	AtomicGeneric2Op
class	AtomicGeneric3Op
class	AtomicGenericPair3Op
class	AtomicOpAdd
class	AtomicOpAnd
class	AtomicOpCAS
class	AtomicOpDec
class	AtomicOpExch
struct	AtomicOpFunctor
class	AtomicOpInc
class	AtomicOpMax
class	AtomicOpMin
class	AtomicOpOr
class	AtomicOpSub
class	AtomicOpXor
class	AtomicRequestProtocol
class	AtomicResponseProtocol
class	AtomicSimpleCPU
class	AtOp64
class	BackdoorManager
	This class manages the backdoors for RangeAddrMapper. More...
class	BadDevice
	BadDevice This device just panics when accessed. More...
class	Barrier
class	BaseArmKvmCPU
class	BaseBufferArg
	Base class for BufferArg and TypedBufferArg, Not intended to be used directly. More...
class	BaseCache
	A basic cache interface. More...
class	BaseCPU
class	BaseGdbRegCache
	Concrete subclasses of this abstract class represent how the register values are transmitted on the wire. More...
class	BaseGen
	Base class for all generators, with the shared functionality and virtual functions for entering, executing and leaving the generator. More...
class	BaseGic
class	BaseGlobalEvent
	Common base class for GlobalEvent and GlobalSyncEvent. More...
class	BaseGlobalEventTemplate
	Funky intermediate class to support CRTP so that we can have a common constructor to create the local events, even though the types of the local events are defined in the derived classes. More...
class	BaseHTMCheckpoint
	Transactional Memory checkpoint. More...
class	BaseInterrupts
class	BaseISA
class	BaseKvmCPU
	Base class for KVM based CPU models. More...
class	BaseKvmTimer
	Timer functions to interrupt VM execution after a number of simulation ticks. More...
class	BaseMemProbe
	Base class for memory system probes accepting Packet instances. More...
class	BaseMMU
class	BasePixelPump
	Timing generator for a pixel-based display. More...
class	BaseRemoteGDB
class	BaseSemihosting
	Semihosting for AArch32, AArch64, RISCV-32 and RISCV-64: https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst. More...
class	BaseSetAssoc
	A basic cache tag store. More...
class	BaseSimpleCPU
class	BaseStackTrace
class	BaseTags
	A common base class of Cache tagstore objects. More...
class	BaseTLB
class	BaseTrafficGen
	The traffic generator is a module that generates stimuli for the memory system, based on a collection of simple generator behaviours that are either probabilistic or based on traces. More...
class	BaseXBar
	The base crossbar contains the common elements of the non-coherent and coherent crossbar. More...
class	BasicPioDevice
class	BasicSignal
class	BitfieldROType
class	BitfieldType
class	BitfieldTypeImpl
class	BitfieldWOType
class	BmpWriter
class	BreakPCEvent
class	Bridge
	A bridge is used to interface two different crossbars (or in general a memory-mapped requestor and responder), with buffering for requests and responses. More...
class	BTBSetAssociative
class	BTBTagType
class	BufferArg
	BufferArg represents an untyped buffer in target user space that is passed by reference to an (emulated) system call. More...
class	Cache
	A coherent cache that can be arranged in flexible topologies. More...
struct	CacheAccessor
	Provides generic cache lookup functions. More...
class	CacheAccessProbeArg
	Information provided to probes on a cache event. More...
class	CacheBlk
	A Basic Cache block. More...
class	CacheBlkPrintWrapper
	Simple class to provide virtual print() method on cache blocks without allocating a vtable pointer for every single cache block. More...
struct	CacheDataUpdateProbeArg
	A data contents update is composed of the updated block's address, the old contents, and the new contents. More...
class	CacheEntry
	A CacheEntry is an entry containing a tag. More...
class	CallbackQueue
class	ChannelAddr
	Class holding a guest address in a contiguous channel-local address space. More...
class	ChannelAddrRange
	The ChanneelAddrRange class describes a contiguous range of addresses in a contiguous channel-local address space. More...
class	Check
class	Checker
	Templated Checker class. More...
class	CheckerCPU
	CheckerCPU class. More...
class	CheckerThreadContext
	Derived ThreadContext class for use with the Checker. More...
class	CheckpointIn
class	CheckTable
class	ChunkGenerator
	This class takes an arbitrary memory region (address/length pair) and generates a series of appropriately (e.g. More...
class	CircleBuf
	Circular buffer backed by a vector. More...
class	CircularQueue
	Circular queue. More...
class	Clint
	NOTE: This implementation of CLINT is based on the SiFive U54MC datasheet: https://sifive.cdn.prismic.io/sifive/fab000f6- 0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_ full_20G1.03.00_manual.pdf. More...
class	ClockDomain
	The ClockDomain provides clock to group of clocked objects bundled under the same clock domain. More...
class	Clocked
	Helper class for objects that need to be clocked. More...
class	ClockedObject
	The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to the cycles of the object. More...
class	ClockRateControlBwIf
struct	ClockRateControlDummyProtocolType
class	ClockRateControlFwIf
class	ClockRateControlInitiatorSocket
class	ClockRateControlSlaveBase
class	ClockRateControlTargetSocket
class	CoherentXBar
	A coherent crossbar connects a number of (potentially) snooping requestors and responders, and routes the request and response packets based on the address, and also forwards all requests to the snoopers and deals with the snoop responses. More...
struct	CommandReg_t
class	CommMonitor
	The communication monitor is a SimObject which can monitor statistics of the communication happening between two ports in the memory system. More...
class	CompressedTags
	A CompressedTags cache tag store. More...
class	CompressionBlk
	A superblock is composed of sub-blocks, and each sub-block has information regarding its superblock and a pointer to its superblock tag. More...
class	ComputeUnit
class	ConfigCache
class	ConstProxyPtr
struct	ContextDescriptor
class	CopyEngine
class	Coroutine
	This template defines a Coroutine wrapper type with a Boost-like interface. More...
class	CountedExitEvent
class	CowDiskImage
	Specialization for accessing a copy-on-write disk image layer. More...
class	CpuCluster
class	CpuLocalTimer
class	CPUProgressEvent
class	CpuThread
class	CustomNoMaliGpu
class	CxxConfigDirectoryEntry
	Config details entry for a SimObject. More...
class	CxxConfigFileBase
	Config file wrapper providing a common interface to CxxConfigManager. More...
class	CxxConfigManager
	This class allows a config file to be read into gem5 (generating the appropriate SimObjects) from C++. More...
class	CxxConfigParams
	Base for peer classes of SimObjectParams derived classes with parameter modifying member functions. More...
class	CxxIniFile
	CxxConfigManager interface for using .ini files. More...
class	Cycles
	Cycles is a wrapper class for representing cycle counts, i.e. More...
class	DataTranslation
	This class represents part of a data address translation. More...
struct	DebugBreakEvent
class	DebugStep
class	DecoderFaultInst
class	DerivedClockDomain
	The derived clock domains provides the notion of a clock domain that is connected to a parent clock domain that can either be a source clock domain or a derived clock domain. More...
struct	DescheduleDeleter
class	DeviceFDEntry
	Holds file descriptors needed to simulate devices opened with pseudo files (commonly with calls to ioctls). More...
class	DirectedGenerator
class	DiskImage
	Basic interface for accessing a disk image. More...
class	Display
struct	DisplayTimings
class	DistEtherLink
	Model for a fixed bandwidth full duplex ethernet link. More...
class	DistHeaderPkt
class	DistIface
	The interface class to talk to peer gem5 processes. More...
class	DmaCallback
	DMA callback class. More...
class	DmaDevice
class	DmaPort
class	DmaReadFifo
	Buffered DMA engine helper class. More...
class	DmaThread
class	DmaVirtDevice
class	Doorbell
	Generic doorbell interface. More...
struct	DoorbellInfo
struct	dp_regs
	Ethernet device registers. More...
struct	dp_rom
class	Drainable
	Interface for objects that might require draining before checkpointing. More...
class	DrainManager
class	DramGen
	DRAM specific generator is for issuing request with variable page hit length and bank utilization. More...
class	DRAMPower
	DRAMPower is a standalone tool which calculates the power consumed by a DRAM in the system. More...
class	DramRotGen
class	Dueler
	A dueler is an entry that may or may not be accounted for sampling. More...
class	DuelingMonitor
	Duel between two sampled options to determine which is the winner. More...
class	DumbTOD
	DumbTOD simply returns some idea of time when read. More...
class	DummyChecker
	Specific non-templated derived class used for SimObject configuration. More...
struct	DummyMatRegContainer
	Dummy type aliases and constants for architectures that do not implement matrix registers. More...
struct	DummyVecPredRegContainer
	Dummy type aliases and constants for architectures that do not implement vector predicate registers. More...
struct	DummyVecRegContainer
	Dummy type aliases and constants for architectures that do not implement vector registers. More...
class	DVFSHandler
	DVFS Handler class, maintains a list of all the domains it can handle. More...
class	DynPoolManager
class	EmbeddedPyBind
struct	EmbeddedPython
class	EmulatedDriver
	EmulatedDriver is an abstract base class for fake SE-mode device drivers. More...
class	EmulationPageTable
class	EnergyCtrl
class	Episode
class	EtherBus
class	EtherDevBase
	Dummy class to keep the Python class hierarchy in sync with the C++ object hierarchy. More...
class	EtherDevice
class	EtherDump
class	EtherInt
class	EtherLink
class	EtherSwitch
class	EtherTapBase
class	EtherTapInt
class	EtherTapStub
class	EthPacketData
class	Event
class	EventBase
	Common base class for Event and GlobalEvent, so they can share flag and priority definitions and accessor functions. More...
class	EventFunctionWrapper
class	EventManager
class	EventQueue
	Queue of events sorted in time order. More...
class	ExecContext
	The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate the state of the CPU model. More...
class	ExecStage
class	ExitGen
	The exit generator exits from the simulation once entered. More...
class	Extensible
class	Extension
	This is the extension for carrying additional information. More...
class	ExtensionBase
	This is base of every extension. More...
class	ExternalMaster
class	ExternalSlave
class	FailUnimplemented
	Static instruction class for unimplemented instructions that cause simulator termination. More...
class	FALRU
	A fully associative LRU cache. More...
class	FALRUBlk
	A fully associative cache block. More...
class	FaultBase
class	FDArray
class	FDEntry
	Holds a single file descriptor mapping and that mapping's data for processes running in syscall emulation mode. More...
class	FetchStage
class	FetchUnit
class	Fiber
	This class represents a fiber, which is a light weight sort of thread which is cooperatively scheduled and runs sequentially with other fibers, swapping in and out of a single actual thread of execution. More...
class	Fifo
	Simple FIFO implementation backed by a circular buffer. More...
class	FileFDEntry
	Holds file descriptors for host-backed files; host-backed files are files which were opened on the physical machine where the simulation is running (probably the thing on/under your desk). More...
class	FixedStreamGen
class	Flags
	Wrapper that groups a few flag bits under the same undelying container. More...
class	FlashDevice
	Flash Device model The Flash Device model is a timing model for a NAND flash device. More...
class	Float16
class	FrameBuffer
	Internal gem5 representation of a frame buffer. More...
class	FreeBSD
	This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Alpha FreeBSD syscall interface. More...
class	FUDesc
class	FunctionalRequestProtocol
class	FunctionalResponseProtocol
class	FunctionProfile
class	FuncUnit
class	FutexKey
	FutexKey class defines an unique identifier for a particular futex in the system. More...
class	FutexMap
	FutexMap class holds a map of all futexes used in the system. More...
class	FVPBasePwrCtrl
struct	FXSave
class	GarnetSyntheticTraffic
struct	GEM5_PACKED
	PM4 packets. More...
class	GenericAlignmentFault
class	GenericArmPciHost
class	GenericHtmFailureFault
class	GenericPageTableFault
class	GenericPciHost
	Configurable generic PCI host interface. More...
class	GenericRiscvPciHost
class	GenericSatCounter
	Implements an n bit saturating counter and provides methods to increment, decrement, and read it. More...
struct	GenericSyscallABI
struct	GenericSyscallABI32
struct	GenericSyscallABI64
class	GenericTimer
class	GenericTimerFrame
class	GenericTimerISA
class	GenericTimerMem
class	GenericWatchdog
class	GicV2
class	Gicv2m
class	Gicv2mFrame
	Ultimately this class should be embedded in the Gicv2m class, but this confuses Python as 'Gicv2m::Frame' gets interpreted as 'Frame' in namespace Gicv2m. More...
class	GicV2Registers
struct	GicV2Types
class	Gicv3
class	Gicv3CPUInterface
class	Gicv3Distributor
class	Gicv3Its
	GICv3 ITS module. More...
class	Gicv3Redistributor
class	Gicv3Registers
struct	GicV3Types
class	GlobalEvent
	The main global event class. More...
class	GlobalInstTracker
class	GlobalMemPipeline
class	Globals
	Container for serializing global variables (not associated with any serialized object). More...
class	GlobalSimLoopExitEvent
class	GlobalSyncEvent
	A special global event that synchronizes all threads and forces them to process asynchronously enqueued events. More...
class	GoodbyeObject
class	GPUCommandProcessor
class	GPUComputeDriver
class	GPUDispatcher
class	GPUDynInst
class	GPUExecContext
class	GPURenderDriver
class	GPUStaticInst
struct	GpuTranslationState
	GPU TranslationState: this currently is a somewhat bastardization of the usage of SenderState, whereby the receiver of a packet is not usually supposed to need to look at the contents of the senderState, you're really only supposed to look at what you pushed on, pop it off, and send it back. More...
class	GpuWavefront
struct	GTestException
class	GTestLogOutput
class	GTestTickHandler
class	GUPSGen
class	HardBreakpoint
class	HBFDEntry
	Extends the base class to include a host-backed file descriptor field that records the integer used to represent the file descriptor on the host and the file's flags. More...
class	HDLcd
class	HelloObject
class	HiFiveBase
class	HMCController
	HMC Controller, in general, is responsible for translating the host protocol (AXI for example) to serial links protocol. More...
class	HorizontalSlice
	Provides a view of a horizontal slice of either a MatStore or a Tile. More...
struct	hsa_packet_header_bitfield_t
class	HSAPacketProcessor
class	HSAQueueDescriptor
class	HSAQueueEntry
class	HWScheduler
class	HybridGen
	Hybrid NVM + DRAM specific generator is for issuing request with variable buffer hit length and bank utilization. More...
class	I2CBus
class	I2CDevice
class	IdeController
	Device model for an Intel PIIX4 IDE controller. More...
class	IdeDisk
	IDE Disk device model. More...
class	IdleGen
	The idle generator does nothing. More...
class	IdleStartEvent
class	IGbE
class	IGbEInt
class	IllegalExecInst
	This class is modelling instructions which are not going to be executed since they are flagged as Illegal Execution Instructions (PSTATE.IL = 1 or CPSR.IL = 1). More...
class	ImgWriter
class	ImmOp
class	ImmOp64
class	IndexingPolicyTemplate
	A common base class for indexing table locations. More...
class	IniFile
	This class represents the contents of a ".ini" file. More...
class	InstDecoder
class	InstResult
class	Intel8254Timer
	Programmable Interval Timer (Intel 8254) More...
class	IntSinkPinBase
class	IntSourcePinBase
class	InvalidateGenerator
class	Iob
class	IPACache
struct	is_iterable
struct	is_iterable< T, std::void_t< decltype(begin(std::declval< T >())), decltype(end(std::declval< T >()))> >
struct	is_std_hash_enabled
struct	is_std_hash_enabled< T, std::void_t< decltype(std::hash< T >())> >
struct	is_vec_reg_container
struct	is_vec_reg_container< gem5::VecRegContainer< SIZE > >
class	IsaFake
	IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and rites. More...
struct	ItsAction
class	ItsCommand
	An ItsCommand is created whenever there is a new command in the command queue. More...
class	ItsProcess
	ItsProcess is a base coroutine wrapper which is spawned by the Gicv3Its module when the latter needs to perform different actions, like translating a peripheral's MSI into an LPI (See derived ItsTranslation) or processing a Command from the ITS queue (ItsCommand). More...
class	ItsTranslation
	An ItsTranslation is created whenever a peripheral writes a message in GITS_TRANSLATER (MSI). More...
class	KernelLaunchStaticInst
class	KernelWorkload
struct	kfd_event_data
struct	kfd_hsa_hw_exception_data
struct	kfd_hsa_memory_exception_data
struct	kfd_ioctl_acquire_vm_args
struct	kfd_ioctl_alloc_memory_of_gpu_args
struct	kfd_ioctl_alloc_queue_gws_args
struct	kfd_ioctl_create_event_args
struct	kfd_ioctl_create_queue_args
struct	kfd_ioctl_dbg_address_watch_args
struct	kfd_ioctl_dbg_register_args
struct	kfd_ioctl_dbg_unregister_args
struct	kfd_ioctl_dbg_wave_control_args
struct	kfd_ioctl_destroy_event_args
struct	kfd_ioctl_destroy_queue_args
struct	kfd_ioctl_free_memory_of_gpu_args
struct	kfd_ioctl_get_clock_counters_args
struct	kfd_ioctl_get_dmabuf_info_args
struct	kfd_ioctl_get_process_apertures_args
struct	kfd_ioctl_get_process_apertures_new_args
struct	kfd_ioctl_get_queue_wave_state_args
struct	kfd_ioctl_get_tile_config_args
struct	kfd_ioctl_get_version_args
struct	kfd_ioctl_import_dmabuf_args
struct	kfd_ioctl_map_memory_to_gpu_args
struct	kfd_ioctl_reset_event_args
struct	kfd_ioctl_set_cu_mask_args
struct	kfd_ioctl_set_event_args
struct	kfd_ioctl_set_memory_policy_args
struct	kfd_ioctl_set_scratch_backing_va_args
struct	kfd_ioctl_set_trap_handler_args
struct	kfd_ioctl_smi_events_args
struct	kfd_ioctl_unmap_memory_from_gpu_args
struct	kfd_ioctl_update_queue_args
struct	kfd_ioctl_wait_events_args
struct	kfd_memory_exception_failure
struct	kfd_process_device_apertures
class	Kvm
	KVM parent interface. More...
class	KvmDevice
	KVM device wrapper. More...
union	KvmFPReg
class	KvmKernelGic
	KVM in-kernel GIC abstraction. More...
class	KvmKernelGicV2
class	KvmKernelGicV3
class	KvmVM
	KVM VM container. More...
class	LdsChunk
	this represents a slice of the overall LDS, intended to be associated with an individual workgroup More...
class	LdsState
class	LinearEquation
	This class describes a linear equation with constant coefficients. More...
class	LinearGen
	The linear generator generates sequential requests from a start to an end address, with a fixed block size. More...
class	LinearSystem
class	Linux
	This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Alpha Linux syscall interface. More...
class	ListenSocket
class	ListenSocketConfig
class	ListenSocketInet
class	ListenSocketUnix
class	ListenSocketUnixAbstract
class	ListenSocketUnixFile
class	LocalInstTracker
class	LocalMemPipeline
class	LocalSimLoopExitEvent
class	Logger
class	LooppointAnalysis
class	LooppointAnalysisManager
class	LupioBLK
	LupioBLK: A virtual block device which aims to provide a disk-like interface for second-level storage. More...
class	LupioIPI
	LupioIPI: An inter-processor interrupt virtual device. More...
class	LupioPIC
	LupioPIC: A programmable interrupt controller virtual device that can manage input IRQs coming from up to 32 sources. More...
class	LupioRNG
	LupioRNG: A Random Number Generator virtual device that returns either a random value, or a seed that can be configured by the user. More...
class	LupioRTC
	LupioRTC: A Real-Time Clock Virtual Device that returns the current date and time in ISO 8601 format. More...
class	LupioSYS
	LupioSYS: A Real-Time System Controller virtual device which provides a way for the software to halt or reboot the computer system. More...
class	LupioTMR
	LupioTMR: A virtual timer device which provides a real time counter, as well as a configurable timer offering periodic and one shot modes. More...
class	LupioTTY
	LupioTTY: The LupioTTY is a virtual terminal device that can both transmit characters to a screen, as well as receive characters input from a keyboard. More...
class	LupV
	The LupV collection consists of a RISC-V processor, as well as the set of LupiIO devices. More...
class	Malta
	Top level class for Malta Chipset emulation. More...
class	MaltaCChip
	Malta CChip CSR Emulation. More...
class	MaltaIO
	Malta I/O device is a catch all for all the south bridge stuff we care to implement. More...
class	MasterPort
class	MathExpr
class	MathExprPowerModel
	A Equation power model. More...
class	MatStore
	Backing store for matrices. More...
class	MC146818
	Real-Time Clock (MC146818) More...
class	McrMrcImplDefined
	This class is also used for IMPLEMENTATION DEFINED registers, whose mcr/mrc behaviour is trappable even for unimplemented registers. More...
class	McrMrcMiscInst
	Certain mrc/mcr instructions act as nops or flush the pipe based on what register the instruction is trying to access. More...
class	McrrOp
class	MemBackdoor
class	MemBackdoorReq
class	MemberEventWrapper
	Wrap a member function inside MemberEventWrapper to use it as an event callback. More...
struct	MemberFunctionSignature
struct	MemberFunctionSignature< R(C::*)(A...) const >
struct	MemberFunctionSignature< R(C::*)(A...) const volatile >
struct	MemberFunctionSignature< R(C::*)(A...) volatile >
struct	MemberFunctionSignature< R(C::*)(A...)>
class	MemChecker
	MemChecker. More...
class	MemCheckerMonitor
	Implements a MemChecker monitor, to be inserted between two ports. More...
class	MemCmd
class	MemDelay
	This abstract component provides a mechanism to delay packets. More...
class	MemFootprintProbe
	Probe to track footprint of accessed memory Two granularity of footprint measurement i.e. More...
class	Memoizer
	This class takes a function as a constructor argument and memoizes it: every time the function gets invoked through the Memoizer object (see operator()), the result gets saved in the internal cache, ready to be retrieved next time an invokation is made with the same arguments. More...
class	MemPool
	Class for handling allocation of physical pages in SE mode. More...
class	MemPools
class	MemState
	This class holds the memory state for the Process class and all of its derived, architecture-specific children. More...
class	MemTest
	The MemTest class tests a cache coherent memory system by generating false sharing and verifying the read data against a reference updated on the completion of writes. More...
class	MemTraceProbe
class	MHU
	Message Handling Unit. More...
class	MhuDoorbell
class	MinorCPU
	MinorCPU is an in-order CPU model with four fixed pipeline stages: More...
class	MinorFU
	A functional unit that can execute any of opClasses operations with a single op(eration)Lat(ency) and issueLat(ency) associated with the unit rather than each operation (as in src/FuncUnit). More...
class	MinorFUPool
	A collection of MinorFUs. More...
class	MinorFUTiming
	Extra timing capability to allow individual ops to have their source register dependency latencies tweaked based on the ExtMachInst of the source instruction. More...
class	MinorOpClass
	Boxing for MinorOpClass to get around a build problem with C++11 but also allow for future additions to op class checking. More...
class	MinorOpClassSet
	Wrapper for a matchable set of op classes. More...
class	MipsLinux
class	MipsProcess
class	MiscRegImmOp64
class	MiscRegImplDefined64
class	MiscRegOp64
	This class is implementing the Base class for a generic AArch64 instruction which is making use of system registers (MiscReg), like MSR,MRS,SYS. More...
class	MiscRegRegImmOp
class	MiscRegRegImmOp64
class	MmDisk
class	MmioVirtIO
class	MonitorCallEvent
class	MrrcOp
class	MrsOp
class	MSHR
	Miss Status and handling Register. More...
class	MSHRQueue
	A Class for maintaining a list of pending and allocated memory requests. More...
class	MsrBase
class	MsrImmOp
class	MsrRegOp
class	MultiLevelPageTable
class	MuxingKvmGic
class	Named
	Interface for things with names. More...
class	NoMaliGpu
class	NonCachingSimpleCPU
	The NonCachingSimpleCPU is an AtomicSimpleCPU using the 'atomic_noncaching' memory mode instead of just 'atomic'. More...
class	NoncoherentCache
	A non-coherent cache. More...
class	NoncoherentXBar
	A non-coherent crossbar connects a number of non-snooping memory-side ports and cpu_sides, and routes the request and response packets based on the address. More...
struct	ns_desc32
struct	ns_desc64
class	NSGigE
	NS DP83820 Ethernet device model. More...
class	NSGigEInt
class	NvmGen
	NVM specific generator is for issuing request with variable buffer hit length and bank utilization. More...
class	ObjectMatch
	ObjectMatch contains a vector of expressions. More...
class	OFSchedulingPolicy
class	OpDesc
class	OpenFlagTable
class	OperandInfo
class	OperatingSystem
	This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to an operating system syscall interface. More...
class	OutgoingRequestBridge
class	OutputDirectory
	Interface for creating files in a gem5 output directory. More...
class	OutputFile
class	OutputStream
struct	P9MsgHeader
struct	P9MsgInfo
class	Packet
	A Packet is used to encapsulate a transfer between two objects in the memory system (e.g., the L1 and L2 cache). More...
class	PacketFifo
struct	PacketFifoEntry
class	PacketQueue
	A packet queue is a class that holds deferred packets and later sends them using the associated CPU-side port or memory-side port. More...
class	PanicPCEvent
struct	ParseParam
struct	ParseParam< BitUnionType< T > >
struct	ParseParam< bool >
struct	ParseParam< DummyMatRegContainer >
struct	ParseParam< DummyVecPredRegContainer >
struct	ParseParam< DummyVecRegContainer >
struct	ParseParam< MatStore< X, Y > >
	Calls required for serialization/deserialization. More...
struct	ParseParam< std::string >
struct	ParseParam< T, decltype(to_number("", std::declval< T & >()), void())>
struct	ParseParam< T, std::enable_if_t< std::is_base_of_v< typename RegisterBankBase::RegisterBaseBase, T > > >
struct	ParseParam< VecPredRegContainer< NumBits, Packed > >
struct	ParseParam< VecRegContainer< Sz > >
	Calls required for serialization/deserialization. More...
class	Pc
struct	pcap_file_header
struct	pcap_pkthdr
class	PcCountPair
class	PcCountTracker
class	PcCountTrackerManager
class	PCEvent
class	PCEventQueue
class	PCEventScope
class	PciBar
class	PciBarNone
struct	PciBusAddr
class	PciDevice
	PCI device, base implementation is only config space. More...
class	PciHost
	The PCI host describes the interface between PCI devices and a simulated system. More...
class	PciIoBar
class	PciLegacyIoBar
class	PciMemBar
class	PciMemUpperBar
class	PciVirtIO
class	PCStateBase
class	PerfKvmCounter
	An instance of a performance counter. More...
class	PerfKvmCounterConfig
	PerfEvent counter configuration. More...
class	PerfKvmTimer
	PerfEvent based timer using the host's CPU cycle counter. More...
class	PhysRegId
	Physical register ID. More...
class	PioDevice
	This device is the base class which all devices senstive to an address range inherit from. More...
class	PioPort
	The PioPort class is a programmed i/o port that all devices that are sensitive to an address range use. More...
class	PipeFDEntry
	Holds the metadata needed to maintain the mappings for file descriptors allocated with the pipe() system calls and its variants. More...
class	PipeStageIFace
struct	Pixel
	Internal gem5 representation of a Pixel. More...
class	PixelConverter
	Configurable RGB pixel converter. More...
class	Pl011
class	PL031
class	Pl050
class	Pl111
class	Platform
class	Plic
class	PlicBase
class	PlicIntDevice
struct	PlicOutput
	NOTE: This implementation of PLIC is based on he riscv-plic-spec repository: https://github.com/riscv/riscv-plic-spec/releases/tag/1.0.0. More...
class	PM4PacketProcessor
class	PM4Queue
	Class defining a PM4 queue. More...
class	PngWriter
	Image writer implementing support for PNG. More...
class	PollEvent
class	PollQueue
class	PoolManager
class	Port
	Ports are used to interface objects to each other. More...
class	PortProxy
	This object is a proxy for a port or other object which implements the functional response protocol, to be used for debug accesses. More...
class	PortTerminator
class	PosixKvmTimer
	Timer based on standard POSIX timers. More...
class	PowerDomain
	The PowerDomain groups PowerState objects together to regulate their power states. More...
class	PowerLinux
class	PowerModel
class	PowerModelState
	A PowerModelState is an abstract class used as interface to get power figures out of SimObjects. More...
class	PowerProcess
class	PowerState
	Helper class for objects that have power states. More...
struct	PrdEntry_t
class	PrdTableEntry
struct	PrimaryQueue
class	Printable
	Abstract base class for objects which support being printed to a stream for debugging. More...
class	ProbeListener
	ProbeListener base class; here to simplify things like containers containing multiple types of ProbeListener. More...
class	ProbeListenerArg
	ProbeListenerArg generates a listener for the class of Arg and the class type T which is the class containing the function that notify will call. More...
class	ProbeListenerArgBase
	ProbeListenerArgBase is used to define the base interface to a ProbeListenerArg (i.e the notify method on specific type). More...
class	ProbeListenerArgFunc
	ProbeListenerArgFunc generates a listener for the class of Arg and a lambda callback function that is called by the notify. More...
class	ProbeListenerObject
	This class is a minimal wrapper around SimObject. More...
class	ProbeManager
	ProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners with probe points. More...
class	ProbePoint
	ProbeListener base class; again used to simplify use of ProbePoints in containers and used as to define interface for adding removing listeners to the ProbePoint. More...
class	ProbePointArg
	ProbePointArg generates a point for the class of Arg. More...
class	Process
class	ProfileNode
class	ProtocolTester
class	ProxyPtr
class	ProxyPtr< void, Proxy >
class	ProxyPtrBuffer
struct	PybindModuleInit
class	PybindSimObjectResolver
	Resolve a SimObject name using the Pybind configuration. More...
class	PyEvent
	PyBind wrapper for Events. More...
class	PyTrafficGen
struct	QCntxt
class	Queue
	A high-level queue interface, to be used by both the MSHR queue and the write buffer. More...
class	QueuedRequestPort
	The QueuedRequestPort combines two queues, a request queue and a snoop response queue, that both share the same port. More...
class	QueuedResponsePort
	A queued port is a port that has an infinite queue for outgoing packets and thus decouples the module that wants to send request/responses from the flow control (retry mechanism) of the port. More...
class	QueueEntry
	A queue entry base class, to be used by both the MSHRs and write-queue entries. More...
class	Random
class	RandomGen
	The random generator is similar to the linear one, but does not generate sequential addresses. More...
class	RandomStreamGen
class	RandomTest
	Helper class to access private members of Random. More...
class	RangeAddrMapper
	Range address mapper that maps a set of original ranges to a set of remapped ranges, where a specific range is of the same size (original and remapped), only with an offset. More...
class	RawDiskImage
	Specialization for accessing a raw disk image. More...
class	RealView
class	RealViewCtrl
class	RealViewOsc
	This is an implementation of a programmable oscillator on the that can be configured through the RealView/Versatile Express configuration interface. More...
class	RealViewTemperatureSensor
	This device implements the temperature sensor used in the RealView/Versatile Express platform. More...
class	RedirectPath
	RedirectPath stores a mapping from one 'appPath' to a vector of 'hostPath'. More...
class	ReExec
class	RefCounted
	Derive from RefCounted if you want to enable reference counting of this class. More...
class	RefCountingPtr
	If you want a reference counting pointer to a mutable object, create it like this: More...
class	RegClass
class	RegClassIterator
class	RegClassOps
class	RegFile
class	RegId
	Register ID: describe an architectural register with its class and index. More...
class	RegImmImmOp
class	RegImmImmOp64
class	RegImmOp
class	RegImmRegOp
class	RegImmRegShiftOp
class	RegisterBank
class	RegisterBankBase
class	RegisterFile
class	RegisterFileCache
class	RegisterManager
class	RegisterManagerPolicy
	Register Manager Policy abstract class. More...
class	RegisterOperandInfo
class	RegMiscRegImmOp
class	RegMiscRegImmOp64
class	RegNone
class	RegOp
class	RegOp64
class	RegRegImmImmOp
class	RegRegImmImmOp64
class	RegRegImmOp
class	RegRegOp
class	RegRegRegImmOp
class	RegRegRegImmOp64
class	RegRegRegOp
class	RegRegRegRegOp
class	ReplaceableEntry
	A replaceable entry is a basic entry in a 2d table-like structure that needs to have replacement functionality. More...
class	ReqPacketQueue
class	Request
struct	RequestorInfo
	The RequestorInfo class contains data about a specific requestor. More...
class	RequestPort
	A RequestPort is a specialisation of a Port, which implements the default protocol for the three different level of transport functions. More...
class	RequestPortWrapper
	The RequestPortWrapper converts inherit-based RequestPort into callback-based. More...
class	ResponsePort
	A ResponsePort is a specialization of a port. More...
class	ResponsePortWrapper
	The ResponsePortWrapper converts inherit-based ResponsePort into callback-based. More...
class	RespPacketQueue
class	RiscvLinux
class	RiscvLinux32
class	RiscvLinux64
class	RiscvProcess
class	RiscvProcess32
class	RiscvProcess64
class	RiscvRTC
	NOTE: This is a generic wrapper around the MC146818 RTC. More...
class	RiscvSemihosting
	Semihosting for RV32 and RV64. More...
class	Root
class	RRSchedulingPolicy
class	RubyDirectedTester
class	RubyTester
class	ScalarMemPipeline
class	ScalarRegisterFile
class	ScalarStatTester
class	Scheduler
class	ScheduleStage
class	ScheduleToExecute
	Communication interface between Schedule and Execute stages. More...
class	SchedulingPolicy
	Interface class for the wave scheduling policy. More...
class	ScoreboardCheckStage
class	ScoreboardCheckToSchedule
	Communication interface between ScoreboardCheck and Schedule stages. More...
class	Scp
class	Scp2ApDoorbell
class	SDMAEngine
	System DMA Engine class for AMD dGPU. More...
class	SectorBlk
	A Basic Sector block. More...
class	SectorSubBlk
	A sector is composed of sub-blocks, and each sub-block has information regarding its sector and a pointer to its sector tag. More...
class	SectorTags
	A SectorTags cache tag store. More...
struct	SemiPseudoAbi32
struct	SemiPseudoAbi64
class	SerialDevice
	Base class for serial devices such as terminals. More...
class	Serializable
	Basic support for object serialization. More...
class	SerializationFixture
	Fixture class that handles temporary directory creation. More...
class	SerialLink
	SerialLink is a simple variation of the Bridge class, with the ability to account for the latency of packet serialization. More...
class	SerialNullDevice
	Dummy serial device that discards all data sent to it. More...
class	SeriesRequestGenerator
class	SESyscallFault
class	SetAssociative
	A set associative indexing policy. More...
class	SETranslatingPortProxy
class	SEWorkload
class	Shader
struct	ShowParam
struct	ShowParam< BitUnionType< T > >
struct	ShowParam< bool >
struct	ShowParam< MatStore< X, Y > >
struct	ShowParam< T, std::enable_if_t< std::is_base_of_v< typename RegisterBankBase::RegisterBaseBase, T > > >
struct	ShowParam< T, std::enable_if_t< std::is_same_v< char, T >||std::is_same_v< unsigned char, T >||std::is_same_v< signed char, T > > >
struct	ShowParam< VecPredRegContainer< NumBits, Packed > >
struct	ShowParam< VecRegContainer< Sz > >
class	SignalInterruptBwIf
struct	SignalInterruptDummyProtocolType
class	SignalInterruptFwIf
class	SignalInterruptInitiatorSocket
class	SignalInterruptSlaveBase
class	SignalInterruptTargetSocket
class	SignalSinkPort
class	SignalSourcePort
class	SimObject
	Abstract superclass for simulation objects. More...
class	SimObjectResolver
	Base class to wrap object resolving functionality. More...
class	SimpleCache
	A very simple cache object. More...
class	SimpleDisk
class	SimpleExecContext
class	SimpleMemDelay
	Delay packets by a constant time. More...
class	SimpleMemobj
	A very simple memory object. More...
class	SimpleObject
class	SimplePoolManager
class	SimpleThread
	The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interface. More...
class	SimpleTimingPort
	The simple timing port uses a queued port to implement recvFunctional and recvTimingReq through recvAtomic. More...
class	SimpleUart
class	SimPoint
class	SimulatorThreads
class	SkewedAssociative
	A skewed associative indexing policy. More...
class	SkipFuncBase
class	SlavePort
struct	SMMUAction
class	SMMUATSDevicePort
class	SMMUATSMemoryPort
struct	SMMUCommand
class	SMMUCommandExecProcess
class	SMMUControlPort
class	SMMUDevicePort
class	SMMUDeviceRetryEvent
struct	SMMUEvent
class	SMMUProcess
class	SMMURequestPort
struct	SMMUSemaphore
struct	SMMUSignal
class	SMMUTableWalkPort
class	SMMUTLB
class	SMMUTranslationProcess
struct	SMMUTranslRequest
class	SMMUv3
class	SMMUv3BaseCache
class	SMMUv3DeviceInterface
struct	SNHash
class	SnoopFilter
	This snoop filter keeps track of which connected port has a particular line of data. More...
class	SnoopRespPacketQueue
class	SocketFDEntry
class	Solaris
	This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Solaris syscall interface. More...
class	SouthBridge
class	Sp804
class	Sp805
class	Sparc32Linux
class	Sparc32Process
class	Sparc64Process
class	SparcLinux
class	SparcProcess
struct	SparcPseudoInstABI
class	SparcSolaris
class	SparseHistStatTester
struct	SpatterAccess
class	SpatterGen
	Spatter Kernel Player. More...
class	SpatterKernel
class	SrcClockDomain
	The source clock domains provides the notion of a clock domain that is connected to a tunable clock source. More...
class	SSTResponderInterface
class	StackDistCalc
	The stack distance calculator is a passive object that merely observes the addresses pass to it. More...
class	StackDistProbe
class	StaticInst
	Base, ISA-independent static instruction class. More...
class	StaticRegisterManagerPolicy
class	StatTester
	This classes are used to test the stats system from setting through to output. More...
class	StochasticGen
class	StreamGen
struct	StreamTableEntry
class	StridedGen
	The strided generator generates sequential requests from a start to an end address, with a fixed block size. More...
struct	StringWrap
class	StubSlavePort
	Implement a ‘stub’ port which just responds to requests by printing a message. More...
class	StubSlavePortHandler
class	StubWorkload
class	SubSystem
	The SubSystem simobject does nothing, it is just a container for other simobjects used by the configuration system. More...
class	SuperBlk
	A basic compression superblock. More...
class	SysBridge
	Each System object in gem5 is responsible for a set of RequestorIDs which identify different sources for memory requests within that System. More...
class	SyscallDesc
	This class provides the wrapper interface for the system call implementations which are defined in the sim/syscall_emul files and bound to the ISAs in the architecture specific code (i.e. More...
class	SyscallDescABI
class	SyscallDescTable
class	SyscallRetryFault
class	SyscallReturn
	This class represents the return value from an emulated system call, including any errno setting. More...
class	SysSecCtrl
	System Security Control registers. More...
class	System
class	SystemCounter
	Global system counter. More...
class	SystemCounterListener
	Abstract class for elements whose events depend on the counting speed of the System Counter. More...
class	T1000
class	TaggedEntry
	A tagged entry is an entry containing a tag. More...
class	TaggedSetAssociative
	This version of set associative indexing deals with a Lookup structure made of address and secure bit. More...
class	TaggedTypes
class	TapEvent
class	TapListener
class	TCPIface
class	TempCacheBlk
	Special instance of CacheBlk for use with tempBlk that deals with its block address regeneration. More...
class	Temperature
	The class stores temperatures in Kelvin and provides helper methods to convert to/from Celsius. More...
class	Terminal
class	TesterDma
class	TesterThread
class	ThermalCapacitor
	A ThermalCapacitor is used to model a thermal capacitance between two thermal domains. More...
class	ThermalDomain
	A ThermalDomain is used to group objects under that operate under the same temperature. More...
class	ThermalEntity
	An abstract class that represents any thermal entity which is used in the circuital thermal equivalent model. More...
class	ThermalModel
class	ThermalNode
	A ThermalNode is used to connect thermal entities, such as resistors, capacitors, references and domains. More...
class	ThermalReference
	A ThermalReference is a thermal domain with fixed temperature. More...
class	ThermalResistor
	A ThermalResistor is used to model a thermal resistance between two thermal domains. More...
class	ThreadBridge
class	ThreadContext
	ThreadContext is the external interface to all thread state for anything outside of the CPU. More...
struct	ThreadState
	Struct for holding general thread state that is needed across CPU models. More...
class	Ticked
	Ticked attaches gem5's event queue/scheduler to evaluate calls and provides a start/stop interface to ticking. More...
class	TickedObject
	TickedObject attaches Ticked to ClockedObject and can be used as a base class where ticked operation. More...
class	Tile
	Provides a view of a matrix that is row-interleaved onto a MatStore. More...
class	Time
class	TimeBuffer
class	TimedQueue
class	TimingExpr
class	TimingExprBin
class	TimingExprEvalContext
	Object to gather the visible context for evaluation. More...
class	TimingExprIf
class	TimingExprLet
class	TimingExprLiteral
class	TimingExprRef
class	TimingExprSrcReg
class	TimingExprUn
class	TimingRequestProtocol
class	TimingResponseProtocol
class	TimingSimpleCPU
class	TLBCoalescer
	The TLBCoalescer is a ClockedObject sitting on the front side (CPUSide) of each TLB. More...
class	TlbiOp
class	TlbiOp64
class	TokenManager
class	TokenRequestPort
class	TokenResponsePort
class	TraceCPU
	The trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model. More...
class	TraceGen
	The trace replay generator reads a trace file and plays back the transactions. More...
class	TracingExtension
	TracingExtension is an Extension of the Packet for recording the trace of the Packet. More...
class	TrafficGen
	The traffic generator is a module that generates stimuli for the memory system, based on a collection of simple behaviours that are either probabilistic or based on traces. More...
class	TranslatingPortProxy
	This proxy attempts to translate virtual addresses using the TLBs. More...
class	TranslationGen
	TranslationGen is a base class for a generator object which returns information about address translations over a range of virtual addresses. More...
class	TranslationGenConstIterator
	An iterator for pulling "Range" instances out of a TranslationGen. More...
class	Trie
	A trie is a tree-based data structure used for data retrieval. More...
struct	TypedAtomicOpFunctor
class	TypedBufferArg
	TypedBufferArg is a class template; instances of this template represent typed buffers in target user space that are passed by reference to an (emulated) system call. More...
class	TypedRegClassOps
class	Uart
class	Uart8250
class	UFSHostDevice
	Host controller layer: This is your Host controller This layer handles the UFS functionality. More...
class	UncontendedMutex
class	UnimpFault
class	UnknownOp
class	UnknownOp64
class	VecElemRegClassOps
class	VecPredRegContainer
	Generic predicate register container. More...
class	VecPredRegT
	Predicate register view. More...
class	VecRegContainer
	Vector Register Abstraction This generic class is the model in a particularization of MVC, to vector registers. More...
class	Vector2dStatTester
class	VectorRegisterFile
class	VectorStatTester
class	VegaTLBCoalescer
	The VegaTLBCoalescer is a ClockedObject sitting on the front side (CPUSide) of each TLB. More...
class	VerticalSlice
	Provides a view of a vertical slice of either a MatStore or a Tile. More...
class	VGic
class	VirtDescriptor
	VirtIO descriptor (chain) wrapper. More...
class	VirtIO9PBase
	This class implements a VirtIO transport layer for the 9p network file system. More...
class	VirtIO9PDiod
	VirtIO 9p proxy that communicates with the diod 9p server using pipes. More...
class	VirtIO9PProxy
	VirtIO 9p proxy base class. More...
class	VirtIO9PSocket
	VirtIO 9p proxy that communicates with a 9p server over tcp sockets. More...
class	VirtIOBlock
	VirtIO block device. More...
class	VirtIOConsole
	VirtIO console. More...
class	VirtIODeviceBase
	Base class for all VirtIO-based devices. More...
class	VirtIODummyDevice
class	VirtIORng
	VirtIO Rng. More...
class	VirtQueue
	Base wrapper around a virtqueue. More...
class	VMA
class	VncInput
class	VncKeyboard
	A device that expects to receive input from the vnc server should derrive (through mulitple inheritence if necessary from VncKeyboard or VncMouse and call setKeyboard() or setMouse() respectively on the vnc server. More...
class	VncMouse
class	VncServer
class	VoltageDomain
	A VoltageDomain is used to group clock domains that operate under the same voltage. More...
class	WaitClass
class	WaiterState
	WaiterState defines internal state of a waiter thread. More...
class	WalkCache
class	WarnUnimplemented
	Base class for unimplemented instructions that cause a warning to be printed (but do not terminate simulation). More...
class	Wavefront
class	WFBarrier
	WF barrier slots. More...
class	WholeTranslationState
	This class captures the state of an address translation. More...
class	Workload
class	WriteAllocator
	The write allocator inspects write packets and detects streaming patterns. More...
class	WriteQueue
	A write queue for all eviction packets, i.e. More...
class	WriteQueueEntry
	Write queue entry. More...
class	X86IdeController
class	X86KvmCPU
	x86 implementation of a KVM-based hardware virtualized CPU. More...
class	X86Linux
class	X86Linux32
class	X86Linux64
struct	X86PseudoInstABI

Typedefs
typedef std::unique_ptr< BaseHTMCheckpoint >	BaseHTMCheckpointPtr
typedef Trie< Addr, X86ISA::TlbEntry >	TlbEntryTrie
typedef MultiLevelPageTable< LongModePTE< 47, 39 >, LongModePTE< 38, 30 >, LongModePTE< 29, 21 >, LongModePTE< 20, 12 > >	ArchPageTable
typedef std::list< AddrRange >	AddrRangeList
	Convenience typedef for a collection of address ranges.
typedef std::unique_ptr< AtomicOpFunctor >	AtomicOpFunctorPtr
template<typename T >
using	BitUnionType = bitfield_backend::BitUnionOperators< T >
template<typename T >
using	BitUnionBaseType = typename bitfield_backend::BitUnionBaseType< T >::Type
using	ListenSocketPtr = std::unique_ptr< ListenSocket >
template<auto F>
using	MemberFunctionClass_t = typename MemberFunctionSignature< decltype(F)>::class_t
template<auto F>
using	MemberFunctionReturn_t = typename MemberFunctionSignature< decltype(F)>::return_t
template<auto F>
using	MemberFunctionArgsTuple_t = typename MemberFunctionSignature< decltype(F)>::argsTuple_t
typedef int64_t	Counter
	Statistics counter type.
typedef uint64_t	Tick
	Tick count type.
typedef uint64_t	Addr
	Address type This will probably be moved somewhere else in the near future.
typedef uint16_t	MicroPC
using	RegVal = uint64_t
using	RegIndex = uint16_t
typedef int16_t	ThreadID
	Thread index/ID type.
typedef int	ContextID
	Globally unique thread context ID.
typedef int16_t	PortID
	Port index/ID type, and a symbolic name for an invalid port id.
typedef std::shared_ptr< FaultBase >	Fault
typedef std::vector< OpDesc * >::const_iterator	OPDDiterator
typedef std::vector< FUDesc * >::const_iterator	FUDDiterator
typedef uint64_t	InstSeqNum
typedef unsigned int	InstTag
using	BTBIndexingPolicy = IndexingPolicyTemplate< BTBTagType >
using	PhysRegIdPtr = PhysRegId *
typedef std::pair< Addr, Addr >	BasicBlockRange
	Probe for SimPoints BBV generation.
typedef RefCountingPtr< StaticInst >	StaticInstPtr
typedef RubyTester::SenderState	SenderState
using	PacketPtr = Packet *
typedef struct gem5::GEM5_PACKED	PM4Header
	PM4 packets.
typedef struct gem5::GEM5_PACKED	PM4WriteData
typedef struct gem5::GEM5_PACKED	PM4MapQueues
typedef struct gem5::GEM5_PACKED	PM4UnmapQueues
typedef struct gem5::GEM5_PACKED	PM4SetResources
typedef struct gem5::GEM5_PACKED	PM4MapProcess
typedef struct gem5::GEM5_PACKED	PM4MapProcessV2
typedef struct gem5::GEM5_PACKED	PM4WaitRegMem
typedef struct gem5::GEM5_PACKED	PM4SetUConfig
typedef struct gem5::GEM5_PACKED	PM4IndirectBuf
typedef struct gem5::GEM5_PACKED	PM4SwitchBuf
typedef struct gem5::GEM5_PACKED	PM4IndirectBufConst
typedef struct gem5::GEM5_PACKED	PM4FrameCtrl
typedef struct gem5::GEM5_PACKED	PM4ReleaseMem
typedef struct gem5::GEM5_PACKED	PM4SetUconfigReg
typedef struct gem5::GEM5_PACKED	PM4RunList
typedef struct gem5::GEM5_PACKED	PM4QueryStatus
typedef struct gem5::GEM5_PACKED	QueueDesc
	Queue descriptor with relevant MQD attributes.
typedef struct gem5::GEM5_PACKED	SDMAQueueDesc
	Queue descriptor for SDMA-based user queues (RLC queues).
typedef gem5::PrimaryQueue	PrimaryQueue
typedef struct gem5::GEM5_PACKED	sdmaCopy
	SDMA packets - see src/core/inc/sdma_registers.h in ROCR-Runtime.
typedef struct gem5::GEM5_PACKED	sdmaWrite
typedef struct gem5::GEM5_PACKED	sdmaConstFill
typedef struct gem5::GEM5_PACKED	sdmaConstFillHeader
typedef struct gem5::GEM5_PACKED	sdmaAESKey
typedef struct gem5::GEM5_PACKED	sdmaAESCounter
typedef struct gem5::GEM5_PACKED	sdmaAESLoad
typedef struct gem5::GEM5_PACKED	sdmaAESOffset
typedef struct gem5::GEM5_PACKED	sdmaIndirectBuffer
typedef struct gem5::GEM5_PACKED	sdmaIndirectBufferHeader
typedef struct gem5::GEM5_PACKED	sdmaFence
typedef struct gem5::GEM5_PACKED	sdmaTrap
typedef struct gem5::GEM5_PACKED	sdmaSemaphore
typedef struct gem5::GEM5_PACKED	sdmaMemInc
typedef struct gem5::GEM5_PACKED	sdmaSRBMWrite
typedef struct gem5::GEM5_PACKED	sdmaSRBMWriteHeader
typedef struct gem5::GEM5_PACKED	sdmaPollRegMem
typedef struct gem5::GEM5_PACKED	sdmaPollRegMemHeader
typedef struct gem5::GEM5_PACKED	sdmaCondExec
typedef struct gem5::GEM5_PACKED	sdmaAtomic
typedef struct gem5::GEM5_PACKED	sdmaAtomicHeader
typedef struct gem5::GEM5_PACKED	sdmaPtePde
typedef struct gem5::GEM5_PACKED	sdmaTimestamp
typedef struct gem5::GEM5_PACKED	sdmaPredExec
typedef struct gem5::GEM5_PACKED	sdmaPredExecHeader
typedef struct gem5::GEM5_PACKED	sdmaDummyTrap
typedef struct gem5::GEM5_PACKED	sdmaDataFillMulti
typedef struct gem5::GEM5_PACKED	sdmaHeaderAgentDisp
typedef struct gem5::GEM5_PACKED	sdmaAQLCopy
typedef struct gem5::GEM5_PACKED	sdmaAQLBarrierOr
typedef uint32_t	_amd_queue_properties32_t
typedef int64_t	amd_signal_kind64_t
typedef struct gem5::amd_signal_s	amd_signal_t
template<class Compat >
using	IntSinkPin = IntSinkPinBase
template<class Compat >
using	IntSourcePin = IntSourcePinBase
typedef std::shared_ptr< EthPacketData >	EthPacketPtr
using	RegisterBankLE = RegisterBank< ByteOrder::little >
using	RegisterBankBE = RegisterBank< ByteOrder::big >
typedef std::map< P9MsgType, P9MsgInfo >	P9MsgInfoMap
typedef uint8_t	P9MsgType
typedef uint16_t	P9Tag
typedef struct gem5::GEM5_PACKED	AMDKernelCode
typedef std::bitset< std::numeric_limits< unsigned long long >::digits >	VectorMask
typedef std::shared_ptr< GPUDynInst >	GPUDynInstPtr
typedef MemBackdoor *	MemBackdoorPtr
typedef std::vector< ReplaceableEntry * >	ReplacementCandidates
	Replacement candidates as chosen by the indexing policy.
typedef uint32_t	CachesMask
using	BaseIndexingPolicy = IndexingPolicyTemplate< AddrTypes >
using	TaggedIndexingPolicy = IndexingPolicyTemplate< TaggedTypes >
typedef uint8_t *	PacketDataPtr
typedef std::list< PacketPtr >	PacketList
typedef uint64_t	PacketId
typedef std::shared_ptr< Request >	RequestPtr
typedef uint16_t	RequestorID
using	TranslationGenPtr = std::unique_ptr< TranslationGen >
template<class IntType >
using	AuxVector = gem5::auxv::AuxVector< IntType >
template<class T , void(T::*)() F>
using	EventWrapper = MemberEventWrapper< F >
typedef const char *	FaultName
typedef statistics::Scalar	FaultStat
typedef std::list< WaiterState >	WaiterList
template<typename T >
using	ConstVPtr = ConstProxyPtr< T, SETranslatingPortProxy >
template<typename T = void>
using	VPtr = ProxyPtr< T, SETranslatingPortProxy >
typedef std::ostream	CheckpointOut
typedef struct statfs	hst_statfs
typedef struct stat	hst_stat
typedef struct stat64	hst_stat64
typedef GenericSatCounter< uint8_t >	SatCounter8
typedef GenericSatCounter< uint16_t >	SatCounter16
typedef GenericSatCounter< uint32_t >	SatCounter32
typedef GenericSatCounter< uint64_t >	SatCounter64

Enumerations
enum	SDWASelVals : int {   SDWA_BYTE_0 = 0 , SDWA_BYTE_1 = 1 , SDWA_BYTE_2 = 2 , SDWA_BYTE_3 = 3 ,   SDWA_WORD_0 = 4 , SDWA_WORD_1 = 5 , SDWA_DWORD = 6 }
enum	SDWADstVals : int { SDWA_UNUSED_PAD = 0 , SDWA_UNUSED_SEXT = 1 , SDWA_UNUSED_PRESERVE = 2 }
enum	SqDPPVals : int {   SQ_DPP_QUAD_PERM_MAX = 0xFF , SQ_DPP_RESERVED = 0x100 , SQ_DPP_ROW_SL1 = 0x101 , SQ_DPP_ROW_SL15 = 0x10F ,   SQ_DPP_ROW_SR1 = 0x111 , SQ_DPP_ROW_SR15 = 0x11F , SQ_DPP_ROW_RR1 = 0x121 , SQ_DPP_ROW_RR15 = 0x12F ,   SQ_DPP_WF_SL1 = 0x130 , SQ_DPP_WF_RL1 = 0x134 , SQ_DPP_WF_SR1 = 0x138 , SQ_DPP_WF_RR1 = 0x13C ,   SQ_DPP_ROW_MIRROR = 0x140 , SQ_DPP_ROW_HALF_MIRROR = 0x141 , SQ_DPP_ROW_BCAST15 = 0x142 , SQ_DPP_ROW_BCAST31 = 0x143 }
enum	{   CoreTag = 0x54410001 , MemTag = 0x54410002 , RevTag = 0x54410007 , SerialTag = 0x54410006 ,   CmdTag = 0x54410009 , NoneTag = 0x00000000 }
enum class	RoundingMode { Downward = 0 , ToNearest = 1 , TowardZero = 2 , Upward = 3 }
enum	RegClassType {   IntRegClass , FloatRegClass , VecRegClass , VecElemClass ,   VecPredRegClass , MatRegClass , CCRegClass , MiscRegClass ,   InvalidRegClass = -1 }
	Enumerate the classes of registers. More...
enum	TrafficType {   BIT_COMPLEMENT_ = 0 , BIT_REVERSE_ = 1 , BIT_ROTATION_ = 2 , NEIGHBOR_ = 3 ,   SHUFFLE_ = 4 , TORNADO_ = 5 , TRANSPOSE_ = 6 , UNIFORM_RANDOM_ = 7 ,   NUM_TRAFFIC_PATTERNS_ }
enum	QueueType {   Compute , Gfx , SDMAGfx , SDMAPage ,   ComputeAQL , InterruptHandler , RLC }
enum	mmio_range_t : int {   NBIO_MMIO_RANGE , MMHUB_MMIO_RANGE , GFX_MMIO_RANGE , GRBM_MMIO_RANGE ,   IH_MMIO_RANGE , NUM_MMIO_RANGES }
enum	amdgpu_hwreg {   HW_REG_MODE = 0x1 , HW_REG_STATUS = 0x2 , HW_REG_TRAPSTS = 0x3 , HW_REG_HW_ID = 0x4 ,   HW_REG_GPR_ALLOC = 0x5 , HW_REG_LDS_ALLOC = 0x6 , HW_REG_IB_STS = 0x7 , HW_REG_SH_MEM_BASES = 0xf ,   HW_REG_TBA_LO = 0x10 , HW_REG_TBA_HI = 0x11 , HW_REG_TMA_LO = 0x12 , HW_REG_TMA_HI = 0x13 ,   HW_REG_FLAT_SCR_LO = 0x14 , HW_REG_FLAT_SCR_HI = 0x15 , HW_REG_XNACK_MASK = 0x16 , HW_REG_HW_ID1 = 0x17 ,   HW_REG_HW_ID2 = 0x18 , HW_REG_POPS_PACKER = 0x19 , HW_REG_SHADER_CYCLES = 0x1d }
enum	soc15_ih_clientid {   SOC15_IH_CLIENTID_RLC = 0x07 , SOC15_IH_CLIENTID_SDMA0 = 0x08 , SOC15_IH_CLIENTID_SDMA1 = 0x09 , SOC15_IH_CLIENTID_SDMA2 = 0x01 ,   SOC15_IH_CLIENTID_SDMA3 = 0x04 , SOC15_IH_CLIENTID_SDMA4 = 0x05 , SOC15_IH_CLIENTID_SDMA5 = 0x11 , SOC15_IH_CLIENTID_SDMA6 = 0x13 ,   SOC15_IH_CLIENTID_SDMA7 = 0x18 , SOC15_IH_CLIENTID_GRBM_CP = 0x14 }
	Defines from driver code. More...
enum	ihSourceId { CP_EOP = 181 , TRAP_ID = 224 }
enum	it_opcode_type {   IT_NOP = 0x10 , IT_WRITE_DATA = 0x37 , IT_WAIT_REG_MEM = 0x3C , IT_INDIRECT_BUFFER = 0x3F ,   IT_RELEASE_MEM = 0x49 , IT_SET_UCONFIG_REG = 0x79 , IT_SWITCH_BUFFER = 0x8B , IT_INVALIDATE_TLBS = 0x98 ,   IT_MAP_PROCESS = 0xA1 , IT_MAP_QUEUES = 0xA2 , IT_UNMAP_QUEUES = 0xA3 , IT_QUERY_STATUS = 0xA4 ,   IT_RUN_LIST = 0xA5 }
	PM4 opcodes. More...
enum class	ItsActionType { INITIAL_NOP , SEND_REQ , TERMINATE }
enum	{ SMMU_CACHE_REPL_ROUND_ROBIN , SMMU_CACHE_REPL_RANDOM , SMMU_CACHE_REPL_LRU }
enum	{ SMMU_SECURE_SZ = 0x184 , SMMU_PAGE_ZERO_SZ = 0x10000 , SMMU_PAGE_ONE_SZ = 0x10000 , SMMU_REG_SIZE = SMMU_PAGE_ONE_SZ + SMMU_PAGE_ZERO_SZ }
enum	{   STE_CONFIG_ABORT = 0x0 , STE_CONFIG_BYPASS = 0x4 , STE_CONFIG_STAGE1_ONLY = 0x5 , STE_CONFIG_STAGE2_ONLY = 0x6 ,   STE_CONFIG_STAGE1_AND_2 = 0x7 }
enum	{ STAGE1_CFG_1L = 0x0 , STAGE1_CFG_2L_4K = 0x1 , STAGE1_CFG_2L_64K = 0x2 }
enum	{ ST_CFG_SPLIT_SHIFT = 6 , ST_CD_ADDR_SHIFT = 6 , CD_TTB_SHIFT = 4 , STE_S2TTB_SHIFT = 4 }
enum	{ TRANS_GRANULE_4K = 0x0 , TRANS_GRANULE_64K = 0x1 , TRANS_GRANULE_16K = 0x2 , TRANS_GRANULE_INVALID = 0x3 }
enum	{   ST_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL , ST_CFG_SIZE_MASK = 0x000000000000003fULL , ST_CFG_SPLIT_MASK = 0x00000000000007c0ULL , ST_CFG_FMT_MASK = 0x0000000000030000ULL ,   ST_CFG_FMT_LINEAR = 0x0000000000000000ULL , ST_CFG_FMT_2LEVEL = 0x0000000000010000ULL , ST_L2_SPAN_MASK = 0x000000000000001fULL , ST_L2_ADDR_MASK = 0x0000ffffffffffe0ULL ,   VMT_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL , VMT_BASE_SIZE_MASK = 0x000000000000001fULL , Q_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL , Q_BASE_SIZE_MASK = 0x000000000000001fULL ,   E_BASE_ADDR_MASK = 0x0000fffffffffffcULL }
enum	{   CR0_SMMUEN_MASK = 0x1 , CR0_PRIQEN_MASK = 0x2 , CR0_EVENTQEN_MASK = 0x4 , CR0_CMDQEN_MASK = 0x8 ,   CR0_ATSCHK_MASK = 0x10 , CR0_VMW_MASK = 0x1C0 }
enum	SMMUCommandType {   CMD_PRF_CONFIG = 0x01 , CMD_PRF_ADDR = 0x02 , CMD_CFGI_STE = 0x03 , CMD_CFGI_STE_RANGE = 0x04 ,   CMD_CFGI_CD = 0x05 , CMD_CFGI_CD_ALL = 0x06 , CMD_TLBI_NH_ALL = 0x10 , CMD_TLBI_NH_ASID = 0x11 ,   CMD_TLBI_NH_VAA = 0x13 , CMD_TLBI_NH_VA = 0x12 , CMD_TLBI_EL3_ALL = 0x18 , CMD_TLBI_EL3_VA = 0x1A ,   CMD_TLBI_EL2_ALL = 0x20 , CMD_TLBI_EL2_ASID = 0x21 , CMD_TLBI_EL2_VA = 0x22 , CMD_TLBI_EL2_VAA = 0x23 ,   CMD_TLBI_S2_IPA = 0x2a , CMD_TLBI_S12_VMALL = 0x28 , CMD_TLBI_NSNH_ALL = 0x30 , CMD_ATC_INV = 0x40 ,   CMD_PRI_RESP = 0x41 , CMD_RESUME = 0x44 , CMD_STALL_TERM = 0x45 , CMD_SYNC = 0x46 }
enum	{ SMMU_MAX_TRANS_ID = 64 }
enum	SMMUActionType {   ACTION_INITIAL_NOP , ACTION_SEND_REQ , ACTION_SEND_REQ_FINAL , ACTION_SEND_RESP ,   ACTION_SEND_RESP_ATS , ACTION_DELAY , ACTION_SLEEP , ACTION_TERMINATE }
enum	Q_STATE { UNBLOCKED = 0 , BLOCKED_BBIT , BLOCKED_BPKT }
enum	_hsa_queue_type_t { _HSA_QUEUE_TYPE_MULTI = 0 , _HSA_QUEUE_TYPE_SINGLE = 1 }
enum	amd_signal_kind_t { AMD_SIGNAL_KIND_INVALID = 0 , AMD_SIGNAL_KIND_USER = 1 , AMD_SIGNAL_KIND_DOORBELL = -1 , AMD_SIGNAL_KIND_LEGACY_DOORBELL = -2 }
enum	kfd_smi_event {   KFD_SMI_EVENT_NONE = 0 , KFD_SMI_EVENT_VMFAULT = 1 , KFD_SMI_EVENT_THERMAL_THROTTLE = 2 , KFD_SMI_EVENT_GPU_PRE_RESET = 3 ,   KFD_SMI_EVENT_GPU_POST_RESET = 4 }
enum	kfd_mmio_remap { KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0 , KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4 }
enum	DeviceRegisterAddress {   CR = 0x00 , CFGR = 0x04 , MEAR = 0x08 , PTSCR = 0x0c ,   ISR = 0x10 , IMR = 0x14 , IER = 0x18 , IHR = 0x1c ,   TXDP = 0x20 , TXDP_HI = 0x24 , TX_CFG = 0x28 , GPIOR = 0x2c ,   RXDP = 0x30 , RXDP_HI = 0x34 , RX_CFG = 0x38 , PQCR = 0x3c ,   WCSR = 0x40 , PCR = 0x44 , RFCR = 0x48 , RFDR = 0x4c ,   BRAR = 0x50 , BRDR = 0x54 , SRR = 0x58 , MIBC = 0x5c ,   MIB_START = 0x60 , MIB_END = 0x88 , VRCR = 0xbc , VTCR = 0xc0 ,   VDR = 0xc4 , CCSR = 0xcc , TBICR = 0xe0 , TBISR = 0xe4 ,   TANAR = 0xe8 , TANLPAR = 0xec , TANER = 0xf0 , TESR = 0xf4 ,   M5REG = 0xf8 , LAST = 0xf8 , RESERVED = 0xfc }
enum	ChipCommandRegister {   CR_TXE = 0x00000001 , CR_TXD = 0x00000002 , CR_RXE = 0x00000004 , CR_RXD = 0x00000008 ,   CR_TXR = 0x00000010 , CR_RXR = 0x00000020 , CR_SWI = 0x00000080 , CR_RST = 0x00000100 }
enum	ConfigurationRegisters {   CFGR_ZERO = 0x00000000 , CFGR_LNKSTS = 0x80000000 , CFGR_SPDSTS = 0x60000000 , CFGR_SPDSTS1 = 0x40000000 ,   CFGR_SPDSTS0 = 0x20000000 , CFGR_DUPSTS = 0x10000000 , CFGR_TBI_EN = 0x01000000 , CFGR_RESERVED = 0x0e000000 ,   CFGR_MODE_1000 = 0x00400000 , CFGR_AUTO_1000 = 0x00200000 , CFGR_PINT_CTL = 0x001c0000 , CFGR_PINT_DUPSTS = 0x00100000 ,   CFGR_PINT_LNKSTS = 0x00080000 , CFGR_PINT_SPDSTS = 0x00040000 , CFGR_TMRTEST = 0x00020000 , CFGR_MRM_DIS = 0x00010000 ,   CFGR_MWI_DIS = 0x00008000 , CFGR_T64ADDR = 0x00004000 , CFGR_PCI64_DET = 0x00002000 , CFGR_DATA64_EN = 0x00001000 ,   CFGR_M64ADDR = 0x00000800 , CFGR_PHY_RST = 0x00000400 , CFGR_PHY_DIS = 0x00000200 , CFGR_EXTSTS_EN = 0x00000100 ,   CFGR_REQALG = 0x00000080 , CFGR_SB = 0x00000040 , CFGR_POW = 0x00000020 , CFGR_EXD = 0x00000010 ,   CFGR_PESEL = 0x00000008 , CFGR_BROM_DIS = 0x00000004 , CFGR_EXT_125 = 0x00000002 , CFGR_BEM = 0x00000001 }
enum	EEPROMAccessRegister {   MEAR_EEDI = 0x00000001 , MEAR_EEDO = 0x00000002 , MEAR_EECLK = 0x00000004 , MEAR_EESEL = 0x00000008 ,   MEAR_MDIO = 0x00000010 , MEAR_MDDIR = 0x00000020 , MEAR_MDC = 0x00000040 }
enum	PCITestControlRegister {   PTSCR_EEBIST_FAIL = 0x00000001 , PTSCR_EEBIST_EN = 0x00000002 , PTSCR_EELOAD_EN = 0x00000004 , PTSCR_RBIST_FAIL = 0x000001b8 ,   PTSCR_RBIST_DONE = 0x00000200 , PTSCR_RBIST_EN = 0x00000400 , PTSCR_RBIST_RST = 0x00002000 , PTSCR_RBIST_RDONLY = 0x000003f9 }
enum	InterruptStatusRegister {   ISR_RESERVE = 0x80000000 , ISR_TXDESC3 = 0x40000000 , ISR_TXDESC2 = 0x20000000 , ISR_TXDESC1 = 0x10000000 ,   ISR_TXDESC0 = 0x08000000 , ISR_RXDESC3 = 0x04000000 , ISR_RXDESC2 = 0x02000000 , ISR_RXDESC1 = 0x01000000 ,   ISR_RXDESC0 = 0x00800000 , ISR_TXRCMP = 0x00400000 , ISR_RXRCMP = 0x00200000 , ISR_DPERR = 0x00100000 ,   ISR_SSERR = 0x00080000 , ISR_RMABT = 0x00040000 , ISR_RTAB = 0x00020000 , ISR_RXSOVR = 0x00010000 ,   ISR_HIBINT = 0x00008000 , ISR_PHY = 0x00004000 , ISR_PME = 0x00002000 , ISR_SWI = 0x00001000 ,   ISR_MIB = 0x00000800 , ISR_TXURN = 0x00000400 , ISR_TXIDLE = 0x00000200 , ISR_TXERR = 0x00000100 ,   ISR_TXDESC = 0x00000080 , ISR_TXOK = 0x00000040 , ISR_RXORN = 0x00000020 , ISR_RXIDLE = 0x00000010 ,   ISR_RXEARLY = 0x00000008 , ISR_RXERR = 0x00000004 , ISR_RXDESC = 0x00000002 , ISR_RXOK = 0x00000001 ,   ISR_ALL = 0x7FFFFFFF , ISR_DELAY , ISR_NODELAY = (ISR_ALL & ~ISR_DELAY) , ISR_IMPL ,   ISR_NOIMPL = (ISR_ALL & ~ISR_IMPL) }
enum	TransmitConfigurationRegister {   TX_CFG_CSI = 0x80000000 , TX_CFG_HBI = 0x40000000 , TX_CFG_MLB = 0x20000000 , TX_CFG_ATP = 0x10000000 ,   TX_CFG_ECRETRY = 0x00800000 , TX_CFG_BRST_DIS = 0x00080000 , TX_CFG_MXDMA1024 = 0x00000000 , TX_CFG_MXDMA512 = 0x00700000 ,   TX_CFG_MXDMA256 = 0x00600000 , TX_CFG_MXDMA128 = 0x00500000 , TX_CFG_MXDMA64 = 0x00400000 , TX_CFG_MXDMA32 = 0x00300000 ,   TX_CFG_MXDMA16 = 0x00200000 , TX_CFG_MXDMA8 = 0x00100000 , TX_CFG_MXDMA = 0x00700000 , TX_CFG_FLTH_MASK = 0x0000ff00 ,   TX_CFG_DRTH_MASK = 0x000000ff }
enum	GeneralPurposeIOControlRegister {   GPIOR_UNUSED = 0xffff8000 , GPIOR_GP5_IN = 0x00004000 , GPIOR_GP4_IN = 0x00002000 , GPIOR_GP3_IN = 0x00001000 ,   GPIOR_GP2_IN = 0x00000800 , GPIOR_GP1_IN = 0x00000400 , GPIOR_GP5_OE = 0x00000200 , GPIOR_GP4_OE = 0x00000100 ,   GPIOR_GP3_OE = 0x00000080 , GPIOR_GP2_OE = 0x00000040 , GPIOR_GP1_OE = 0x00000020 , GPIOR_GP5_OUT = 0x00000010 ,   GPIOR_GP4_OUT = 0x00000008 , GPIOR_GP3_OUT = 0x00000004 , GPIOR_GP2_OUT = 0x00000002 , GPIOR_GP1_OUT = 0x00000001 }
enum	ReceiveConfigurationRegister {   RX_CFG_AEP = 0x80000000 , RX_CFG_ARP = 0x40000000 , RX_CFG_STRIPCRC = 0x20000000 , RX_CFG_RX_FD = 0x10000000 ,   RX_CFG_ALP = 0x08000000 , RX_CFG_AIRL = 0x04000000 , RX_CFG_MXDMA512 = 0x00700000 , RX_CFG_MXDMA = 0x00700000 ,   RX_CFG_DRTH = 0x0000003e , RX_CFG_DRTH0 = 0x00000002 }
enum	PauseControlStatusRegister {   PCR_PSEN = (1 << 31) , PCR_PS_MCAST = (1 << 30) , PCR_PS_DA = (1 << 29) , PCR_STHI_8 = (3 << 23) ,   PCR_STLO_4 = (1 << 23) , PCR_FFHI_8K = (3 << 21) , PCR_FFLO_4K = (1 << 21) , PCR_PAUSE_CNT = 0xFFFE }
enum	ReceiveFilterMatchControlRegister {   RFCR_RFEN = 0x80000000 , RFCR_AAB = 0x40000000 , RFCR_AAM = 0x20000000 , RFCR_AAU = 0x10000000 ,   RFCR_APM = 0x08000000 , RFCR_APAT = 0x07800000 , RFCR_APAT3 = 0x04000000 , RFCR_APAT2 = 0x02000000 ,   RFCR_APAT1 = 0x01000000 , RFCR_APAT0 = 0x00800000 , RFCR_AARP = 0x00400000 , RFCR_MHEN = 0x00200000 ,   RFCR_UHEN = 0x00100000 , RFCR_ULM = 0x00080000 , RFCR_RFADDR = 0x000003ff }
enum	ReceiveFilterMatchDataRegister { RFDR_BMASK = 0x00030000 , RFDR_RFDATA0 = 0x000000ff , RFDR_RFDATA1 = 0x0000ff00 }
enum	ManagementInformationBaseControlRegister { MIBC_MIBS = 0x00000008 , MIBC_ACLR = 0x00000004 , MIBC_FRZ = 0x00000002 , MIBC_WRN = 0x00000001 }
enum	VLANIPReceiveControlRegister {   VRCR_RUDPE = 0x00000080 , VRCR_RTCPE = 0x00000040 , VRCR_RIPE = 0x00000020 , VRCR_IPEN = 0x00000010 ,   VRCR_DUTF = 0x00000008 , VRCR_DVTF = 0x00000004 , VRCR_VTREN = 0x00000002 , VRCR_VTDEN = 0x00000001 }
enum	VLANIPTransmitControlRegister { VTCR_PPCHK = 0x00000008 , VTCR_GCHK = 0x00000004 , VTCR_VPPTI = 0x00000002 , VTCR_VGTI = 0x00000001 }
enum	ClockrunControlStatusRegister { CCSR_CLKRUN_EN = 0x00000001 }
enum	TBIControlRegister { TBICR_MR_LOOPBACK = 0x00004000 , TBICR_MR_AN_ENABLE = 0x00001000 , TBICR_MR_RESTART_AN = 0x00000200 }
enum	TBIStatusRegister { TBISR_MR_LINK_STATUS = 0x00000020 , TBISR_MR_AN_COMPLETE = 0x00000004 }
enum	TBIAutoNegotiationAdvertisementRegister {   TANAR_NP = 0x00008000 , TANAR_RF2 = 0x00002000 , TANAR_RF1 = 0x00001000 , TANAR_PS2 = 0x00000100 ,   TANAR_PS1 = 0x00000080 , TANAR_HALF_DUP = 0x00000040 , TANAR_FULL_DUP = 0x00000020 , TANAR_UNUSED = 0x00000E1F }
enum	M5ControlRegister { M5REG_RESERVED = 0xfffffffc , M5REG_RSS = 0x00000004 , M5REG_RX_THREAD = 0x00000002 , M5REG_TX_THREAD = 0x00000001 }
enum	CMDSTSFlatsForDescriptors {   CMDSTS_OWN = 0x80000000 , CMDSTS_MORE = 0x40000000 , CMDSTS_INTR = 0x20000000 , CMDSTS_ERR = 0x10000000 ,   CMDSTS_OK = 0x08000000 , CMDSTS_LEN_MASK = 0x0000ffff , CMDSTS_DEST_MASK = 0x01800000 , CMDSTS_DEST_SELF = 0x00800000 ,   CMDSTS_DEST_MULTI = 0x01000000 }
enum	ExtendedFlagsForDescriptors {   EXTSTS_UDPERR = 0x00400000 , EXTSTS_UDPPKT = 0x00200000 , EXTSTS_TCPERR = 0x00100000 , EXTSTS_TCPPKT = 0x00080000 ,   EXTSTS_IPERR = 0x00040000 , EXTSTS_IPPKT = 0x00020000 }
enum class	PciIntPin : uint8_t {   NO_INT =0 , INTA , INTB , INTC ,   INTD }
enum	BMIRegOffset { BMICommand = 0x0 , BMIStatus = 0x2 , BMIDescTablePtr = 0x4 }
enum	Events_t {   None = 0 , Transfer , ReadWait , WriteWait ,   PrdRead , DmaRead , DmaWrite }
enum	DevAction_t {   ACT_NONE = 0 , ACT_CMD_WRITE , ACT_CMD_COMPLETE , ACT_CMD_ERROR ,   ACT_SELECT_WRITE , ACT_STAT_READ , ACT_DATA_READY , ACT_DATA_READ_BYTE ,   ACT_DATA_READ_SHORT , ACT_DATA_WRITE_BYTE , ACT_DATA_WRITE_SHORT , ACT_DMA_READY ,   ACT_DMA_DONE , ACT_SRST_SET , ACT_SRST_CLEAR }
enum	DevState_t {   Device_Idle_S = 0 , Device_Idle_SI , Device_Idle_NS , Device_Srst ,   Command_Execution , Prepare_Data_In , Data_Ready_INTRQ_In , Transfer_Data_In ,   Prepare_Data_Out , Data_Ready_INTRQ_Out , Transfer_Data_Out , Prepare_Data_Dma ,   Transfer_Data_Dma , Device_Dma_Abort }
enum	DmaState_t { Dma_Idle = 0 , Dma_Start , Dma_Transfer }
enum	EXEC_POLICY { OLDEST = 0 , RR }
enum	TLB_CACHE { TLB_MISS_CACHE_MISS = 0 , TLB_MISS_CACHE_HIT , TLB_HIT_CACHE_MISS , TLB_HIT_CACHE_HIT }
enum	STAT_STATUS { IdleExec , BusyExec , PostExec }
enum	DISPATCH_STATUS { EMPTY = 0 , EXREADY , SKIP }
enum	ScalarRegInitFields : int {   PrivateSegBuf = 0 , DispatchPtr = 1 , QueuePtr = 2 , KernargSegPtr = 3 ,   DispatchId = 4 , FlatScratchInit = 5 , PrivateSegSize = 6 , WorkgroupIdX = 7 ,   WorkgroupIdY = 8 , WorkgroupIdZ = 9 , WorkgroupInfo = 10 , PrivSegWaveByteOffset = 11 ,   NumScalarInitFields = 12 }
	these enums represent the indices into the initialRegState bitfields in HsaKernelInfo. More...
enum	VectorRegInitFields : int { WorkitemIdX = 0 , WorkitemIdY = 1 , WorkitemIdZ = 2 , NumVectorInitFields = 3 }
enum	InstMemoryHop : int {   Initiate = 0 , CoalsrSend = 1 , CoalsrRecv = 2 , GMEnqueue = 3 ,   Complete = 4 , InstMemoryHopMax = 5 }
enum	BlockMemoryHop : int { BlockSend = 0 , BlockRecv = 1 }
enum class	HtmFailureFaultCause : int {   INVALID = -1 , EXPLICIT , NEST , SIZE ,   EXCEPTION , MEMORY , OTHER , NUM_CAUSES }
enum class	HtmCacheFailure { NO_FAIL , FAIL_SELF , FAIL_REMOTE , FAIL_OTHER }
enum	AuxiliaryVectorType {   GEM5_DEPRECATE_AT =(NULL, Null) , GEM5_DEPRECATE_AT =(NULL, Null) , GEM5_DEPRECATE_AT =(NULL, Null) , GEM5_DEPRECATE_AT =(NULL, Null) ,   GEM5_DEPRECATE_AT =(NULL, Null) , GEM5_DEPRECATE_AT =(NULL, Null) , GEM5_DEPRECATE_AT =(NULL, Null) , GEM5_DEPRECATE_AT =(NULL, Null) ,   GEM5_DEPRECATE_AT =(NULL, Null) , GEM5_DEPRECATE_AT =(NULL, Null) , GEM5_DEPRECATE_AT =(NULL, Null) , GEM5_DEPRECATE_AT =(NULL, Null) ,   GEM5_DEPRECATE_AT =(NULL, Null) , GEM5_DEPRECATE_AT =(NULL, Null) , GEM5_DEPRECATE_AT =(NULL, Null) , GEM5_DEPRECATE_AT =(NULL, Null) ,   GEM5_DEPRECATE_AT =(NULL, Null) , GEM5_DEPRECATE_AT =(NULL, Null) , GEM5_DEPRECATE_AT =(NULL, Null) , M5_BASE_PLATFORM ,   GEM5_DEPRECATE_AT =(NULL, Null) , GEM5_DEPRECATE_AT =(NULL, Null) , GEM5_DEPRECATE_AT =(NULL, Null) }
enum class	DrainState { DrainState::Running , DrainState::Draining , DrainState::Drained , DrainState::Resuming }
	Object drain/handover states. More...

Functions
template<typename T , int N>
void	initMemReqHelper (GPUDynInstPtr gpuDynInst, MemCmd mem_req_type, bool is_atomic=false)
	Helper function for instructions declared in op_encodings.
template<int N>
void	initScratchReqHelper (GPUDynInstPtr gpuDynInst, MemCmd mem_req_type)
template<typename T , int N>
void	initMemReqScalarHelper (GPUDynInstPtr gpuDynInst, MemCmd mem_req_type)
	Helper function for scalar instructions declared in op_encodings.
static const uint64_t	KVM_REG64_TTBR0 (regCp64(15, 0, 2))
static const uint64_t	KVM_REG64_TTBR1 (regCp64(15, 1, 2))
constexpr uint64_t	kvmXReg (const int num)
constexpr uint64_t	kvmFPReg (const int num)
static bool	tryTranslate (ThreadContext *tc, Addr addr)
template<class XC >
Fault	initiateMemRead (XC *xc, Addr addr, std::size_t size, Request::Flags flags, const std::vector< bool > &byte_enable)
template<class XC , class MemT >
Fault	initiateMemRead (XC *xc, trace::InstRecord *traceData, Addr addr, MemT &mem, Request::Flags flags)
	Initiate a read from memory in timing mode.
template<ByteOrder Order, class MemT >
void	getMem (PacketPtr pkt, MemT &mem, trace::InstRecord *traceData)
	Extract the data returned from a timing mode read.
template<class MemT >
void	getMemLE (PacketPtr pkt, MemT &mem, trace::InstRecord *traceData)
template<class MemT >
void	getMemBE (PacketPtr pkt, MemT &mem, trace::InstRecord *traceData)
template<class XC >
Fault	readMemAtomic (XC *xc, Addr addr, uint8_t *mem, std::size_t size, Request::Flags flags, const std::vector< bool > &byte_enable)
	Read from memory in atomic mode.
template<ByteOrder Order, class XC , class MemT >
Fault	readMemAtomic (XC *xc, trace::InstRecord *traceData, Addr addr, MemT &mem, Request::Flags flags)
	Read from memory in atomic mode.
template<ByteOrder Order, class XC , class MemT >
Fault	readMemAtomic (XC *xc, trace::InstRecord *traceData, Addr addr, MemT &mem, size_t size, Request::Flags flags)
	Read from memory in atomic mode.
template<class XC , class MemT >
Fault	readMemAtomicLE (XC *xc, trace::InstRecord *traceData, Addr addr, MemT &mem, Request::Flags flags)
template<class XC , class MemT >
Fault	readMemAtomicLE (XC *xc, trace::InstRecord *traceData, Addr addr, MemT &mem, size_t size, Request::Flags flags)
template<class XC , class MemT >
Fault	readMemAtomicBE (XC *xc, trace::InstRecord *traceData, Addr addr, MemT &mem, Request::Flags flags)
template<class XC >
Fault	writeMemTiming (XC *xc, uint8_t *mem, Addr addr, std::size_t size, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)
	Write to memory in timing mode.
template<ByteOrder Order, class XC , class MemT >
Fault	writeMemTiming (XC *xc, trace::InstRecord *traceData, MemT mem, Addr addr, Request::Flags flags, uint64_t *res)
template<ByteOrder Order, class XC , class MemT >
Fault	writeMemTiming (XC *xc, trace::InstRecord *traceData, MemT mem, Addr addr, size_t size, Request::Flags flags, uint64_t *res)
template<class XC , class MemT >
Fault	writeMemTimingLE (XC *xc, trace::InstRecord *traceData, MemT mem, Addr addr, Request::Flags flags, uint64_t *res)
template<class XC , class MemT >
Fault	writeMemTimingLE (XC *xc, trace::InstRecord *traceData, MemT mem, Addr addr, size_t size, Request::Flags flags, uint64_t *res)
template<class XC , class MemT >
Fault	writeMemTimingBE (XC *xc, trace::InstRecord *traceData, MemT mem, Addr addr, Request::Flags flags, uint64_t *res)
template<class XC >
Fault	writeMemAtomic (XC *xc, uint8_t *mem, Addr addr, std::size_t size, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)
	Write to memory in atomic mode.
template<ByteOrder Order, class XC , class MemT >
Fault	writeMemAtomic (XC *xc, trace::InstRecord *traceData, const MemT &mem, Addr addr, Request::Flags flags, uint64_t *res)
template<ByteOrder Order, class XC , class MemT >
Fault	writeMemAtomic (XC *xc, trace::InstRecord *traceData, const MemT &mem, Addr addr, size_t size, Request::Flags flags, uint64_t *res)
template<class XC , class MemT >
Fault	writeMemAtomicLE (XC *xc, trace::InstRecord *traceData, const MemT &mem, Addr addr, Request::Flags flags, uint64_t *res)
template<class XC , class MemT >
Fault	writeMemAtomicLE (XC *xc, trace::InstRecord *traceData, const MemT &mem, size_t size, Addr addr, Request::Flags flags, uint64_t *res)
template<class XC , class MemT >
Fault	writeMemAtomicBE (XC *xc, trace::InstRecord *traceData, const MemT &mem, Addr addr, Request::Flags flags, uint64_t *res)
template<ByteOrder Order, class XC , class MemT >
Fault	amoMemAtomic (XC *xc, trace::InstRecord *traceData, MemT &mem, Addr addr, Request::Flags flags, AtomicOpFunctor *_amo_op)
	Do atomic read-modify-write (AMO) in atomic mode.
template<class XC , class MemT >
Fault	amoMemAtomicLE (XC *xc, trace::InstRecord *traceData, MemT &mem, Addr addr, Request::Flags flags, AtomicOpFunctor *_amo_op)
template<class XC , class MemT >
Fault	amoMemAtomicBE (XC *xc, trace::InstRecord *traceData, MemT &mem, Addr addr, Request::Flags flags, AtomicOpFunctor *_amo_op)
template<class XC , class MemT >
Fault	initiateMemAMO (XC *xc, trace::InstRecord *traceData, Addr addr, MemT &mem, Request::Flags flags, AtomicOpFunctor *_amo_op)
	Do atomic read-modify-wrote (AMO) in timing mode.
static std::ostream &	operator<< (std::ostream &os, const PCStateBase &pc)
static bool	operator== (const PCStateBase &a, const PCStateBase &b)
static bool	operator!= (const PCStateBase &a, const PCStateBase &b)
std::ostream &	operator<< (std::ostream &os, const BaseSemihosting::InPlaceArg &ipa)
auto	operator& (TypeTLB lhs, TypeTLB rhs)
	Implementing the "&" bitwise operator for TypeTLB allows us to handle TypeTLB::unified efficiently.
typedef	GEM5_ALIGNED (8) uint64_t uint64_ta
template<typename xint >
static void	setRegNoEffectWithMask (ThreadContext *context, RiscvType type, PrivilegeModeSet pms, CSRIndex idx, xint val)
template<typename xint >
static void	setRegWithMask (ThreadContext *context, RiscvType type, PrivilegeModeSet pms, CSRIndex idx, xint val)
static Addr	buildKey (Addr vpn, uint16_t asid)
static std::string	getMiscRegName (RegIndex index)
template<class T >
void	writeVal (T val, PortProxy &proxy, Addr &addr)
template<class T >
uint8_t	writeOutField (PortProxy &proxy, Addr addr, T val)
uint8_t	writeOutString (PortProxy &proxy, Addr addr, std::string str, int length)
template<class T >
uint64_t	composeBitVector (T vec)
int	divideFromConf (uint32_t conf)
	BitUnion64 (XStateBV) Bitfield< 0 > fpu
	EndBitUnion (XStateBV) struct XSaveHeader
template<typename Struct , typename Entry >
static auto	newVarStruct (size_t entries)
static void	dumpKvm (const struct kvm_regs &regs)
static void	dumpKvm (const char *reg_name, const struct kvm_segment &seg)
static void	dumpKvm (const char *reg_name, const struct kvm_dtable &dtable)
static void	dumpKvm (const struct kvm_sregs &sregs)
static void	dumpFpuSpec (const struct FXSave &xs)
static void	dumpFpuSpec (const struct kvm_fpu &fpu)
template<typename T >
static void	dumpFpuCommon (const T &fpu)
static void	dumpKvm (const struct kvm_fpu &fpu)
static void	dumpKvm (const struct kvm_xsave &xsave)
static void	dumpKvm (const struct kvm_msrs &msrs)
static void	dumpKvm (const struct kvm_xcrs &regs)
static void	dumpKvm (const struct kvm_vcpu_events &events)
static bool	isCanonicalAddress (uint64_t addr)
static void	checkSeg (const char *name, const int idx, const struct kvm_segment &seg, struct kvm_sregs sregs)
static void	setKvmSegmentReg (ThreadContext *tc, struct kvm_segment &kvm_seg, const int index)
static void	setKvmDTableReg (ThreadContext *tc, struct kvm_dtable &kvm_dtable, const int index)
static void	forceSegAccessed (struct kvm_segment &seg)
template<typename T >
static void	updateKvmStateFPUCommon (ThreadContext *tc, T &fpu)
void	setContextSegment (ThreadContext *tc, const struct kvm_segment &kvm_seg, const int index)
void	setContextSegment (ThreadContext *tc, const struct kvm_dtable &kvm_dtable, const int index)
template<typename T >
static void	updateThreadContextFPUCommon (ThreadContext *tc, const T &fpu)
static struct kvm_cpuid_entry2	makeKvmCpuid (uint32_t function, uint32_t index, CpuidResult &result, uint32_t flags=0)
template<>
void	paramOut (CheckpointOut &cp, const std::string &name, ExtMachInst const &machInst)
template<>
void	paramIn (CheckpointIn &cp, const std::string &name, ExtMachInst &machInst)
template<>
void	paramOut (CheckpointOut &cp, const std::string &name, const X86ISA::ExtMachInst &machInst)
template<>
void	paramIn (CheckpointIn &cp, const std::string &name, X86ISA::ExtMachInst &machInst)
static AddrRangeList	operator- (const AddrRange &range, const AddrRangeList &to_exclude)
static AddrRangeList	operator- (const AddrRange &range, const AddrRange &to_exclude)
static AddrRangeList	exclude (const AddrRangeList &base, AddrRangeList to_exclude)
static AddrRangeList	exclude (const AddrRangeList &base, const AddrRange &to_exclude)
static AddrRangeList	operator- (const AddrRangeList &base, const AddrRangeList &to_exclude)
static AddrRangeList	operator-= (AddrRangeList &base, const AddrRangeList &to_exclude)
static AddrRangeList	operator- (const AddrRangeList &base, const AddrRange &to_exclude)
static AddrRangeList	operator-= (AddrRangeList &base, const AddrRange &to_exclude)
AddrRange	RangeEx (Addr start, Addr end)
AddrRange	RangeIn (Addr start, Addr end)
AddrRange	RangeSize (Addr start, Addr size)
ssize_t	atomic_read (int fd, void *s, size_t n)
ssize_t	atomic_write (int fd, const void *s, size_t n)
constexpr uint64_t	mask (unsigned nbits)
	Generate a 64-bit mask of 'nbits' 1s, right justified.
template<class T >
constexpr T	bits (T val, unsigned first, unsigned last)
	Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
template<class T >
constexpr T	bits (T val, unsigned bit)
	Extract the bit from this position from 'val' and right justify it.
template<class T >
constexpr T	mbits (T val, unsigned first, unsigned last)
	Mask off the given bits in place like bits() but without shifting.
constexpr uint64_t	mask (unsigned first, unsigned last)
template<int N>
constexpr uint64_t	sext (uint64_t val)
	Sign-extend an N-bit value to 64 bits.
constexpr uint64_t	sext (uint64_t val, int N)
	Sign-extend an N-bit value to 64 bits.
template<int N>
constexpr uint64_t	szext (uint64_t val)
	Sign-extend an N-bit value to 64 bits.
template<class T , class B >
constexpr T	insertBits (T val, unsigned first, unsigned last, B bit_val)
	Returns val with bits first to last set to the LSBs of bit_val.
template<class T , class B >
constexpr T	insertBits (T val, unsigned bit, B bit_val)
	Overloaded for access to only one bit in value.
template<class T , class B >
constexpr void	replaceBits (T &val, unsigned first, unsigned last, B bit_val)
	A convenience function to replace bits first to last of val with bit_val in place.
template<class T , class B >
constexpr void	replaceBits (T &val, unsigned bit, B bit_val)
	Overloaded function to allow to access only 1 bit.
template<class T >
std::enable_if_t< std::is_integral_v< T >, T >	reverseBits (T val, size_t size=sizeof(T))
	Takes a value and returns the bit reversed version.
constexpr int	findMsbSet (uint64_t val)
	Returns the bit position of the MSB that is set in the input.
constexpr int	findLsbSet (uint64_t val)
	Returns the bit position of the LSB that is set in the input That function will either use a builtin that exploit a "count trailing zeros" instruction or use fall back method, findLsbSetFallback.
template<size_t N>
constexpr int	findLsbSet (std::bitset< N > bs)
constexpr int	popCount (uint64_t val)
	Returns the number of set ones in the provided value.
constexpr uint64_t	alignToPowerOfTwo (uint64_t val)
	Align to the next highest power of two.
constexpr int	ctz32 (uint32_t value)
	Count trailing zeros in a 32-bit value.
constexpr int	ctz64 (uint64_t value)
	Count trailing zeros in a 64-bit value.
constexpr int	clz32 (uint32_t value)
	Count leading zeros in a 32-bit value.
constexpr int	clz64 (uint64_t value)
	Count leading zeros in a 64-bit value.
template<typename T >
std::ostream &	operator<< (std::ostream &os, const BitUnionType< T > &bu)
	A default << operator which casts a bitunion to its underlying type and passes it to bitfield_backend::bitfieldBackendPrinter.
template<class T , class U >
T	safe_cast (U &&ref_or_ptr)
std::ostream &	operator<< (std::ostream &out, const gem5::ChannelAddr &addr)
template<typename T >
void	arrayParamOut (CheckpointOut &cp, const std::string &name, const CircleBuf< T > &param)
template<typename T >
void	arrayParamIn (CheckpointIn &cp, const std::string &name, CircleBuf< T > &param)
template<typename T >
void	arrayParamOut (CheckpointOut &cp, const std::string &name, const Fifo< T > &param)
template<typename T >
void	arrayParamIn (CheckpointIn &cp, const std::string &name, Fifo< T > &param)
static bool	findCarry (int width, uint64_t dest, uint64_t src1, uint64_t src2)
	Calculate the carry flag from an addition.
static bool	findOverflow (int width, uint64_t dest, uint64_t src1, uint64_t src2)
	Calculate the overflow flag from an addition.
static bool	findParity (int width, uint64_t dest)
	Calculate the parity of a value.
static bool	findNegative (int width, uint64_t dest)
	Calculate the negative flag.
static bool	findZero (int width, uint64_t dest)
	Calculate the zero flag.
void	ccprintf (cp::Print &print)
template<typename T , typename ... Args>
void	ccprintf (cp::Print &print, const T &value, const Args &...args)
template<typename ... Args>
void	ccprintf (std::ostream &stream, const char *format, const Args &...args)
template<typename ... Args>
void	cprintf (const char *format, const Args &...args)
template<typename ... Args>
std::string	csprintf (const char *format, const Args &...args)
template<typename ... Args>
void	ccprintf (std::ostream &stream, const std::string &format, const Args &...args)
template<typename ... Args>
void	cprintf (const std::string &format, const Args &...args)
template<typename ... Args>
std::string	csprintf (const std::string &format, const Args &...args)
template<uint32_t Poly>
uint32_t	crc32 (const uint8_t *data, uint32_t crc, std::size_t size)
	Evaluate the CRC32 of the first size bytes of a data buffer, using a specific polynomium and an initial value.
void	setDebugFlag (const char *string)
void	clearDebugFlag (const char *string)
void	dumpDebugFlags (std::ostream &os)
void	setFpRound (RoundingMode rm)
RoundingMode	getFpRound ()
uint64_t	procInfo (const char *filename, const char *target)
uint64_t	memUsage ()
	Determine the simulator process' total virtual memory usage.
std::unique_ptr< ImgWriter >	createImgWriter (enums::ImageFormat type, const FrameBuffer *fb)
	Factory Function which allocates a ImgWriter object and returns a smart pointer to it.
template<class T >
static constexpr std::enable_if_t< std::is_integral_v< T >, int >	floorLog2 (T x)
template<class T >
static constexpr int	ceilLog2 (const T &n)
template<class T >
static constexpr bool	isPowerOf2 (const T &n)
template<class T , class U >
static constexpr T	divCeil (const T &a, const U &b)
template<typename T >
static constexpr std::enable_if_t< sizeof(T)==sizeof(uint64_t)>	mulUnsigned (std::make_unsigned_t< T > &high, std::make_unsigned_t< T > &low, std::make_unsigned_t< T > val_a, std::make_unsigned_t< T > val_b)
template<typename T >
static constexpr std::enable_if_t< sizeof(T)==sizeof(uint64_t)>	mulSignedManual (std::make_signed_t< T > &high, std::make_signed_t< T > &low, std::make_signed_t< T > val_a, std::make_signed_t< T > val_b)
template<typename T >
static constexpr std::enable_if_t< sizeof(T)==sizeof(uint64_t)>	mulSigned (std::make_signed_t< T > &high, std::make_signed_t< T > &low, std::make_signed_t< T > val_a, std::make_signed_t< T > val_b)
template<typename T >
static constexpr std::pair< std::make_unsigned_t< T >, std::make_unsigned_t< T > >	mulUnsigned (std::make_unsigned_t< T > val_a, std::make_unsigned_t< T > val_b)
template<typename T >
static constexpr std::pair< std::make_signed_t< T >, std::make_signed_t< T > >	mulSigned (std::make_signed_t< T > val_a, std::make_signed_t< T > val_b)
template<class T , class U >
static constexpr T	roundUp (const T &val, const U &align)
	This function is used to align addresses in memory.
template<class T , class U >
static constexpr T	roundDown (const T &val, const U &align)
	This function is used to align addresses in memory.
static constexpr int	log2i (int value)
	Calculate the log2 of a power of 2 integer.
bool	operator== (const Pixel &lhs, const Pixel &rhs)
bool	to_number (const std::string &value, Pixel &retval)
std::ostream &	operator<< (std::ostream &os, const Pixel &pxl)
static void	writePng (png_structp pngPtr, png_bytep data, png_size_t length)
	Write callback to use with libpng APIs.
template<class ArgT >
static int	fcntlHelper (int fd, int cmd, ArgT arg)
static int	fcntlHelper (int fd, int cmd)
template<class T >
bool	operator== (const RefCountingPtr< T > &l, const RefCountingPtr< T > &r)
	Check for equality of two reference counting pointers.
template<class T >
bool	operator== (const RefCountingPtr< T > &l, const T *r)
	Check for equality of of a reference counting pointers and a regular pointer.
template<class T >
bool	operator== (const T *l, const RefCountingPtr< T > &r)
	Check for equality of of a reference counting pointers and a regular pointer.
template<class T >
bool	operator!= (const RefCountingPtr< T > &l, const RefCountingPtr< T > &r)
	Check for inequality of two reference counting pointers.
template<class T >
bool	operator!= (const RefCountingPtr< T > &l, const T *r)
	Check for inequality of of a reference counting pointers and a regular pointer.
template<class T >
bool	operator!= (const T *l, const RefCountingPtr< T > &r)
	Check for inequality of of a reference counting pointers and a regular pointer.
ListenSocketConfig	listenSocketInetConfig (int port)
ListenSocketConfig	listenSocketUnixFileConfig (std::string dir, std::string fname)
ListenSocketConfig	listenSocketUnixAbstractConfig (std::string path)
static std::ostream &	operator<< (std::ostream &os, const ListenSocket &socket)
static ListenSocketConfig	listenSocketEmptyConfig ()
void	debugDumpStats ()
template<typename T >
bool	emptyStrings (const T &labels)
	Check if all strings in a container are empty.
bool	split_first (const std::string &s, std::string &lhs, std::string &rhs, char c)
bool	split_last (const std::string &s, std::string &lhs, std::string &rhs, char c)
void	tokenize (std::vector< std::string > &v, const std::string &s, char token, bool ignore)
void	eat_lead_white (std::string &s)
void	eat_end_white (std::string &s)
void	eat_white (std::string &s)
std::string	to_lower (const std::string &s)
template<class T >
std::enable_if_t<(std::is_integral_v< T >||std::is_floating_point_v< T >||std::is_enum_v< T >) &&!std::is_same_v< bool, T >, bool >	to_number (const std::string &value, T &retval)
	Turn a string representation of a number, either integral, floating point, or enum into an actual number.
bool	to_bool (const std::string &value, bool &retval)
	Turn a string representation of a boolean into a boolean value.
std::string	quote (const std::string &s)
bool	startswith (const char *s, const char *prefix)
	Return true if 's' starts with the prefix string 'prefix'.
bool	startswith (const std::string &s, const char *prefix)
	Return true if 's' starts with the prefix string 'prefix'.
bool	startswith (const std::string &s, const std::string &prefix)
	Return true if 's' starts with the prefix string 'prefix'.
std::string	replace (const std::string &s, char from, char to)
std::ostream &	operator<< (std::ostream &out, const Temperature &temp)
constexpr Temperature	operator* (const Temperature &lhs, const double &rhs)
constexpr Temperature	operator* (const double &lhs, const Temperature &rhs)
constexpr Temperature	operator/ (const Temperature &lhs, const double &rhs)
void	sleep (const Time &time)
time_t	mkutctime (struct tm *time)
bool	operator== (const Time &l, const Time &r)
bool	operator!= (const Time &l, const Time &r)
bool	operator< (const Time &l, const Time &r)
bool	operator<= (const Time &l, const Time &r)
bool	operator> (const Time &l, const Time &r)
bool	operator>= (const Time &l, const Time &r)
Time	operator+ (const Time &l, const Time &r)
Time	operator- (const Time &l, const Time &r)
std::ostream &	operator<< (std::ostream &out, const Time &time)
std::ostream &	operator<< (std::ostream &out, const Cycles &cycles)
static MicroPC	romMicroPC (MicroPC upc)
static MicroPC	normalMicroPC (MicroPC upc)
static bool	isRomMicroPC (MicroPC upc)
static uint32_t	floatToBits32 (float val)
static uint64_t	floatToBits64 (double val)
static uint64_t	floatToBits (double val)
static uint32_t	floatToBits (float val)
static float	bitsToFloat32 (uint32_t val)
static double	bitsToFloat64 (uint64_t val)
static double	bitsToFloat (uint64_t val)
static float	bitsToFloat (uint32_t val)
static void	onKickSignal (int signo, siginfo_t *si, void *data)
	Dummy handler for KVM kick signals.
static pid_t	sysGettid ()
static constexpr auto	genTagExtractor (BTBIndexingPolicy *ip)
	This helper generates a tag extractor function object which will be typically used by Replaceable entries indexed with the BaseIndexingPolicy.
constexpr RegClass	invalidRegClass (InvalidRegClass, "invalid", 0, debug::InvalidReg)
std::ostream &	operator<< (std::ostream &os, const RegId &rid)
void	change_thread_state (ThreadID tid, int activate, int priority)
	Changes the status and priority of the thread with the given number.
std::ostream &	operator<< (std::ostream &out, const Check &obj)
std::ostream &	operator<< (std::ostream &out, const CheckTable &obj)
std::ostream &	operator<< (std::ostream &out, const RubyTester &obj)
void	pybind_init_tracers (py::module_ &m_native)
void	takeOverFrom (ThreadContext &new_tc, ThreadContext &old_tc)
	Copy state between thread contexts in preparation for CPU handover.
Addr	addrBlockOffset (Addr addr, Addr block_size)
	Calculates the offset of a given address wrt aligned fixed-size blocks.
Addr	addrBlockAlign (Addr addr, Addr block_size)
	Returns the address of the closest aligned fixed-size block to the given address.
bool	transferNeedsBurst (Addr addr, unsigned int size, unsigned int block_size)
	Returns true if the given memory access (address, size) needs to be fragmented across aligned fixed-size blocks.
bool	isAnyActiveElement (const std::vector< bool >::const_iterator &it_start, const std::vector< bool >::const_iterator &it_end)
	Test if there is any active element in an enablement range.
	BitUnion32 (IDR0) Bitfield< 0 > s2p
	EndBitUnion (IDR0) BitUnion32(IRQCtrl) Bitfield< 0 > gerrorIrqEn
	EndBitUnion (IRQCtrl) union SMMURegs
static uint8_t	bcdize (uint8_t val)
static uint8_t	unbcdize (uint8_t val)
static int	SPDSTS_POLARITY (int lnksts)
void	SafeRead (std::ifstream &stream, void *data, int count)
template<class T >
void	SafeRead (std::ifstream &stream, T &data)
template<class T >
void	SafeReadSwap (std::ifstream &stream, T &data)
void	SafeWrite (std::ofstream &stream, const void *data, int count)
template<class T >
void	SafeWrite (std::ofstream &stream, const T &data)
template<class T >
void	SafeWriteSwap (std::ofstream &stream, const T &data)
template<typename T >
T	p9toh (T v)
	Convert p9 byte order (LE) to host byte order.
template<typename T >
T	htop9 (T v)
	Convert host byte order to p9 byte order (LE)
template<>
P9MsgHeader	p9toh (P9MsgHeader v)
template<>
P9MsgHeader	htop9 (P9MsgHeader v)
static void	replaceUpgrade (PacketPtr pkt)
void	printSize (std::ostream &stream, size_t size)
static constexpr auto	genTagExtractor (BaseIndexingPolicy *ip)
	This helper generates an a tag extractor function object which will be typically used by Replaceable entries indexed with the BaseIndexingPolicy.
static constexpr auto	genTagExtractor (TaggedIndexingPolicy *ip)
	This helper generates an a tag extractor function object which will be typically used by Replaceable entries indexed with the TaggedIndexingPolicy.
std::string	htmFailureToStr (HtmFailureFaultCause cause)
	Convert enum into string to be used for debug purposes.
std::string	htmFailureToStr (HtmCacheFailure rc)
	Convert enum into string to be used for debug purposes.
std::ostream &	operator<< (std::ostream &os, const TranslationGen::Range &range)
static void	init_drain (py::module_ &m_native)
static void	init_serialize (py::module_ &m_native)
static void	init_range (py::module_ &m_native)
static void	init_pc (py::module_ &m_native)
static void	init_net (py::module_ &m_native)
static void	init_loader (py::module_ &m_native)
static void	init_socket (py::module_ &m_native)
void	pybind_init_core (py::module_ &m_native)
static void	output (const char *filename)
static void	activate (const char *expr)
static void	ignore (const char *expr)
void	pybind_init_debug (py::module_ &m_native)
void	pybind_init_event (py::module_ &m_native)
void	pybind_init_core (pybind11::module_ &m_native)
void	pybind_init_debug (pybind11::module_ &m_native)
void	pybind_init_event (pybind11::module_ &m_native)
void	pybind_init_stats (pybind11::module_ &m_native)
static const py::object	cast_stat_info (const statistics::Info *info)
void	pybind_init_stats (py::module_ &m_native)
void	print_backtrace ()
	Print a gem5 post-mortem report.
std::pair< std::uint64_t, bool >	getUintX (const void *buf, std::size_t bytes, ByteOrder endian)
bool	setUintX (std::uint64_t val, void *buf, std::size_t bytes, ByteOrder endian)
std::pair< std::string, bool >	printUintX (const void *buf, std::size_t bytes, ByteOrder endian)
std::string	printByteBuf (const void *buf, std::size_t bytes, ByteOrder endian, std::size_t chunk_size)
uint64_t	swap_byte64 (uint64_t x)
uint32_t	swap_byte32 (uint32_t x)
uint16_t	swap_byte16 (uint16_t x)
template<typename T >
std::enable_if_t< sizeof(T)==8 &&std::is_convertible_v< T, uint64_t >, T >	swap_byte (T x)
template<typename T >
std::enable_if_t< sizeof(T)==4 &&std::is_convertible_v< T, uint32_t >, T >	swap_byte (T x)
template<typename T >
std::enable_if_t< sizeof(T)==2 &&std::is_convertible_v< T, uint16_t >, T >	swap_byte (T x)
template<typename T >
std::enable_if_t< sizeof(T)==1 &&std::is_convertible_v< T, uint8_t >, T >	swap_byte (T x)
template<typename T , size_t N>
std::array< T, N >	swap_byte (std::array< T, N > a)
template<typename T >
T	betole (T value)
template<typename T >
T	letobe (T value)
template<typename T >
T	htole (T value)
template<typename T >
T	letoh (T value)
template<typename T >
T	htobe (T value)
template<typename T >
T	betoh (T value)
template<typename T >
T	htog (T value, ByteOrder guest_byte_order)
template<typename T >
T	gtoh (T value, ByteOrder guest_byte_order)
void	fixClockFrequency ()
bool	clockFrequencyFixed ()
void	setClockFrequency (Tick tps)
Tick	getClockFrequency ()
void	setOutputDir (const std::string &dir)
CallbackQueue &	exitCallbacks ()
	Queue of C++ callbacks to invoke on simulator exit.
void	registerExitCallback (const std::function< void()> &callback)
	Register an exit callback.
void	doExitCleanup ()
	Do C++ simulator exit processing.
Tick	curTick ()
	The universal simulation clock.
std::map< std::string, CxxConfigDirectoryEntry * > &	cxxConfigDirectory ()
	Directory of all SimObject classes config details.
static std::string	formatParamList (const std::vector< std::string > &param_values)
void	schedBreak (Tick when)
	Cause the simulator to execute a breakpoint.
void	schedRelBreak (Tick delta)
	Cause the simulator to execute a breakpoint relative to the current tick.
void	takeCheckpoint (Tick when)
	Function to cause the simulator to take a checkpoint from the debugger.
void	eventqDump ()
	Dump all the events currently on the event queue.
EventQueue *	getEventQueue (uint32_t index)
	Function for returning eventq queue for the provided index.
void	dumpMainQueue ()
EventQueue *	curEventQueue ()
void	curEventQueue (EventQueue *q)
bool	operator< (const Event &l, const Event &r)
bool	operator> (const Event &l, const Event &r)
bool	operator<= (const Event &l, const Event &r)
bool	operator>= (const Event &l, const Event &r)
bool	operator== (const Event &l, const Event &r)
bool	operator!= (const Event &l, const Event &r)
template<typename ABI , bool store_ret, typename Ret , typename ... Args>
Ret	invokeSimcall (ThreadContext *tc, std::function< Ret(ThreadContext *, Args...)> target)
template<typename ABI , typename Ret , typename ... Args>
Ret	invokeSimcall (ThreadContext *tc, std::function< Ret(ThreadContext *, Args...)> target)
template<typename ABI , bool store_ret, typename Ret , typename ... Args>
Ret	invokeSimcall (ThreadContext *tc, Ret(*target)(ThreadContext *, Args...))
template<typename ABI , typename Ret , typename ... Args>
Ret	invokeSimcall (ThreadContext *tc, Ret(*target)(ThreadContext *, Args...))
template<typename ABI , typename ... Args>
void	invokeSimcall (ThreadContext *tc, std::function< void(ThreadContext *, Args...)> target)
template<typename ABI , typename ... Args>
void	invokeSimcall (ThreadContext *tc, void(*target)(ThreadContext *, Args...))
template<typename ABI , typename Ret , typename ... Args>
std::string	dumpSimcall (std::string name, ThreadContext *tc, std::function< Ret(ThreadContext *, Args...)> target=std::function< Ret(ThreadContext *, Args...)>())
template<typename ABI , typename Ret , typename ... Args>
std::string	dumpSimcall (std::string name, ThreadContext *tc, Ret(*target)(ThreadContext *, Args...))
static bool	setupAltStack ()
static void	installSignalHandler (int signal, void(*handler)(int sigtype), int flags=SA_RESTART, struct sigaction *old_sa=NULL)
static void	raiseFatalSignal (int signo)
void	dumpStatsHandler (int sigtype)
	Stats signal handler.
void	dumprstStatsHandler (int sigtype)
void	exitNowHandler (int sigtype)
	Exit signal handler.
void	abortHandler (int sigtype)
	Abort signal handler.
static void	segvHandler (int sigtype)
	Segmentation fault signal handler.
static void	ioHandler (int sigtype)
void	initSignals ()
void	initSigInt ()
void	restoreSigInt ()
static std::ostream &	operator<< (std::ostream &os, const Port &port)
static std::string	normalize (const std::string &directory)
template<class AddrType >
void	copyStringArray (std::vector< std::string > &strings, AddrType array_ptr, AddrType data_ptr, const ByteOrder bo, PortProxy &memProxy)
template<typename T , typename Proxy , typename A >
std::enable_if_t< std::is_integral_v< A >, ConstProxyPtr< T, Proxy > >	operator+ (A a, const ConstProxyPtr< T, Proxy > &other)
template<typename T , typename Proxy , typename A >
std::enable_if_t< std::is_integral_v< A >, ProxyPtr< T, Proxy > >	operator+ (A a, const ProxyPtr< T, Proxy > &other)
template<typename T , typename Proxy >
std::ostream &	operator<< (std::ostream &os, const ConstProxyPtr< T, Proxy > &vptr)
void	py_interact ()
static std::string	normalizePath (std::string path)
template<class T >
void	paramOut (CheckpointOut &os, const std::string &name, const T &param)
	This function is used for writing parameters to a checkpoint.
template<class T >
bool	paramInImpl (CheckpointIn &cp, const std::string &name, T &param)
template<class T >
bool	optParamIn (CheckpointIn &cp, const std::string &name, T &param, bool do_warn=true)
	This function is used for restoring optional parameters from the checkpoint.
template<class T >
void	paramIn (CheckpointIn &cp, const std::string &name, T &param)
	This function is used for restoring parameters from a checkpoint.
template<class InputIterator >
void	arrayParamOut (CheckpointOut &os, const std::string &name, InputIterator start, InputIterator end)
template<class T >
void	arrayParamOut (CheckpointOut &os, const std::string &name, const T *param, unsigned size)
template<class T , class InsertIterator >
void	arrayParamIn (CheckpointIn &cp, const std::string &name, InsertIterator inserter, ssize_t fixed_size=-1)
	Extract values stored in the checkpoint, and assign them to the provided array container.
template<class T >
decltype(std::declval< T >().insert(std::declval< typename T::value_type >()), void())	arrayParamIn (CheckpointIn &cp, const std::string &name, T &param)
template<class T >
decltype(std::declval< T >().push_back(std::declval< typename T::value_type >()), void())	arrayParamIn (CheckpointIn &cp, const std::string &name, T &param)
template<class T >
void	arrayParamIn (CheckpointIn &cp, const std::string &name, T *param, unsigned size)
template<class T >
void	mappingParamOut (CheckpointOut &os, const char *sectionName, const char *const names[], const T *param, unsigned size)
	Serialize a mapping represented as two arrays: one containing names and the other containing values.
template<class T >
void	mappingParamIn (CheckpointIn &cp, const char *sectionName, const char *const names[], T *param, unsigned size)
	Restore mappingParamOut.
void	exitSimLoop (const std::string &message, int exit_code=0, Tick when=curTick(), Tick repeat=0, bool serialize=false)
	Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (curTick()).
void	exitSimLoopNow (const std::string &message, int exit_code=0, Tick repeat=0, bool serialize=false)
	Schedule an event as above, but make it high priority so it runs before any normal events which are schedule at the current time.
void	objParamIn (CheckpointIn &cp, const std::string &name, SimObject *&param)
	To avoid circular dependencies the unserialization of SimObjects must be implemented here.
void	debug_serialize (const std::string &cpt_dir)
Event *	doSimLoop (EventQueue *)
	forward declaration
GlobalSimLoopExitEvent *	simulate (Tick num_cycles)
void	set_max_tick (Tick tick)
	Set the maximum tick.
Tick	get_max_tick ()
	Get the maximum simulation tick.
void	terminateEventQueueThreads ()
	Terminate helper threads when running in parallel mode.
SyscallReturn	unimplementedFunc (SyscallDesc *desc, ThreadContext *tc)
	Handler for unimplemented syscalls that we haven't thought about.
void	warnUnsupportedOS (std::string syscall_name)
SyscallReturn	ignoreFunc (SyscallDesc *desc, ThreadContext *tc)
	Handler for unimplemented syscalls that we never intend to implement (signal handling, etc.) and should not affect the correct behavior of the program.
SyscallReturn	ignoreWarnOnceFunc (SyscallDesc *desc, ThreadContext *tc)
	Like above, but only prints a warning once per syscall desc it's used with.
static void	exitFutexWake (ThreadContext *tc, VPtr<> addr, uint64_t tgid)
static SyscallReturn	exitImpl (SyscallDesc *desc, ThreadContext *tc, bool group, int status)
SyscallReturn	exitFunc (SyscallDesc *desc, ThreadContext *tc, int status)
	Target exit() handler: terminate current context.
SyscallReturn	exitGroupFunc (SyscallDesc *desc, ThreadContext *tc, int status)
	Target exit_group() handler: terminate simulation. (exit all threads)
SyscallReturn	getpagesizeFunc (SyscallDesc *desc, ThreadContext *tc)
	Target getpagesize() handler.
SyscallReturn	brkFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> new_brk)
	Target brk() handler: set brk address.
SyscallReturn	setTidAddressFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> tidPtr)
	Target set_tid_address() handler.
SyscallReturn	closeFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd)
	Target close() handler.
SyscallReturn	_llseekFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, uint32_t offset_high, uint32_t offset_low, VPtr<> result_ptr, int whence)
	Target _llseek() handler.
SyscallReturn	gethostnameFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> buf_ptr, int name_len)
	Target gethostname() handler.
SyscallReturn	unlinkFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname)
	Target unlink() handler.
SyscallReturn	unlinkImpl (SyscallDesc *desc, ThreadContext *tc, std::string path)
SyscallReturn	linkFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr<> new_pathname)
	Target link() handler.
SyscallReturn	symlinkFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr<> new_pathname)
	Target symlink() handler.
SyscallReturn	mkdirFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, mode_t mode)
	Target mkdir() handler.
SyscallReturn	mkdirImpl (SyscallDesc *desc, ThreadContext *tc, std::string path, mode_t mode)
SyscallReturn	renameFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> oldpath, VPtr<> newpath)
	Target rename() handler.
SyscallReturn	renameImpl (SyscallDesc *desc, ThreadContext *tc, std::string old_name, std::string new_name)
SyscallReturn	truncate64Func (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, int64_t length)
	Target truncate64() handler.
SyscallReturn	ftruncate64Func (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, int64_t length)
	Target ftruncate64() handler.
SyscallReturn	umaskFunc (SyscallDesc *desc, ThreadContext *tc)
	Target umask() handler.
SyscallReturn	chownFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, uint32_t owner, uint32_t group)
	Target chown() handler.
SyscallReturn	chownImpl (SyscallDesc *desc, ThreadContext *tc, std::string path, uint32_t owner, uint32_t group)
SyscallReturn	fchownFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, uint32_t owner, uint32_t group)
	Target fchown() handler.
SyscallReturn	dupFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd)
	FIXME: The file description is not shared among file descriptors created with dup.
SyscallReturn	dup2Func (SyscallDesc *desc, ThreadContext *tc, int old_tgt_fd, int new_tgt_fd)
	Target dup2() handler.
SyscallReturn	fcntlFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, int cmd, guest_abi::VarArgs< int > varargs)
	Target fcntl() handler.
SyscallReturn	fcntl64Func (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, int cmd)
	Target fcntl64() handler.
SyscallReturn	pipePseudoFunc (SyscallDesc *desc, ThreadContext *tc)
	Pseudo Funcs - These functions use a different return convension, returning a second value in a register other than the normal return register.
SyscallReturn	pipeFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> tgt_addr)
	Target pipe() handler.
SyscallReturn	pipe2Func (SyscallDesc *desc, ThreadContext *tc, VPtr<> tgt_addr, int flags)
	Target pipe() handler.
SyscallReturn	getpgrpFunc (SyscallDesc *desc, ThreadContext *tc)
	Target getpgrpFunc() handler.
SyscallReturn	setpgidFunc (SyscallDesc *desc, ThreadContext *tc, int pid, int pgid)
	Target setpgid() handler.
SyscallReturn	getpidFunc (SyscallDesc *desc, ThreadContext *tc)
	Target getpid() handler.
SyscallReturn	gettidFunc (SyscallDesc *desc, ThreadContext *tc)
	Target gettid() handler.
SyscallReturn	getppidFunc (SyscallDesc *desc, ThreadContext *tc)
	Target getppid() handler.
SyscallReturn	getuidFunc (SyscallDesc *desc, ThreadContext *tc)
SyscallReturn	geteuidFunc (SyscallDesc *desc, ThreadContext *tc)
	Target geteuid() handler.
SyscallReturn	getgidFunc (SyscallDesc *desc, ThreadContext *tc)
	Target getgid() handler.
SyscallReturn	getegidFunc (SyscallDesc *desc, ThreadContext *tc)
	Target getegid() handler.
SyscallReturn	accessFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, mode_t mode)
	Target access() handler.
SyscallReturn	accessImpl (SyscallDesc *desc, ThreadContext *tc, std::string path, mode_t mode)
SyscallReturn	mknodFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, mode_t mode, dev_t dev)
	Target mknod() handler.
SyscallReturn	mknodImpl (SyscallDesc *desc, ThreadContext *tc, std::string path, mode_t mode, dev_t dev)
SyscallReturn	chdirFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname)
	Target chdir() handler.
SyscallReturn	rmdirFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname)
SyscallReturn	rmdirImpl (SyscallDesc *desc, ThreadContext *tc, std::string path)
SyscallReturn	shutdownFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, int how)
	Target shutdown() handler.
SyscallReturn	bindFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> buf_ptr, int addrlen)
SyscallReturn	listenFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, int backlog)
SyscallReturn	connectFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> buf_ptr, int addrlen)
SyscallReturn	recvmsgFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> msgPtr, int flags)
SyscallReturn	sendmsgFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> msgPtr, int flags)
SyscallReturn	getsockoptFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, int level, int optname, VPtr<> valPtr, VPtr<> lenPtr)
SyscallReturn	getsocknameFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> addrPtr, VPtr<> lenPtr)
SyscallReturn	getpeernameFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> sockAddrPtr, VPtr<> addrlenPtr)
SyscallReturn	setsockoptFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, int level, int optname, VPtr<> valPtr, socklen_t len)
SyscallReturn	getcpuFunc (SyscallDesc *desc, ThreadContext *tc, VPtr< uint32_t > cpu, VPtr< uint32_t > node, VPtr< uint32_t > tcache)
template<class OS >
SyscallReturn	atSyscallPath (ThreadContext *tc, int dirfd, std::string &path)
template<class OS >
SyscallReturn	futexFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> uaddr, int op, int val, int timeout, VPtr<> uaddr2, int val3)
	Futex system call Implemented by Daniel Sanchez Used by printf's in multi-threaded apps.
template<class T1 , class T2 >
void	getElapsedTimeMicro (T1 &sec, T2 &usec)
	Helper function to convert current elapsed time to seconds and microseconds.
template<class T1 , class T2 >
void	getElapsedTimeNano (T1 &sec, T2 &nsec)
	Helper function to convert current elapsed time to seconds and nanoseconds.
template<typename OS , typename TgtStatPtr , typename HostStatPtr >
void	copyOutStatBuf (TgtStatPtr tgt, HostStatPtr host, bool fakeTTY=false)
template<typename OS , typename TgtStatPtr , typename HostStatPtr >
void	copyOutStat64Buf (TgtStatPtr tgt, HostStatPtr host, bool fakeTTY=false)
template<class OS , typename TgtStatPtr , typename HostStatPtr >
void	copyOutStatfsBuf (TgtStatPtr tgt, HostStatPtr host)
template<typename OS , typename TgtStatPtr , typename HostStatPtr >
void	copyOutStatxBuf (TgtStatPtr tgt, HostStatPtr host, bool fakeTTY=false)
template<class OS >
SyscallReturn	ioctlFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, unsigned req, VPtr<> addr)
	Target ioctl() handler.
template<class OS >
SyscallReturn	openatFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_dirfd, VPtr<> pathname, int tgt_flags, int mode)
	Target open() handler.
template<class OS >
SyscallReturn	openFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, int tgt_flags, int mode)
	Target open() handler.
template<class OS >
SyscallReturn	getcwdFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> buf_ptr, typename OS::size_t size)
	Target getcwd() handler.
template<class OS >
SyscallReturn	lseekFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, typename OS::off_t offs, int whence)
	Target lseek() handler.
template<class OS >
SyscallReturn	unlinkatFunc (SyscallDesc *desc, ThreadContext *tc, int dirfd, VPtr<> pathname, int flags)
	Target unlinkat() handler.
template<class OS >
SyscallReturn	faccessatFunc (SyscallDesc *desc, ThreadContext *tc, int dirfd, VPtr<> pathname, int mode)
	Target facessat() handler.
template<class OS >
SyscallReturn	readlinkatFunc (SyscallDesc *desc, ThreadContext *tc, int dirfd, VPtr<> pathname, VPtr<> buf_ptr, typename OS::size_t bufsiz)
	Target readlinkat() handler.
template<class OS >
SyscallReturn	readlinkFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr<> buf_ptr, typename OS::size_t bufsiz)
	Target readlink() handler.
template<class OS >
SyscallReturn	renameatFunc (SyscallDesc *desc, ThreadContext *tc, int olddirfd, VPtr<> oldpath, int newdirfd, VPtr<> newpath)
	Target renameat() handler.
template<class OS >
SyscallReturn	fchownatFunc (SyscallDesc *desc, ThreadContext *tc, int dirfd, VPtr<> pathname, uint32_t owner, uint32_t group, int flags)
	Target fchownat() handler.
template<class OS >
SyscallReturn	mkdiratFunc (SyscallDesc *desc, ThreadContext *tc, int dirfd, VPtr<> pathname, mode_t mode)
	Target mkdirat() handler.
template<class OS >
SyscallReturn	mknodatFunc (SyscallDesc *desc, ThreadContext *tc, int dirfd, VPtr<> pathname, mode_t mode, dev_t dev)
	Target mknodat() handler.
template<class OS >
SyscallReturn	sysinfoFunc (SyscallDesc *desc, ThreadContext *tc, VPtr< typename OS::tgt_sysinfo > sysinfo)
	Target sysinfo() handler.
template<class OS >
SyscallReturn	fchmodatFunc (SyscallDesc *desc, ThreadContext *tc, int dirfd, VPtr<> pathname, mode_t mode)
	Target chmod() handler.
template<class OS >
SyscallReturn	chmodFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, mode_t mode)
	Target chmod() handler.
template<class OS >
SyscallReturn	pollFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> fdsPtr, int nfds, int tmout)
template<class OS >
SyscallReturn	fchmodFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, uint32_t mode)
	Target fchmod() handler.
template<class OS >
SyscallReturn	mremapFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> start, typename OS::size_t old_length, typename OS::size_t new_length, int flags, guest_abi::VarArgs< uint64_t > varargs)
	Target mremap() handler.
template<class OS >
SyscallReturn	statFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr< typename OS::tgt_stat > tgt_stat)
	Target stat() handler.
template<class OS >
SyscallReturn	newfstatatFunc (SyscallDesc *desc, ThreadContext *tc, int dirfd, VPtr<> pathname, VPtr< typename OS::tgt_stat64 > tgt_stat, int flags)
	Target newfstatat() handler.
template<class OS >
SyscallReturn	fstatat64Func (SyscallDesc *desc, ThreadContext *tc, int dirfd, VPtr<> pathname, VPtr< typename OS::tgt_stat64 > tgt_stat)
	Target fstatat64() handler.
template<class OS >
SyscallReturn	stat64Func (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr< typename OS::tgt_stat64 > tgt_stat)
	Target stat64() handler.
template<class OS >
SyscallReturn	statxFunc (SyscallDesc *desc, ThreadContext *tc, int dirfd, VPtr<> pathname, int flags, unsigned int mask, VPtr< typename OS::tgt_statx > tgt_statx)
	Target statx() handler.
template<class OS >
SyscallReturn	fstat64Func (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr< typename OS::tgt_stat64 > tgt_stat)
	Target fstat64() handler.
template<class OS >
SyscallReturn	lstatFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr< typename OS::tgt_stat > tgt_stat)
	Target lstat() handler.
template<class OS >
SyscallReturn	lstat64Func (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr< typename OS::tgt_stat64 > tgt_stat)
	Target lstat64() handler.
template<class OS >
SyscallReturn	fstatFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr< typename OS::tgt_stat > tgt_stat)
	Target fstat() handler.
template<class OS >
SyscallReturn	statfsFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr< typename OS::tgt_statfs > tgt_stat)
	Target statfs() handler.
template<class OS >
SyscallReturn	doClone (SyscallDesc *desc, ThreadContext *tc, RegVal flags, RegVal newStack, VPtr<> ptidPtr, VPtr<> ctidPtr, VPtr<> tlsPtr)
template<class OS >
SyscallReturn	clone3Func (SyscallDesc *desc, ThreadContext *tc, VPtr< typename OS::tgt_clone_args > cl_args, RegVal size)
template<class OS >
SyscallReturn	cloneFunc (SyscallDesc *desc, ThreadContext *tc, RegVal flags, RegVal newStack, VPtr<> ptidPtr, VPtr<> ctidPtr, VPtr<> tlsPtr)
template<class OS >
SyscallReturn	cloneBackwardsFunc (SyscallDesc *desc, ThreadContext *tc, RegVal flags, RegVal newStack, VPtr<> ptidPtr, VPtr<> tlsPtr, VPtr<> ctidPtr)
template<class OS >
SyscallReturn	fstatfsFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr< typename OS::tgt_statfs > tgt_stat)
	Target fstatfs() handler.
template<class OS >
SyscallReturn	readvFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> tiov_base, typename OS::size_t count)
	Target readv() handler.
template<class OS >
SyscallReturn	writevFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> tiov_base, typename OS::size_t count)
	Target writev() handler.
template<class OS >
SyscallReturn	mmapFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> start, typename OS::size_t length, int prot, int tgt_flags, int tgt_fd, typename OS::off_t offset)
	Target mmap() handler.
template<class OS >
SyscallReturn	pread64Func (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> bufPtr, typename OS::size_t nbytes, typename OS::off_t offset)
template<class OS >
SyscallReturn	pwrite64Func (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> bufPtr, typename OS::size_t nbytes, typename OS::off_t offset)
template<class OS >
SyscallReturn	mmap2Func (SyscallDesc *desc, ThreadContext *tc, VPtr<> start, typename OS::size_t length, int prot, int tgt_flags, int tgt_fd, typename OS::off_t offset)
	Target mmap2() handler.
template<class OS >
SyscallReturn	getrlimitFunc (SyscallDesc *desc, ThreadContext *tc, unsigned resource, VPtr< typename OS::rlimit > rlp)
	Target getrlimit() handler.
template<class OS >
SyscallReturn	prlimitFunc (SyscallDesc *desc, ThreadContext *tc, int pid, int resource, VPtr<> n, VPtr< typename OS::rlimit > rlp)
template<class OS >
SyscallReturn	clock_gettimeFunc (SyscallDesc *desc, ThreadContext *tc, int clk_id, VPtr< typename OS::timespec > tp)
	Target clock_gettime() function.
template<class OS >
SyscallReturn	clock_getresFunc (SyscallDesc *desc, ThreadContext *tc, int clk_id, VPtr< typename OS::timespec > tp)
	Target clock_getres() function.
template<class OS >
SyscallReturn	gettimeofdayFunc (SyscallDesc *desc, ThreadContext *tc, VPtr< typename OS::timeval > tp, VPtr<> tz_ptr)
	Target gettimeofday() handler.
template<class OS >
SyscallReturn	futimesatFunc (SyscallDesc *desc, ThreadContext *tc, int dirfd, VPtr<> pathname, VPtr< typename OS::timeval[2]> tp)
	Target futimesat() handler.
template<class OS >
SyscallReturn	utimesFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr< typename OS::timeval[2]> tp)
	Target utimes() handler.
template<class OS >
SyscallReturn	execveFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr<> argv_mem_loc, VPtr<> envp_mem_loc)
template<class OS >
SyscallReturn	getrusageFunc (SyscallDesc *desc, ThreadContext *tc, int who, VPtr< typename OS::rusage > rup)
	Target getrusage() function.
template<class OS >
SyscallReturn	timesFunc (SyscallDesc *desc, ThreadContext *tc, VPtr< typename OS::tms > bufp)
	Target times() function.
template<class OS >
SyscallReturn	timeFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> taddr)
	Target time() function.
template<class OS >
SyscallReturn	tgkillFunc (SyscallDesc *desc, ThreadContext *tc, int tgid, int tid, int sig)
template<class OS >
SyscallReturn	socketFunc (SyscallDesc *desc, ThreadContext *tc, int domain, int type, int prot)
template<class OS >
SyscallReturn	socketpairFunc (SyscallDesc *desc, ThreadContext *tc, int domain, int type, int prot, VPtr<> svPtr)
template<class OS >
SyscallReturn	selectFunc (SyscallDesc *desc, ThreadContext *tc, int nfds, VPtr< typename OS::fd_set > readfds, VPtr< typename OS::fd_set > writefds, VPtr< typename OS::fd_set > errorfds, VPtr< typename OS::timeval > timeout)
template<class OS >
SyscallReturn	readFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> buf_ptr, typename OS::size_t nbytes)
template<class OS >
SyscallReturn	writeFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> buf_ptr, typename OS::size_t nbytes)
template<class OS >
SyscallReturn	wait4Func (SyscallDesc *desc, ThreadContext *tc, pid_t pid, VPtr<> statPtr, int options, VPtr<> rusagePtr)
template<class OS >
SyscallReturn	acceptFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> addrPtr, VPtr<> lenPtr)
template<class OS >
SyscallReturn	eventfdFunc (SyscallDesc *desc, ThreadContext *tc, unsigned initval, int in_flags)
	Target eventfd() function.
template<class OS >
SyscallReturn	schedGetaffinityFunc (SyscallDesc *desc, ThreadContext *tc, pid_t pid, typename OS::size_t cpusetsize, VPtr<> cpu_set_mask)
	Target sched_getaffinity.
template<class OS >
SyscallReturn	recvfromFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> buf_ptr, typename OS::size_t buf_len, int flags, VPtr<> addr_ptr, VPtr<> addrlen_ptr)
template<typename OS >
SyscallReturn	sendtoFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> buf_ptr, typename OS::size_t buf_len, int flags, VPtr<> addr_ptr, socklen_t addr_len)
template<typename OS >
SyscallReturn	munmapFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> start, typename OS::size_t length)
	Target munmap() handler.
template<typename OS >
SyscallReturn	fallocateFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, int mode, typename OS::off_t offset, typename OS::off_t len)
template<typename OS >
SyscallReturn	truncateFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, typename OS::off_t length)
	Target truncate() handler.
template<typename OS >
SyscallReturn	ftruncateFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, typename OS::off_t length)
	Target ftruncate() handler.
template<typename OS >
SyscallReturn	getrandomFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> buf_ptr, typename OS::size_t count, unsigned int flags)
void	printSystems ()
static std::ostream &	operator<< (std::ostream &os, const DummyMatRegContainer &d)
static std::ostream &	operator<< (std::ostream &os, const DummyVecPredRegContainer &d)
static std::ostream &	operator<< (std::ostream &os, const DummyVecRegContainer &d)
String to number helper functions for signed and unsigned
integeral type, as well as enums and floating-point types.
template<class T >
std::enable_if_t< std::is_integral_v< T >, T >	__to_number (const std::string &value)
template<class T >
std::enable_if_t< std::is_enum_v< T >, T >	__to_number (const std::string &value)
template<class T >
std::enable_if_t< std::is_floating_point_v< T >, T >	__to_number (const std::string &value)
void	serialize (const ThreadContext &tc, CheckpointOut &cp)
	Thread context serialization helpers.
void	unserialize (ThreadContext &tc, CheckpointIn &cp)
VirtIO endian conversion helpers
VirtIO prior to version 1.0 (legacy versions) normally send values to the host in the guest systems native byte order. This is going to change in version 1.0 which mandates little endian. We currently only support the legacy version of VirtIO (the new and shiny standard is still in a draft state and not implemented by the kernel). Once we support the new standard, we should negotiate the VirtIO version with the guest and automatically use the right type of byte swapping.
template<typename T >
std::enable_if_t< std::is_same_v< T, vring_used_elem >, T >	swap_byte (T v)
template<typename T >
std::enable_if_t< std::is_same_v< T, vring_desc >, T >	swap_byte (T v)

Variables
static const int	ROW_SIZE = 16
static const int	NUM_BANKS = 4
static uint64_t	invariant_reg_vector []
static constexpr unsigned	NUM_XREGS = int_reg::NumArchRegs - 1
static constexpr unsigned	NUM_QREGS = NumVecV8ArchRegs
constexpr unsigned	MaxMatRegRowLenInBytes = 256
constexpr unsigned	MaxMatRegRows = 256
constexpr unsigned	MaxVecRegLenInBytes = 1ULL << 16
Bitfield< 1 >	sse
Bitfield< 2 >	avx
Bitfield< 4, 3 >	mpx
Bitfield< 7, 5 >	avx512
Bitfield< 8 >	pt
Bitfield< 9 >	pkru
Bitfield< 10 >	pasid
Bitfield< 12, 11 >	cet
Bitfield< 13 >	hdc
Bitfield< 14 >	uintr
Bitfield< 15 >	lbr
Bitfield< 16 >	hwp
Bitfield< 18, 17 >	amx
Bitfield< 63, 19 >	reserved
const uint8_t	reverseBitsLookUpTable []
	Lookup table used for High Speed bit reversing.
const char *	compileDate = __DATE__ " " __TIME__
static const int	roundOps []
thread_local GTestLogOutput	gtestLogOutput
	c2 = 31
	high = AB + c2
const uint8_t	image_file []
	This image file contains the text "This is a test image.\n" 31 times.
const uint8_t	image_file_gzipped []
	This is "image_file" compressed using GZip.
OutputDirectory	simout
PollQueue	pollQueue
static const char	GDBStart = '$'
static const char	GDBEnd = '#'
static const char	GDBGoodP = '+'
static const char	GDBBadP = '-'
template<typename T >
constexpr bool	is_iterable_v = is_iterable<T>::value
template<typename T >
constexpr bool	is_std_hash_enabled_v = is_std_hash_enabled<T>::value
const Tick	MaxTick = 0xffffffffffffffffULL
static const MicroPC	MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1)
const Addr	MaxAddr = (Addr)-1
const ThreadID	InvalidThreadID = (ThreadID)-1
const ContextID	InvalidContextID = (ContextID)-1
const PortID	InvalidPortID = (PortID)-1
constexpr decltype(nullptr)	NoFault = nullptr
const char *	gem5Version = "24.1.0.1"
int	maxThreadsPerCPU = 1
	The maximum number of active threads across all cpus.
static const uint64_t	MIN_HOST_CYCLES = 1000
	Minimum number of cycles that a host can spend in a KVM call (used to calculate the resolution of some timers).
StaticInstPtr	nopStaticInstPtr = new NopStaticInst
	Pointer to a statically allocated generic "nop" instruction object.
const StaticInstPtr	nullStaticInstPtr
	Statically allocated null StaticInstPtr.
static const OpClass	IntAluOp = enums::IntAlu
static const OpClass	IntMultOp = enums::IntMult
static const OpClass	IntDivOp = enums::IntDiv
static const OpClass	FloatAddOp = enums::FloatAdd
static const OpClass	FloatCmpOp = enums::FloatCmp
static const OpClass	FloatCvtOp = enums::FloatCvt
static const OpClass	FloatMultOp = enums::FloatMult
static const OpClass	FloatMultAccOp = enums::FloatMultAcc
static const OpClass	FloatDivOp = enums::FloatDiv
static const OpClass	FloatMiscOp = enums::FloatMisc
static const OpClass	FloatSqrtOp = enums::FloatSqrt
static const OpClass	SimdAddOp = enums::SimdAdd
static const OpClass	SimdAddAccOp = enums::SimdAddAcc
static const OpClass	SimdAluOp = enums::SimdAlu
static const OpClass	SimdCmpOp = enums::SimdCmp
static const OpClass	SimdCvtOp = enums::SimdCvt
static const OpClass	SimdMiscOp = enums::SimdMisc
static const OpClass	SimdMultOp = enums::SimdMult
static const OpClass	SimdMultAccOp = enums::SimdMultAcc
static const OpClass	SimdMatMultAccOp = enums::SimdMatMultAcc
static const OpClass	SimdShiftOp = enums::SimdShift
static const OpClass	SimdShiftAccOp = enums::SimdShiftAcc
static const OpClass	SimdDivOp = enums::SimdDiv
static const OpClass	SimdSqrtOp = enums::SimdSqrt
static const OpClass	SimdReduceAddOp = enums::SimdReduceAdd
static const OpClass	SimdReduceAluOp = enums::SimdReduceAlu
static const OpClass	SimdReduceCmpOp = enums::SimdReduceCmp
static const OpClass	SimdFloatAddOp = enums::SimdFloatAdd
static const OpClass	SimdFloatAluOp = enums::SimdFloatAlu
static const OpClass	SimdFloatCmpOp = enums::SimdFloatCmp
static const OpClass	SimdFloatCvtOp = enums::SimdFloatCvt
static const OpClass	SimdFloatDivOp = enums::SimdFloatDiv
static const OpClass	SimdFloatMiscOp = enums::SimdFloatMisc
static const OpClass	SimdFloatMultOp = enums::SimdFloatMult
static const OpClass	SimdFloatMultAccOp = enums::SimdFloatMultAcc
static const OpClass	SimdFloatMatMultAccOp = enums::SimdFloatMatMultAcc
static const OpClass	SimdFloatSqrtOp = enums::SimdFloatSqrt
static const OpClass	SimdFloatReduceCmpOp = enums::SimdFloatReduceCmp
static const OpClass	SimdFloatReduceAddOp = enums::SimdFloatReduceAdd
static const OpClass	SimdAesOp = enums::SimdAes
static const OpClass	SimdAesMixOp = enums::SimdAesMix
static const OpClass	SimdSha1HashOp = enums::SimdSha1Hash
static const OpClass	SimdSha1Hash2Op = enums::SimdSha1Hash2
static const OpClass	SimdSha256HashOp = enums::SimdSha256Hash
static const OpClass	SimdSha256Hash2Op = enums::SimdSha256Hash2
static const OpClass	SimdShaSigma2Op = enums::SimdShaSigma2
static const OpClass	SimdShaSigma3Op = enums::SimdShaSigma3
static const OpClass	SimdPredAluOp = enums::SimdPredAlu
static const OpClass	MatrixOp = enums::Matrix
static const OpClass	MatrixMovOp = enums::MatrixMov
static const OpClass	MatrixOPOp = enums::MatrixOP
static const OpClass	MemReadOp = enums::MemRead
static const OpClass	MemWriteOp = enums::MemWrite
static const OpClass	FloatMemReadOp = enums::FloatMemRead
static const OpClass	FloatMemWriteOp = enums::FloatMemWrite
static const OpClass	SimdUnitStrideLoadOp = enums::SimdUnitStrideLoad
static const OpClass	SimdUnitStrideStoreOp = enums::SimdUnitStrideStore
static const OpClass	SimdUnitStrideMaskLoadOp = enums::SimdUnitStrideMaskLoad
static const OpClass	SimdUnitStrideMaskStoreOp = enums::SimdUnitStrideMaskStore
static const OpClass	SimdStridedLoadOp = enums::SimdStridedLoad
static const OpClass	SimdStridedStoreOp = enums::SimdStridedStore
static const OpClass	SimdIndexedLoadOp = enums::SimdIndexedLoad
static const OpClass	SimdIndexedStoreOp = enums::SimdIndexedStore
static const OpClass	SimdUnitStrideFaultOnlyFirstLoadOp = enums::SimdUnitStrideFaultOnlyFirstLoad
static const OpClass	SimdWholeRegisterLoadOp = enums::SimdWholeRegisterLoad
static const OpClass	SimdWholeRegisterStoreOp = enums::SimdWholeRegisterStore
static const OpClass	IprAccessOp = enums::IprAccess
static const OpClass	InstPrefetchOp = enums::InstPrefetch
static const OpClass	SimdUnitStrideSegmentedLoadOp = enums::SimdUnitStrideSegmentedLoad
static const OpClass	SimdUnitStrideSegmentedStoreOp = enums::SimdUnitStrideSegmentedStore
static const OpClass	SimdExtOp = enums::SimdExt
static const OpClass	SimdFloatExtOp = enums::SimdFloatExt
static const OpClass	SimdConfigOp = enums::SimdConfig
static const OpClass	Num_OpClasses = enums::Num_OpClass
constexpr char	IntRegClassName [] = "integer"
constexpr char	FloatRegClassName [] = "floating_point"
constexpr char	VecRegClassName [] = "vector"
constexpr char	VecElemClassName [] = "vector_element"
constexpr char	VecPredRegClassName [] = "vector_predicate"
constexpr char	MatRegClassName [] = "matrix"
constexpr char	CCRegClassName [] = "condition_code"
constexpr char	MiscRegClassName [] = "miscellaneous"
int	TESTER_NETWORK =0
static unsigned int	TESTER_ALLOCATOR = 0
const int	CHECK_SIZE_BITS = 2
const int	CHECK_SIZE = (1 << CHECK_SIZE_BITS)
const int	CACHE_LINE_BITS = 6
static EmbeddedPyBind	_py_tracers ("trace", pybind_init_tracers)
static constexpr int	AMDGPU_VM_COUNT = 16
constexpr int	FRAMEBUFFER_BAR = 0
constexpr int	DOORBELL_BAR = 2
constexpr int	MMIO_BAR = 5
constexpr uint32_t	VGA_ROM_DEFAULT = 0xc0000
constexpr uint32_t	ROM_SIZE = 0x20000
static constexpr uint32_t	IH_OFFSET_SHIFT = 2
static constexpr uint32_t	GRBM_OFFSET_SHIFT = 2
static constexpr uint32_t	MMHUB_OFFSET_SHIFT = 2
constexpr uint32_t	INTR_COOKIE_SIZE = 32
	MSI-style interrupts.
constexpr unsigned int	SDMA_ATOMIC_ADD64 = 47
const uint64_t	AmbaVendor = 0xb105f00d00000000ULL
static const std::map< enums::NoMaliGpuType, nomali_gpu_type_t >	gpuTypeMap
Bitfield< 1 >	s1p
Bitfield< 3, 2 >	ttf
Bitfield< 4 >	cohacc
Bitfield< 5 >	btm
Bitfield< 7, 6 >	httu
Bitfield< 8 >	dormhint
Bitfield< 9 >	hyp
Bitfield< 10 >	ats
Bitfield< 11 >	ns1ats
Bitfield< 12 >	asid16
Bitfield< 13 >	msi
Bitfield< 14 >	sev
Bitfield< 15 >	atos
Bitfield< 16 >	pri
Bitfield< 17 >	vmw
Bitfield< 18 >	vmid16
Bitfield< 19 >	cd2l
Bitfield< 20 >	vatos
Bitfield< 22, 21 >	ttEndian
Bitfield< 23 >	atsRecErr
Bitfield< 25, 24 >	stallModel
Bitfield< 26 >	termModel
Bitfield< 28, 27 >	stLevel
Bitfield< 1 >	priqIrqEn
Bitfield< 2 >	eventqIrqEn
const char *	NsRxStateStrings []
const char *	NsTxStateStrings []
const char *	NsDmaState []
const uint16_t	FHASH_ADDR = 0x100
const uint16_t	FHASH_SIZE = 0x100
const uint8_t	EEPROM_READ = 0x2
const uint8_t	EEPROM_SIZE = 64
const uint8_t	EEPROM_PMATCH2_ADDR = 0xA
const uint8_t	EEPROM_PMATCH1_ADDR = 0xB
const uint8_t	EEPROM_PMATCH0_ADDR = 0xC
const int	RX_INT = 0x1
const int	TX_INT = 0x2
const uint8_t	UART_MCR_LOOP = 0x10
const int	MaxNiagaraProcs = 32
const Addr	IntManAddr = 0x0000
const Addr	IntManSize = 0x0020
const Addr	IntCtlAddr = 0x0400
const Addr	IntCtlSize = 0x0020
const Addr	JIntVecAddr = 0x0A00
const Addr	IntVecDisAddr = 0x0800
const Addr	IntVecDisSize = 0x0100
const Addr	JIntData0Addr = 0x0400
const Addr	JIntData1Addr = 0x0500
const Addr	JIntDataA0Addr = 0x0600
const Addr	JIntDataA1Addr = 0x0700
const Addr	JIntBusyAddr = 0x0900
const Addr	JIntBusySize = 0x0100
const Addr	JIntABusyAddr = 0x0B00
const uint64_t	IntManMask = 0x01F3F
const uint64_t	IntCtlMask = 0x00006
const uint64_t	JIntVecMask = 0x0003F
const uint64_t	IntVecDis = 0x31F3F
const uint64_t	JIntBusyMask = 0x0003F
static const P9MsgInfoMap	p9_msg_info
const uint8_t	RamSize = 32
const uint8_t	NumOutputBits = 14
static const int	LDS_SIZE = 65536
Fault	dummyFault1 = std::make_shared<gem5::FaultBase>()
Fault	dummyFault2 = std::make_shared<gem5::FaultBase>()
PybindSimObjectResolver	pybindSimObjectResolver
const ByteOrder	HostByteOrder = ByteOrder::big
Tick	simQuantum = 0
	Simulation Quantum for multiple eventq simulation.
uint32_t	numMainEventQueues = 0
	Current number of allocated main event queues.
std::vector< EventQueue * >	mainEventQueue
	Array for main event queues.
__thread EventQueue *	_curEventQueue = NULL
	The current event queue for the running thread.
bool	inParallelMode = false
	Current mode of execution: parallel / serial.
bool	FullSystem
	The FullSystem variable can be used to determine the current mode of simulation.
unsigned int	FullSystemInt
	In addition to the boolean flag we make use of an unsigned int since the CPU instruction decoder makes use of the variable in switch statements.
std::set< std::string >	version_tags
	The version tags for this build of the simulator, to be stored in the Globals section during serialization and compared upon unserialization.
struct sigaction	old_int_sa
Root::RootStats &	rootStats = Root::RootStats::instance
	Global simulator statistics that are not associated with a specific SimObject.
int	ckptMaxCount = 0
int	ckptCount = 0
int	ckptPrevCount = -1
template<class T >
decltype(std::begin(std::declval< const T & >()), std::end(std::declval< const T & >()), void())	arrayParamOut (CheckpointOut &os, const std::string &name, const T &param)
GlobalSimLoopExitEvent *	simulate_limit_event = nullptr
static std::unique_ptr< SimulatorThreads >	simulatorThreads
GlobalSimLoopExitEvent *	global_exit_event = nullptr
	Simulate for num_cycles additional cycles.
statistics::Formula &	simSeconds = rootStats.simSeconds
statistics::Value &	simTicks = rootStats.simTicks
statistics::Value &	simFreq = rootStats.simFreq
statistics::Value &	hostSeconds = rootStats.hostSeconds
const char *	hostname = "m5.eecs.umich.edu"
const unsigned	seconds_since_epoch = 1000 * 1000 * 1000
	Approximate seconds since the epoch (1/1/1970).
Asynchronous event flags.
To avoid races, signal handlers simply set these flags, which are then checked in the main event loop. Defined in main.cc.
volatile bool	async_event = false
	Some asynchronous event has happened.
volatile bool	async_statdump = false
	Async request to dump stats.
volatile bool	async_statreset = false
	Async request to reset stats.
volatile bool	async_exit = false
	Async request to exit simulator.
volatile bool	async_io = false
	Async I/O request (SIGIO).
volatile bool	async_exception = false
	Python exception.

Detailed Description

Copyright (c) 2024 Arm Limited All rights reserved.

SSTResponderInterface provides an interface specified gem5's expectations on the functionality of an SST Responder.

the profiler uses GPUCoalescer code even though the GPUCoalescer is not built for all ISAs, which can lead to run/link time errors.

On Linux, MAP_NORESERVE allow us to simulate a very large memory without committing to actually providing the swap space on the host.

Copyright (c) 2019, 2020 Inria All rights reserved.

Copyright (c) 2018-2020 Inria All rights reserved.

Copyright (c) 2019 Metempsy Technology Consulting All rights reserved.

Copyright (c) 2018 Metempsy Technology Consulting Copyright (c) 2024 Samsung Electronics All rights reserved.

Copyright (c) 2018 Metempsy Technology Consulting All rights reserved.

Note: For details on the implementation see https://wiki.osdev.org/%228042%22_PS/2_Controller.

UFS command flow state machine digraph CommandFlow{ node [fontsize=10]; IDLE -> transferHandler [ label=" transfer/task/command request " fontsize=6]; transferHandler -> command [ label=" It is a command " fontsize=6]; command -> IDLE [ label=" Command done, no further action " fontsize=6]; transferHandler -> taskStart [ label=" It is a task " fontsize=6]; taskStart -> finalUTP [ label=" Task handled, now acknowledge (UFS) " fontsize=6]; transferHandler -> transferStart [ label=" It is a transfer " fontsize=6]; transferStart -> SCSIResume [ label=" Transfer, obtain the specific command " fontsize=6]; SCSIResume -> DiskDataFlowPhase [ label=" Disk data transfer (see other graphs) " fontsize=6]; SCSIResume -> DeviceDataPhase [ label=" Device info transfer (handled in SCSIResume) " fontsize=6]; DiskDataFlowPhase -> transferDone [ label=" Transfer done, acknowledge SCSI command " fontsize=6]; DeviceDataPhase -> transferDone [ label=" Transfer done, acknowledge SCSI command " fontsize=6]; transferDone -> finalUTP [ label=" Transfer handled, now acknowledge (UFS) " fontsize=6]; finalUTP -> readDone [ label=" All handled, clear data structures " fontsize=6]; readDone -> IDLE [ label=" All handled, nothing outstanding " fontsize=6]; readDone -> transferHandler [ label=" All handled, handle next outstanding " fontsize=6]; }.

Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.

The license below extends only to copyright in the software and shall not be construed as granting a license to any other intellectual property including but not limited to intellectual property relating to a hardware implementation of the functionality of the software licensed hereunder. You may use the software subject to the license terms below provided that you ensure that this notice is replicated unmodified and in its entirety in all distributions of the software, modified or unmodified, in source code or in binary form.

Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Todo:

Generalized N-dimensinal vector documentation key stats interval stats – these both can use the same function that prints out a specific set of stats VectorStandardDeviation totals Document Namespaces

UFS read transaction flow state machine digraph readFlow{ node [fontsize=10]; getScatterGather -> commitReadFromDisk [ label=" Put the information about the data transfer to the disk " fontsize=6]; commitReadFromDisk -> waitForReads [ label=" Push the reads to the flashmodel and wait for callbacks " fontsize=6]; waitForReads -> pushToDMA [ label=" Push to the DMA and wait for them to finish " fontsize=6]; pushToDMA -> waitForReads [ label=" Wait for the next disk event " fontsize=6]; pushToDMA -> waitForDMA [ label=" Wait for the last DMA transfer to finish " fontsize=6]; waitForDMA -> finishTransfer [ label=" Continue with the command flow " fontsize=6]; } UFS write transaction flow state machine digraph WriteFlow{ node [fontsize=10]; getScatterGather -> getFromDMA [ label=" Put the transfer information to the DMA " fontsize=6]; getFromDMA -> waitForDMA [ label=" Wait for dma actions to arrive " fontsize=6]; waitForDMA -> pushToDisk [ label=" Push arrived DMA to disk " fontsize=6]; pushToDisk -> waitForDMA [ label=" Wait for next DMA action " fontsize=6]; pushToDisk -> waitForDisk [ label=" All DMA actions are done, wait for disk " fontsize=6]; waitForDisk -> finishTransfer [ label=" All transactions are done , continue the command flow " fontsize=6]; }

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the Access Map Pattern Matching Prefetcher

References: Access map pattern matching for high performance data cache prefetch. Ishii, Y., Inaba, M., & Hiraki, K. (2011). Journal of Instruction-Level Parallelism, 13, 1-24.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the 'A Best-Offset Prefetcher' Reference: Michaud, P. (2015, June). A best-offset prefetcher. In 2nd Data Prefetching Championship.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the Indirect Memory Prefetcher

References: IMP: Indirect memory prefetcher. Yu, X., Hughes, C. J., Satish, N., & Devadas, S. (2015, December). In Proceedings of the 48th International Symposium on Microarchitecture (pp. 178-190). ACM.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the Irregular Stream Buffer prefetcher Reference: Jain, A., & Lin, C. (2013, December). Linearizing irregular memory accesses for improved correlated prefetching. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 247-259). ACM.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the 'Proactive Instruction Fetch' prefetcher Reference: Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December). Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 152-162). ACM.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the 'Sandbox Based Optimal Offset Estimation' Reference: Brown, N. T., & Sendag, R. Sandbox Based Optimal Offset Estimation.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the Signature Path Prefetcher

References: Lookahead prefetching with signature path J Kim, PV Gratz, ALN Reddy The 2nd Data Prefetching Championship (DPC2) The filter feature described in the paper is not implemented, as it redundant prefetches are dropped by the cache.

The license below extends only to copyright in the software and shall not be construed as granting a license to any other intellectual property including but not limited to intellectual property relating to a hardware implementation of the functionality of the software licensed hereunder. You may use the software subject to the license terms below provided that you ensure that this notice is replicated unmodified and in its entirety in all distributions of the software, modified or unmodified, in source code or in binary form.

Copyright (c) 2018 Metempsy Technology Consulting All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the Signature Path Prefetcher (v2)

References: Path confidence based lookahead prefetching Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy, Chris Wilkerson, and Zeshan Chishti. 2016. In The 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-49). IEEE Press, Piscataway, NJ, USA, Article 60, 12 pages.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. The SlimAMPM Prefetcher Reference: Towards Bandwidth-Efficient Prefetching with Slim AMPM. Young, Vinson, and A. Krishna. The 2nd Data Prefetching Championship (2015).

This prefetcher uses two other prefetchers, the AMPM and the DCPT.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the Spatio-Temporal Memory Streaming Prefetcher (STeMS) Reference: Spatio-temporal memory streaming. Somogyi, S., Wenisch, T. F., Ailamaki, A., & Falsafi, B. (2009). ACM SIGARCH Computer Architecture News, 37(3), 69-80.

Notes:

• The functionality described in the paper as Streamed Value Buffer (SVB) is not implemented here, as this is handled by the QueuedPrefetcher class

The license below extends only to copyright in the software and shall not be construed as granting a license to any other intellectual property including but not limited to intellectual property relating to a hardware implementation of the functionality of the software licensed hereunder. You may use the software subject to the license terms below provided that you ensure that this notice is replicated unmodified and in its entirety in all distributions of the software, modified or unmodified, in source code or in binary form.

Copyright (c) 2020 Inria All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

On FreeBSD or OSX the MAP_NORESERVE flag does not exist, so simply make it 0.

here we guard the coalescer code with ifdefs as there is no easy way to refactor this code without removing GPUCoalescer stats from the profiler.

eventually we should use probe points here, but until then these ifdefs will serve.

• OutgoingRequestBridge acts as a SimObject owning pointers to both a gem5 OutgoingRequestPort and an SST port (via SSTResponderInterface). This bridge will forward gem5 packets from the gem5 port to the SST interface. Responses from SST will be handle by OutgoingRequestPort itself. Note: the bridge should be decoupled from the SST libraries so that it'll be SST-version-independent. Thus, there's no translation between a gem5 packet and SST Response here.

  • OutgoingRequestPort is a specialized ResponsePort working with OutgoingRequestBridge.

  This interfaces expects SST Responder to be able to handle gem5 packet on recvTimingReq(), recvRespRetry(), and recvFunctional().

Typedef Documentation

_amd_queue_properties32_t

typedef uint32_t gem5::_amd_queue_properties32_t

Definition at line 62 of file hsa_queue.hh.

Addr

typedef uint64_t gem5::Addr

Address type This will probably be moved somewhere else in the near future.

This should be at least as big as the biggest address width in use in the system, which will probably be 64 bits.

Definition at line 147 of file types.hh.

amd_signal_kind64_t

typedef int64_t gem5::amd_signal_kind64_t

Definition at line 40 of file hsa_signal.hh.

amd_signal_t

typedef struct gem5::amd_signal_s gem5::amd_signal_t

AMDKernelCode

typedef struct gem5::GEM5_PACKED gem5::AMDKernelCode

ArchPageTable

typedef MultiLevelPageTable<LongModePTE<47, 39>, LongModePTE<38, 30>, LongModePTE<29, 21>, LongModePTE<20, 12> > gem5::ArchPageTable

Definition at line 82 of file process.cc.

AuxVector

template<class IntType >

using gem5::AuxVector = typedef gem5::auxv::AuxVector<IntType>

Definition at line 132 of file aux_vector.hh.

BaseHTMCheckpointPtr

typedef std::unique_ptr<BaseHTMCheckpoint> gem5::BaseHTMCheckpointPtr

Definition at line 127 of file htm.hh.

BaseIndexingPolicy

using gem5::BaseIndexingPolicy = typedef IndexingPolicyTemplate<AddrTypes>

Definition at line 215 of file base.hh.

BasicBlockRange

typedef std::pair<Addr, Addr> gem5::BasicBlockRange

Probe for SimPoints BBV generation.

Start and end address of basic block for SimPoint profiling. This structure is used to look up the hash table of BBVs.

• first: PC of first inst in basic block
• second: PC of last inst in basic block

Definition at line 61 of file simpoint.hh.

BTBIndexingPolicy

using gem5::BTBIndexingPolicy = typedef IndexingPolicyTemplate<BTBTagType>

Definition at line 70 of file btb_entry.hh.

CachesMask

typedef uint32_t gem5::CachesMask

Definition at line 80 of file fa_lru.hh.

CheckpointOut

typedef std::ostream gem5::CheckpointOut

Definition at line 66 of file serialize.hh.

ConstVPtr

template<typename T >

using gem5::ConstVPtr = typedef ConstProxyPtr<T, SETranslatingPortProxy>

Definition at line 398 of file proxy_ptr.hh.

ContextID

typedef int gem5::ContextID

Globally unique thread context ID.

Definition at line 239 of file types.hh.

Counter

typedef int64_t gem5::Counter

Statistics counter type.

All counters are of 64-bit values.

Not much excuse for not using a 64-bit integer here, but if you're desperate and only run short simulations you could make this 32 bits.

Definition at line 53 of file types.hh.

EthPacketPtr

typedef std::shared_ptr<EthPacketData> gem5::EthPacketPtr

Definition at line 90 of file etherpkt.hh.

EventWrapper

template<class T , void(T::*)() F>

using gem5::EventWrapper = typedef MemberEventWrapper<F>

Definition at line 1133 of file eventq.hh.

Fault

typedef std::shared_ptr<FaultBase> gem5::Fault

Definition at line 249 of file types.hh.

FaultName

typedef const char* gem5::FaultName

Definition at line 55 of file faults.hh.

FaultStat

typedef statistics::Scalar gem5::FaultStat

Definition at line 56 of file faults.hh.

FUDDiterator

typedef std::vector<FUDesc*>::const_iterator gem5::FUDDiterator

Definition at line 91 of file func_unit.hh.

GPUDynInstPtr

typedef std::shared_ptr<GPUDynInst> gem5::GPUDynInstPtr

Definition at line 49 of file misc.hh.

hst_stat

typedef struct stat gem5::hst_stat

Definition at line 554 of file syscall_emul.hh.

hst_stat64

typedef struct stat64 gem5::hst_stat64

Definition at line 555 of file syscall_emul.hh.

hst_statfs

typedef struct statfs gem5::hst_statfs

Definition at line 549 of file syscall_emul.hh.

InstSeqNum

typedef uint64_t gem5::InstSeqNum

Definition at line 40 of file inst_seq.hh.

InstTag

typedef unsigned int gem5::InstTag

Definition at line 43 of file inst_seq.hh.

IntSinkPin

template<class Compat >

using gem5::IntSinkPin = typedef IntSinkPinBase

Definition at line 75 of file intpin.hh.

IntSourcePin

template<class Compat >

using gem5::IntSourcePin = typedef IntSourcePinBase

Definition at line 94 of file intpin.hh.

ListenSocketPtr

using gem5::ListenSocketPtr = typedef std::unique_ptr<ListenSocket>

Definition at line 112 of file socket.hh.

MemBackdoorPtr

typedef MemBackdoor* gem5::MemBackdoorPtr

Definition at line 127 of file backdoor.hh.

MemberFunctionArgsTuple_t

template<auto F>

using gem5::MemberFunctionArgsTuple_t = typedef typename MemberFunctionSignature<decltype(F)>::argsTuple_t

Definition at line 92 of file type_traits.hh.

MemberFunctionClass_t

template<auto F>

using gem5::MemberFunctionClass_t = typedef typename MemberFunctionSignature<decltype(F)>::class_t

Definition at line 84 of file type_traits.hh.

MemberFunctionReturn_t

template<auto F>

using gem5::MemberFunctionReturn_t = typedef typename MemberFunctionSignature<decltype(F)>::return_t

Definition at line 88 of file type_traits.hh.

MicroPC

typedef uint16_t gem5::MicroPC

Definition at line 149 of file types.hh.

OPDDiterator

typedef std::vector<OpDesc*>::const_iterator gem5::OPDDiterator

Definition at line 90 of file func_unit.hh.

P9MsgInfoMap

typedef std::map<P9MsgType, P9MsgInfo> gem5::P9MsgInfoMap

Definition at line 76 of file fs9p.cc.

P9MsgType

typedef uint8_t gem5::P9MsgType

Definition at line 54 of file fs9p.hh.

P9Tag

typedef uint16_t gem5::P9Tag

Definition at line 55 of file fs9p.hh.

PacketDataPtr

typedef uint8_t* gem5::PacketDataPtr

Definition at line 72 of file packet.hh.

PacketId

typedef uint64_t gem5::PacketId

Definition at line 74 of file packet.hh.

PacketList

typedef std::list<PacketPtr> gem5::PacketList

Definition at line 73 of file packet.hh.

PacketPtr

typedef Packet * gem5::PacketPtr

Definition at line 70 of file thread_context.hh.

PhysRegIdPtr

using gem5::PhysRegIdPtr = typedef PhysRegId*

Definition at line 510 of file reg_class.hh.

PM4FrameCtrl

typedef struct gem5::GEM5_PACKED gem5::PM4FrameCtrl

PM4Header

typedef struct gem5::GEM5_PACKED gem5::PM4Header

PM4 packets.

PM4IndirectBuf

typedef struct gem5::GEM5_PACKED gem5::PM4IndirectBuf

PM4IndirectBufConst

typedef struct gem5::GEM5_PACKED gem5::PM4IndirectBufConst

PM4MapProcess

typedef struct gem5::GEM5_PACKED gem5::PM4MapProcess

PM4MapProcessV2

typedef struct gem5::GEM5_PACKED gem5::PM4MapProcessV2

PM4MapQueues

typedef struct gem5::GEM5_PACKED gem5::PM4MapQueues

PM4QueryStatus

typedef struct gem5::GEM5_PACKED gem5::PM4QueryStatus

PM4ReleaseMem

typedef struct gem5::GEM5_PACKED gem5::PM4ReleaseMem

PM4RunList

typedef struct gem5::GEM5_PACKED gem5::PM4RunList

PM4SetResources

typedef struct gem5::GEM5_PACKED gem5::PM4SetResources

PM4SetUConfig

typedef struct gem5::GEM5_PACKED gem5::PM4SetUConfig

PM4SetUconfigReg

typedef struct gem5::GEM5_PACKED gem5::PM4SetUconfigReg

PM4SwitchBuf

typedef struct gem5::GEM5_PACKED gem5::PM4SwitchBuf

PM4UnmapQueues

typedef struct gem5::GEM5_PACKED gem5::PM4UnmapQueues

PM4WaitRegMem

typedef struct gem5::GEM5_PACKED gem5::PM4WaitRegMem

PM4WriteData

typedef struct gem5::GEM5_PACKED gem5::PM4WriteData

PortID

typedef int16_t gem5::PortID

Port index/ID type, and a symbolic name for an invalid port id.

Definition at line 245 of file types.hh.

PrimaryQueue

typedef gem5::PrimaryQueue gem5::PrimaryQueue

QueueDesc

typedef struct gem5::GEM5_PACKED gem5::QueueDesc

Queue descriptor with relevant MQD attributes.

Taken from https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/ drivers/gpu/drm/amd/include/v9_structs.h

RegIndex

using gem5::RegIndex = typedef uint16_t

Definition at line 176 of file types.hh.

RegisterBankBE

using gem5::RegisterBankBE = typedef RegisterBank<ByteOrder::big>

Definition at line 1127 of file reg_bank.hh.

RegisterBankLE

using gem5::RegisterBankLE = typedef RegisterBank<ByteOrder::little>

Definition at line 1126 of file reg_bank.hh.

RegVal

using gem5::RegVal = typedef uint64_t

Definition at line 173 of file types.hh.

ReplacementCandidates

typedef std::vector<ReplaceableEntry*> gem5::ReplacementCandidates

Replacement candidates as chosen by the indexing policy.

Definition at line 46 of file base.hh.

RequestorID

typedef uint16_t gem5::RequestorID

Definition at line 95 of file request.hh.

RequestPtr

typedef std::shared_ptr<Request> gem5::RequestPtr

Definition at line 94 of file request.hh.

sdmaAESCounter

typedef struct gem5::GEM5_PACKED gem5::sdmaAESCounter

sdmaAESKey

typedef struct gem5::GEM5_PACKED gem5::sdmaAESKey

sdmaAESLoad

typedef struct gem5::GEM5_PACKED gem5::sdmaAESLoad

sdmaAESOffset

typedef struct gem5::GEM5_PACKED gem5::sdmaAESOffset

sdmaAQLBarrierOr

typedef struct gem5::GEM5_PACKED gem5::sdmaAQLBarrierOr

sdmaAQLCopy

typedef struct gem5::GEM5_PACKED gem5::sdmaAQLCopy

sdmaAtomic

typedef struct gem5::GEM5_PACKED gem5::sdmaAtomic

sdmaAtomicHeader

typedef struct gem5::GEM5_PACKED gem5::sdmaAtomicHeader

sdmaCondExec

typedef struct gem5::GEM5_PACKED gem5::sdmaCondExec

sdmaConstFill

typedef struct gem5::GEM5_PACKED gem5::sdmaConstFill

sdmaConstFillHeader

typedef struct gem5::GEM5_PACKED gem5::sdmaConstFillHeader

sdmaCopy

typedef struct gem5::GEM5_PACKED gem5::sdmaCopy

SDMA packets - see src/core/inc/sdma_registers.h in ROCR-Runtime.

sdmaDataFillMulti

typedef struct gem5::GEM5_PACKED gem5::sdmaDataFillMulti

sdmaDummyTrap

typedef struct gem5::GEM5_PACKED gem5::sdmaDummyTrap

sdmaFence

typedef struct gem5::GEM5_PACKED gem5::sdmaFence

sdmaHeaderAgentDisp

typedef struct gem5::GEM5_PACKED gem5::sdmaHeaderAgentDisp

sdmaIndirectBuffer

typedef struct gem5::GEM5_PACKED gem5::sdmaIndirectBuffer

sdmaIndirectBufferHeader

typedef struct gem5::GEM5_PACKED gem5::sdmaIndirectBufferHeader

sdmaMemInc

typedef struct gem5::GEM5_PACKED gem5::sdmaMemInc

sdmaPollRegMem

typedef struct gem5::GEM5_PACKED gem5::sdmaPollRegMem

sdmaPollRegMemHeader

typedef struct gem5::GEM5_PACKED gem5::sdmaPollRegMemHeader

sdmaPredExec

typedef struct gem5::GEM5_PACKED gem5::sdmaPredExec

sdmaPredExecHeader

typedef struct gem5::GEM5_PACKED gem5::sdmaPredExecHeader

sdmaPtePde

typedef struct gem5::GEM5_PACKED gem5::sdmaPtePde

SDMAQueueDesc

typedef struct gem5::GEM5_PACKED gem5::SDMAQueueDesc

Queue descriptor for SDMA-based user queues (RLC queues).

Taken from https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/ drivers/gpu/drm/amd/include/v9_structs.h

sdmaSemaphore

typedef struct gem5::GEM5_PACKED gem5::sdmaSemaphore

sdmaSRBMWrite

typedef struct gem5::GEM5_PACKED gem5::sdmaSRBMWrite

sdmaSRBMWriteHeader

typedef struct gem5::GEM5_PACKED gem5::sdmaSRBMWriteHeader

sdmaTimestamp

typedef struct gem5::GEM5_PACKED gem5::sdmaTimestamp

sdmaTrap

typedef struct gem5::GEM5_PACKED gem5::sdmaTrap

sdmaWrite

typedef struct gem5::GEM5_PACKED gem5::sdmaWrite

SenderState

typedef RubyTester::SenderState gem5::SenderState

Definition at line 39 of file Check.cc.

StaticInstPtr

typedef RefCountingPtr<StaticInst> gem5::StaticInstPtr

Definition at line 38 of file static_inst_fwd.hh.

TaggedIndexingPolicy

using gem5::TaggedIndexingPolicy = typedef IndexingPolicyTemplate<TaggedTypes>

Definition at line 67 of file tagged_entry.hh.

ThreadID

typedef int16_t gem5::ThreadID

Thread index/ID type.

Definition at line 235 of file types.hh.

Tick

typedef uint64_t gem5::Tick

Tick count type.

Definition at line 58 of file types.hh.

TlbEntryTrie

typedef Trie<Addr, X86ISA::TlbEntry> gem5::TlbEntryTrie

Definition at line 61 of file pagetable.hh.

TranslationGenPtr

using gem5::TranslationGenPtr = typedef std::unique_ptr<TranslationGen>

Definition at line 131 of file translation_gen.hh.

VectorMask

typedef std::bitset<std::numeric_limits<unsigned long long>::digits> gem5::VectorMask

Definition at line 48 of file misc.hh.

VPtr

template<typename T = void>

using gem5::VPtr = typedef ProxyPtr<T, SETranslatingPortProxy>

Definition at line 400 of file proxy_ptr.hh.

WaiterList

typedef std::list<WaiterState> gem5::WaiterList

Definition at line 104 of file futex_map.hh.

Enumeration Type Documentation

anonymous enum

anonymous enum

Enumerator
CoreTag
MemTag
RevTag
SerialTag
CmdTag
NoneTag

Definition at line 49 of file atag.hh.

anonymous enum

anonymous enum

Enumerator
SMMU_CACHE_REPL_ROUND_ROBIN
SMMU_CACHE_REPL_RANDOM
SMMU_CACHE_REPL_LRU

Definition at line 57 of file smmu_v3_caches.hh.

anonymous enum

anonymous enum

Enumerator
SMMU_SECURE_SZ
SMMU_PAGE_ZERO_SZ
SMMU_PAGE_ONE_SZ
SMMU_REG_SIZE

Definition at line 48 of file smmu_v3_defs.hh.

anonymous enum

anonymous enum

Enumerator
STE_CONFIG_ABORT
STE_CONFIG_BYPASS
STE_CONFIG_STAGE1_ONLY
STE_CONFIG_STAGE2_ONLY
STE_CONFIG_STAGE1_AND_2

Definition at line 56 of file smmu_v3_defs.hh.

anonymous enum

anonymous enum

Enumerator
STAGE1_CFG_1L
STAGE1_CFG_2L_4K
STAGE1_CFG_2L_64K

Definition at line 65 of file smmu_v3_defs.hh.

anonymous enum

anonymous enum

Enumerator
ST_CFG_SPLIT_SHIFT
ST_CD_ADDR_SHIFT
CD_TTB_SHIFT
STE_S2TTB_SHIFT

Definition at line 72 of file smmu_v3_defs.hh.

anonymous enum

anonymous enum

Enumerator
TRANS_GRANULE_4K
TRANS_GRANULE_64K
TRANS_GRANULE_16K
TRANS_GRANULE_INVALID

Definition at line 80 of file smmu_v3_defs.hh.

anonymous enum

anonymous enum

Enumerator
ST_BASE_ADDR_MASK
ST_CFG_SIZE_MASK
ST_CFG_SPLIT_MASK
ST_CFG_FMT_MASK
ST_CFG_FMT_LINEAR
ST_CFG_FMT_2LEVEL
ST_L2_SPAN_MASK
ST_L2_ADDR_MASK
VMT_BASE_ADDR_MASK
VMT_BASE_SIZE_MASK
Q_BASE_ADDR_MASK
Q_BASE_SIZE_MASK
E_BASE_ADDR_MASK

Definition at line 88 of file smmu_v3_defs.hh.

anonymous enum

anonymous enum

Enumerator
CR0_SMMUEN_MASK
CR0_PRIQEN_MASK
CR0_EVENTQEN_MASK
CR0_CMDQEN_MASK
CR0_ATSCHK_MASK
CR0_VMW_MASK

Definition at line 353 of file smmu_v3_defs.hh.

anonymous enum

anonymous enum

Enumerator
SMMU_MAX_TRANS_ID

Definition at line 456 of file smmu_v3_defs.hh.

_hsa_queue_type_t

enum gem5::_hsa_queue_type_t

Enumerator
_HSA_QUEUE_TYPE_MULTI
_HSA_QUEUE_TYPE_SINGLE

Definition at line 40 of file hsa_queue.hh.

amd_signal_kind_t

enum gem5::amd_signal_kind_t

Enumerator
AMD_SIGNAL_KIND_INVALID
AMD_SIGNAL_KIND_USER
AMD_SIGNAL_KIND_DOORBELL
AMD_SIGNAL_KIND_LEGACY_DOORBELL

Definition at line 41 of file hsa_signal.hh.

amdgpu_hwreg

enum gem5::amdgpu_hwreg

Enumerator
HW_REG_MODE
HW_REG_STATUS
HW_REG_TRAPSTS
HW_REG_HW_ID
HW_REG_GPR_ALLOC
HW_REG_LDS_ALLOC
HW_REG_IB_STS
HW_REG_SH_MEM_BASES
HW_REG_TBA_LO
HW_REG_TBA_HI
HW_REG_TMA_LO
HW_REG_TMA_HI
HW_REG_FLAT_SCR_LO
HW_REG_FLAT_SCR_HI
HW_REG_XNACK_MASK
HW_REG_HW_ID1
HW_REG_HW_ID2
HW_REG_POPS_PACKER
HW_REG_SHADER_CYCLES

Definition at line 49 of file hwreg_defines.hh.

AuxiliaryVectorType

enum gem5::AuxiliaryVectorType

Enumerator
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
M5_BASE_PLATFORM
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT
GEM5_DEPRECATE_AT

Definition at line 99 of file aux_vector.hh.

BlockMemoryHop

enum gem5::BlockMemoryHop : int

Enumerator
BlockSend
BlockRecv

Definition at line 61 of file misc.hh.

BMIRegOffset

enum gem5::BMIRegOffset

Enumerator
BMICommand
BMIStatus
BMIDescTablePtr

Definition at line 57 of file ide_ctrl.cc.

ChipCommandRegister

enum gem5::ChipCommandRegister

Enumerator
CR_TXE
CR_TXD
CR_RXE
CR_RXD
CR_TXR
CR_RXR
CR_SWI
CR_RST

Definition at line 85 of file ns_gige_reg.h.

ClockrunControlStatusRegister

enum gem5::ClockrunControlStatusRegister

Enumerator
CCSR_CLKRUN_EN

Definition at line 335 of file ns_gige_reg.h.

CMDSTSFlatsForDescriptors

enum gem5::CMDSTSFlatsForDescriptors

Enumerator
CMDSTS_OWN
CMDSTS_MORE
CMDSTS_INTR
CMDSTS_ERR
CMDSTS_OK
CMDSTS_LEN_MASK
CMDSTS_DEST_MASK
CMDSTS_DEST_SELF
CMDSTS_DEST_MULTI

Definition at line 394 of file ns_gige_reg.h.

ConfigurationRegisters

enum gem5::ConfigurationRegisters

Enumerator
CFGR_ZERO
CFGR_LNKSTS
CFGR_SPDSTS
CFGR_SPDSTS1
CFGR_SPDSTS0
CFGR_DUPSTS
CFGR_TBI_EN
CFGR_RESERVED
CFGR_MODE_1000
CFGR_AUTO_1000
CFGR_PINT_CTL
CFGR_PINT_DUPSTS
CFGR_PINT_LNKSTS
CFGR_PINT_SPDSTS
CFGR_TMRTEST
CFGR_MRM_DIS
CFGR_MWI_DIS
CFGR_T64ADDR
CFGR_PCI64_DET
CFGR_DATA64_EN
CFGR_M64ADDR
CFGR_PHY_RST
CFGR_PHY_DIS
CFGR_EXTSTS_EN
CFGR_REQALG
CFGR_SB
CFGR_POW
CFGR_EXD
CFGR_PESEL
CFGR_BROM_DIS
CFGR_EXT_125
CFGR_BEM

Definition at line 98 of file ns_gige_reg.h.

DevAction_t

enum gem5::DevAction_t

Enumerator
ACT_NONE
ACT_CMD_WRITE
ACT_CMD_COMPLETE
ACT_CMD_ERROR
ACT_SELECT_WRITE
ACT_STAT_READ
ACT_DATA_READY
ACT_DATA_READ_BYTE
ACT_DATA_READ_SHORT
ACT_DATA_WRITE_BYTE
ACT_DATA_WRITE_SHORT
ACT_DMA_READY
ACT_DMA_DONE
ACT_SRST_SET
ACT_SRST_CLEAR

Definition at line 156 of file ide_disk.hh.

DeviceRegisterAddress

enum gem5::DeviceRegisterAddress

Enumerator
CR
CFGR
MEAR
PTSCR
ISR
IMR
IER
IHR
TXDP
TXDP_HI
TX_CFG
GPIOR
RXDP
RXDP_HI
RX_CFG
PQCR
WCSR
PCR
RFCR
RFDR
BRAR
BRDR
SRR
MIBC
MIB_START
MIB_END
VRCR
VTCR
VDR
CCSR
TBICR
TBISR
TANAR
TANLPAR
TANER
TESR
M5REG
LAST
RESERVED

Definition at line 41 of file ns_gige_reg.h.

DevState_t

enum gem5::DevState_t

Enumerator
Device_Idle_S
Device_Idle_SI
Device_Idle_NS
Device_Srst
Command_Execution
Prepare_Data_In
Data_Ready_INTRQ_In
Transfer_Data_In
Prepare_Data_Out
Data_Ready_INTRQ_Out
Transfer_Data_Out
Prepare_Data_Dma
Transfer_Data_Dma
Device_Dma_Abort

Definition at line 175 of file ide_disk.hh.

DISPATCH_STATUS

enum gem5::DISPATCH_STATUS

Enumerator
EMPTY
EXREADY
SKIP

Definition at line 59 of file exec_stage.hh.

DmaState_t

enum gem5::DmaState_t

Enumerator
Dma_Idle
Dma_Start
Dma_Transfer

Definition at line 204 of file ide_disk.hh.

EEPROMAccessRegister

enum gem5::EEPROMAccessRegister

Enumerator
MEAR_EEDI
MEAR_EEDO
MEAR_EECLK
MEAR_EESEL
MEAR_MDIO
MEAR_MDDIR
MEAR_MDC

Definition at line 135 of file ns_gige_reg.h.

Events_t

enum gem5::Events_t

Enumerator
None
Transfer
ReadWait
WriteWait
PrdRead
DmaRead
DmaWrite

Definition at line 145 of file ide_disk.hh.

EXEC_POLICY

enum gem5::EXEC_POLICY

Enumerator
OLDEST
RR

Definition at line 73 of file compute_unit.hh.

ExtendedFlagsForDescriptors

enum gem5::ExtendedFlagsForDescriptors

Enumerator
EXTSTS_UDPERR
EXTSTS_UDPPKT
EXTSTS_TCPERR
EXTSTS_TCPPKT
EXTSTS_IPERR
EXTSTS_IPPKT

Definition at line 409 of file ns_gige_reg.h.

GeneralPurposeIOControlRegister

enum gem5::GeneralPurposeIOControlRegister

Enumerator
GPIOR_UNUSED
GPIOR_GP5_IN
GPIOR_GP4_IN
GPIOR_GP3_IN
GPIOR_GP2_IN
GPIOR_GP1_IN
GPIOR_GP5_OE
GPIOR_GP4_OE
GPIOR_GP3_OE
GPIOR_GP2_OE
GPIOR_GP1_OE
GPIOR_GP5_OUT
GPIOR_GP4_OUT
GPIOR_GP3_OUT
GPIOR_GP2_OUT
GPIOR_GP1_OUT

Definition at line 227 of file ns_gige_reg.h.

HtmCacheFailure

enum class gem5::HtmCacheFailure

strong

Enumerator
NO_FAIL
FAIL_SELF
FAIL_REMOTE
FAIL_OTHER

Definition at line 59 of file htm.hh.

HtmFailureFaultCause

enum class gem5::HtmFailureFaultCause : int

strong

Enumerator
INVALID
EXPLICIT
NEST
SIZE
EXCEPTION
MEMORY
OTHER
NUM_CAUSES

Definition at line 47 of file htm.hh.

ihSourceId

enum gem5::ihSourceId

Enumerator
CP_EOP
TRAP_ID

Definition at line 70 of file interrupt_handler.hh.

InstMemoryHop

enum gem5::InstMemoryHop : int

Enumerator
Initiate
CoalsrSend
CoalsrRecv
GMEnqueue
Complete
InstMemoryHopMax

Definition at line 51 of file misc.hh.

InterruptStatusRegister

enum gem5::InterruptStatusRegister

Enumerator
ISR_RESERVE
ISR_TXDESC3
ISR_TXDESC2
ISR_TXDESC1
ISR_TXDESC0
ISR_RXDESC3
ISR_RXDESC2
ISR_RXDESC1
ISR_RXDESC0
ISR_TXRCMP
ISR_RXRCMP
ISR_DPERR
ISR_SSERR
ISR_RMABT
ISR_RTAB
ISR_RXSOVR
ISR_HIBINT
ISR_PHY
ISR_PME
ISR_SWI
ISR_MIB
ISR_TXURN
ISR_TXIDLE
ISR_TXERR
ISR_TXDESC
ISR_TXOK
ISR_RXORN
ISR_RXIDLE
ISR_RXEARLY
ISR_RXERR
ISR_RXDESC
ISR_RXOK
ISR_ALL
ISR_DELAY
ISR_NODELAY
ISR_IMPL
ISR_NOIMPL

Definition at line 160 of file ns_gige_reg.h.

it_opcode_type

enum gem5::it_opcode_type

PM4 opcodes.

Taken from linux tree from the following locations: https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/ drivers/gpu/drm/amd/amdkfd/kfd_pm4_opcodes.h https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/ drivers/gpu/drm/amd/amdgpu/soc15d.h

Enumerator
IT_NOP
IT_WRITE_DATA
IT_WAIT_REG_MEM
IT_INDIRECT_BUFFER
IT_RELEASE_MEM
IT_SET_UCONFIG_REG
IT_SWITCH_BUFFER
IT_INVALIDATE_TLBS
IT_MAP_PROCESS
IT_MAP_QUEUES
IT_UNMAP_QUEUES
IT_QUERY_STATUS
IT_RUN_LIST

Definition at line 52 of file pm4_defines.hh.

ItsActionType

enum class gem5::ItsActionType

strong

Enumerator
INITIAL_NOP
SEND_REQ
TERMINATE

Definition at line 62 of file gic_v3_its.hh.

kfd_mmio_remap

enum gem5::kfd_mmio_remap

Enumerator
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL

Definition at line 511 of file kfd_ioctl.h.

kfd_smi_event

enum gem5::kfd_smi_event

Enumerator
KFD_SMI_EVENT_NONE
KFD_SMI_EVENT_VMFAULT
KFD_SMI_EVENT_THERMAL_THROTTLE
KFD_SMI_EVENT_GPU_PRE_RESET
KFD_SMI_EVENT_GPU_POST_RESET

Definition at line 492 of file kfd_ioctl.h.

M5ControlRegister

enum gem5::M5ControlRegister

Enumerator
M5REG_RESERVED
M5REG_RSS
M5REG_RX_THREAD
M5REG_TX_THREAD

Definition at line 369 of file ns_gige_reg.h.

ManagementInformationBaseControlRegister

enum gem5::ManagementInformationBaseControlRegister

Enumerator
MIBC_MIBS
MIBC_ACLR
MIBC_FRZ
MIBC_WRN

Definition at line 304 of file ns_gige_reg.h.

mmio_range_t

enum gem5::mmio_range_t : int

Enumerator
NBIO_MMIO_RANGE
MMHUB_MMIO_RANGE
GFX_MMIO_RANGE
GRBM_MMIO_RANGE
IH_MMIO_RANGE
NUM_MMIO_RANGES

Definition at line 102 of file amdgpu_vm.hh.

PauseControlStatusRegister

enum gem5::PauseControlStatusRegister

Enumerator
PCR_PSEN
PCR_PS_MCAST
PCR_PS_DA
PCR_STHI_8
PCR_STLO_4
PCR_FFHI_8K
PCR_FFLO_4K
PCR_PAUSE_CNT

Definition at line 263 of file ns_gige_reg.h.

PciIntPin

enum class gem5::PciIntPin : uint8_t

strong

Enumerator
NO_INT
INTA
INTB
INTC
INTD

Definition at line 66 of file types.hh.

PCITestControlRegister

enum gem5::PCITestControlRegister

Enumerator
PTSCR_EEBIST_FAIL
PTSCR_EEBIST_EN
PTSCR_EELOAD_EN
PTSCR_RBIST_FAIL
PTSCR_RBIST_DONE
PTSCR_RBIST_EN
PTSCR_RBIST_RST
PTSCR_RBIST_RDONLY

Definition at line 147 of file ns_gige_reg.h.

Q_STATE

enum gem5::Q_STATE

Enumerator
UNBLOCKED
BLOCKED_BBIT
BLOCKED_BPKT

Definition at line 63 of file hsa_packet_processor.hh.

QueueType

enum gem5::QueueType

Enumerator
Compute
Gfx
SDMAGfx
SDMAPage
ComputeAQL
InterruptHandler
RLC

Definition at line 41 of file amdgpu_defines.hh.

ReceiveConfigurationRegister

enum gem5::ReceiveConfigurationRegister

Enumerator
RX_CFG_AEP
RX_CFG_ARP
RX_CFG_STRIPCRC
RX_CFG_RX_FD
RX_CFG_ALP
RX_CFG_AIRL
RX_CFG_MXDMA512
RX_CFG_MXDMA
RX_CFG_DRTH
RX_CFG_DRTH0

Definition at line 248 of file ns_gige_reg.h.

ReceiveFilterMatchControlRegister

enum gem5::ReceiveFilterMatchControlRegister

Enumerator
RFCR_RFEN
RFCR_AAB
RFCR_AAM
RFCR_AAU
RFCR_APM
RFCR_APAT
RFCR_APAT3
RFCR_APAT2
RFCR_APAT1
RFCR_APAT0
RFCR_AARP
RFCR_MHEN
RFCR_UHEN
RFCR_ULM
RFCR_RFADDR

Definition at line 276 of file ns_gige_reg.h.

ReceiveFilterMatchDataRegister

enum gem5::ReceiveFilterMatchDataRegister

Enumerator
RFDR_BMASK
RFDR_RFDATA0
RFDR_RFDATA1

Definition at line 296 of file ns_gige_reg.h.

RegClassType

enum gem5::RegClassType

Enumerate the classes of registers.

Enumerator
IntRegClass	Integer register.
FloatRegClass	Floating-point register.
VecRegClass	Vector Register.
VecElemClass	Vector Register Native Elem lane.
VecPredRegClass
MatRegClass	Matrix Register.
CCRegClass	Condition-code register.
MiscRegClass	Control (misc) register.
InvalidRegClass

Definition at line 59 of file reg_class.hh.

RoundingMode

enum class gem5::RoundingMode

strong

Enumerator
Downward
ToNearest
TowardZero
Upward

Definition at line 37 of file fenv.hh.

ScalarRegInitFields

enum gem5::ScalarRegInitFields : int

these enums represent the indices into the initialRegState bitfields in HsaKernelInfo.

each bit specifies whether or not the particular piece of state that the bit corresponds to should be initialized into the VGPRs/SGPRs. the order in which the fields are placed matters, as all enabled pieces of state will be initialized into contiguous registers in the same order as their position in the bitfield - which is specified in the HSA ABI.

Enumerator
PrivateSegBuf
DispatchPtr
QueuePtr
KernargSegPtr
DispatchId
FlatScratchInit
PrivateSegSize
WorkgroupIdX
WorkgroupIdY
WorkgroupIdZ
WorkgroupInfo
PrivSegWaveByteOffset
NumScalarInitFields

Definition at line 54 of file kernel_code.hh.

SDWADstVals

enum gem5::SDWADstVals : int

Enumerator
SDWA_UNUSED_PAD
SDWA_UNUSED_SEXT
SDWA_UNUSED_PRESERVE

Definition at line 56 of file inst_util.hh.

SDWASelVals

enum gem5::SDWASelVals : int

Enumerator
SDWA_BYTE_0
SDWA_BYTE_1
SDWA_BYTE_2
SDWA_BYTE_3
SDWA_WORD_0
SDWA_WORD_1
SDWA_DWORD

Definition at line 44 of file inst_util.hh.

SMMUActionType

enum gem5::SMMUActionType

Enumerator
ACTION_INITIAL_NOP
ACTION_SEND_REQ
ACTION_SEND_REQ_FINAL
ACTION_SEND_RESP
ACTION_SEND_RESP_ATS
ACTION_DELAY
ACTION_SLEEP
ACTION_TERMINATE

Definition at line 58 of file smmu_v3_proc.hh.

SMMUCommandType

enum gem5::SMMUCommandType

Enumerator
CMD_PRF_CONFIG
CMD_PRF_ADDR
CMD_CFGI_STE
CMD_CFGI_STE_RANGE
CMD_CFGI_CD
CMD_CFGI_CD_ALL
CMD_TLBI_NH_ALL
CMD_TLBI_NH_ASID
CMD_TLBI_NH_VAA
CMD_TLBI_NH_VA
CMD_TLBI_EL3_ALL
CMD_TLBI_EL3_VA
CMD_TLBI_EL2_ALL
CMD_TLBI_EL2_ASID
CMD_TLBI_EL2_VA
CMD_TLBI_EL2_VAA
CMD_TLBI_S2_IPA
CMD_TLBI_S12_VMALL
CMD_TLBI_NSNH_ALL
CMD_ATC_INV
CMD_PRI_RESP
CMD_RESUME
CMD_STALL_TERM
CMD_SYNC

Definition at line 363 of file smmu_v3_defs.hh.

soc15_ih_clientid

enum gem5::soc15_ih_clientid

Defines from driver code.

Taken from https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/ drivers/gpu/drm/amd/include/soc15_ih_clientid.h

Enumerator
SOC15_IH_CLIENTID_RLC
SOC15_IH_CLIENTID_SDMA0
SOC15_IH_CLIENTID_SDMA1
SOC15_IH_CLIENTID_SDMA2
SOC15_IH_CLIENTID_SDMA3
SOC15_IH_CLIENTID_SDMA4
SOC15_IH_CLIENTID_SDMA5
SOC15_IH_CLIENTID_SDMA6
SOC15_IH_CLIENTID_SDMA7
SOC15_IH_CLIENTID_GRBM_CP

Definition at line 56 of file interrupt_handler.hh.

SqDPPVals

enum gem5::SqDPPVals : int

Enumerator
SQ_DPP_QUAD_PERM_MAX
SQ_DPP_RESERVED
SQ_DPP_ROW_SL1
SQ_DPP_ROW_SL15
SQ_DPP_ROW_SR1
SQ_DPP_ROW_SR15
SQ_DPP_ROW_RR1
SQ_DPP_ROW_RR15
SQ_DPP_WF_SL1
SQ_DPP_WF_RL1
SQ_DPP_WF_SR1
SQ_DPP_WF_RR1
SQ_DPP_ROW_MIRROR
SQ_DPP_ROW_HALF_MIRROR
SQ_DPP_ROW_BCAST15
SQ_DPP_ROW_BCAST31

Definition at line 64 of file inst_util.hh.

STAT_STATUS

enum gem5::STAT_STATUS

Enumerator
IdleExec
BusyExec
PostExec

Definition at line 52 of file exec_stage.hh.

TBIAutoNegotiationAdvertisementRegister

enum gem5::TBIAutoNegotiationAdvertisementRegister

Enumerator
TANAR_NP
TANAR_RF2
TANAR_RF1
TANAR_PS2
TANAR_PS1
TANAR_HALF_DUP
TANAR_FULL_DUP
TANAR_UNUSED

Definition at line 356 of file ns_gige_reg.h.

TBIControlRegister

enum gem5::TBIControlRegister

Enumerator
TBICR_MR_LOOPBACK
TBICR_MR_AN_ENABLE
TBICR_MR_RESTART_AN

Definition at line 341 of file ns_gige_reg.h.

TBIStatusRegister

enum gem5::TBIStatusRegister

Enumerator
TBISR_MR_LINK_STATUS
TBISR_MR_AN_COMPLETE

Definition at line 349 of file ns_gige_reg.h.

TLB_CACHE

enum gem5::TLB_CACHE

Enumerator
TLB_MISS_CACHE_MISS
TLB_MISS_CACHE_HIT
TLB_HIT_CACHE_MISS
TLB_HIT_CACHE_HIT

Definition at line 79 of file compute_unit.hh.

TrafficType

enum gem5::TrafficType

Enumerator
BIT_COMPLEMENT_
BIT_REVERSE_
BIT_ROTATION_
NEIGHBOR_
SHUFFLE_
TORNADO_
TRANSPOSE_
UNIFORM_RANDOM_
NUM_TRAFFIC_PATTERNS_

Definition at line 47 of file GarnetSyntheticTraffic.hh.

TransmitConfigurationRegister

enum gem5::TransmitConfigurationRegister

Enumerator
TX_CFG_CSI
TX_CFG_HBI
TX_CFG_MLB
TX_CFG_ATP
TX_CFG_ECRETRY
TX_CFG_BRST_DIS
TX_CFG_MXDMA1024
TX_CFG_MXDMA512
TX_CFG_MXDMA256
TX_CFG_MXDMA128
TX_CFG_MXDMA64
TX_CFG_MXDMA32
TX_CFG_MXDMA16
TX_CFG_MXDMA8
TX_CFG_MXDMA
TX_CFG_FLTH_MASK
TX_CFG_DRTH_MASK

Definition at line 204 of file ns_gige_reg.h.

VectorRegInitFields

enum gem5::VectorRegInitFields : int

Enumerator
WorkitemIdX
WorkitemIdY
WorkitemIdZ
NumVectorInitFields

Definition at line 71 of file kernel_code.hh.

VLANIPReceiveControlRegister

enum gem5::VLANIPReceiveControlRegister

Enumerator
VRCR_RUDPE
VRCR_RTCPE
VRCR_RIPE
VRCR_IPEN
VRCR_DUTF
VRCR_DVTF
VRCR_VTREN
VRCR_VTDEN

Definition at line 313 of file ns_gige_reg.h.

VLANIPTransmitControlRegister

enum gem5::VLANIPTransmitControlRegister

Enumerator
VTCR_PPCHK
VTCR_GCHK
VTCR_VPPTI
VTCR_VGTI

Definition at line 326 of file ns_gige_reg.h.

Function Documentation

__to_number() [1/3]

template<class T >

std::enable_if_t< std::is_integral_v< T >, T > gem5::__to_number

(

const std::string &

value

)

Definition at line 117 of file str.hh.

References gem5::MipsISA::r.

__to_number() [2/3]

template<class T >

std::enable_if_t< std::is_enum_v< T >, T > gem5::__to_number

(

const std::string &

value

)

Definition at line 141 of file str.hh.

References gem5::MipsISA::r.

__to_number() [3/3]

template<class T >

std::enable_if_t< std::is_floating_point_v< T >, T > gem5::__to_number

(

const std::string &

value

)

Definition at line 149 of file str.hh.

References gem5::MipsISA::r.

_llseekFunc()

SyscallReturn gem5::_llseekFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		uint32_t	offset_high,
		uint32_t	offset_low,
		VPtr<>	result_ptr,
		int	whence
	)

Target _llseek() handler.

Definition at line 309 of file syscall_emul.cc.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyOut(), gem5::System::getGuestByteOrder(), gem5::ThreadContext::getProcessPtr(), gem5::ThreadContext::getSystemPtr(), htog(), gem5::ArmISA::offset, and gem5::MipsISA::p.

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32().

abortHandler()

void gem5::abortHandler

(

int

sigtype

)

Abort signal handler.

Definition at line 149 of file init_signals.cc.

References ccprintf(), curEventQueue(), gem5::PowerISA::eq, print_backtrace(), raiseFatalSignal(), and STATIC_ERR.

Referenced by initSignals().

acceptFunc()

template<class OS >

SyscallReturn gem5::acceptFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr<>	addrPtr,
		VPtr<>	lenPtr
	)

We poll the socket file descriptor first to guarantee that we do not block on our accept call. The socket can be opened without the non-blocking flag (it blocks). This will cause deadlocks between communicating processes.

Definition at line 2918 of file syscall_emul.hh.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), gem5::BaseBufferArg::copyOut(), gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, gem5::SyscallReturn::retry(), and gem5::ArmISA::sa.

accessFunc()

SyscallReturn gem5::accessFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		mode_t	mode
	)

Target access() handler.

Definition at line 871 of file syscall_emul.cc.

References accessImpl(), and gem5::ArmISA::mode.

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

accessImpl()

SyscallReturn gem5::accessImpl	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		std::string	path,
		mode_t	mode
	)

Definition at line 882 of file syscall_emul.cc.

References gem5::Process::checkPathRedirect(), gem5::ThreadContext::getProcessPtr(), gem5::ArmISA::mode, and gem5::MipsISA::p.

Referenced by accessFunc(), and faccessatFunc().

activate()

static void gem5::activate ( const char *  expr )

static

Definition at line 71 of file debug.cc.

References activate(), and gem5::trace::getDebugLogger().

Referenced by activate(), pybind_init_debug(), and gem5::Gicv3Redistributor::write().

addrBlockAlign()

Addr gem5::addrBlockAlign ( Addr  addr, Addr  block_size  )

inline

Returns the address of the closest aligned fixed-size block to the given address.

Parameters

addr	Input address.
block_size	Block size in bytes.

Returns

Address of the closest aligned block.

Definition at line 66 of file utils.hh.

References gem5::X86ISA::addr.

Referenced by gem5::o3::LSQ::SplitDataRequest::initiateTranslation().

addrBlockOffset()

Addr gem5::addrBlockOffset ( Addr  addr, Addr  block_size  )

inline

Calculates the offset of a given address wrt aligned fixed-size blocks.

Parameters

addr	Input address.
block_size	Block size in bytes.

Returns

Offset of the given address in bytes.

Definition at line 53 of file utils.hh.

References gem5::X86ISA::addr.

Referenced by gem5::CheckerCPU::genMemFragmentRequest(), gem5::AtomicSimpleCPU::genMemFragmentRequest(), gem5::minor::LSQ::SplitDataRequest::makeFragmentRequests(), and transferNeedsBurst().

amoMemAtomic()

template<ByteOrder Order, class XC , class MemT >

Fault gem5::amoMemAtomic	(	XC *	xc,
		trace::InstRecord *	traceData,
		MemT &	mem,
		Addr	addr,
		Request::Flags	flags,
		AtomicOpFunctor *	_amo_op
	)

Do atomic read-modify-write (AMO) in atomic mode.

Definition at line 319 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, gtoh(), mem, NoFault, and gem5::trace::InstRecord::setData().

amoMemAtomicBE()

template<class XC , class MemT >

Fault gem5::amoMemAtomicBE	(	XC *	xc,
		trace::InstRecord *	traceData,
		MemT &	mem,
		Addr	addr,
		Request::Flags	flags,
		AtomicOpFunctor *	_amo_op
	)

Definition at line 350 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, and mem.

amoMemAtomicLE()

template<class XC , class MemT >

Fault gem5::amoMemAtomicLE	(	XC *	xc,
		trace::InstRecord *	traceData,
		MemT &	mem,
		Addr	addr,
		Request::Flags	flags,
		AtomicOpFunctor *	_amo_op
	)

Definition at line 341 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, and mem.

arrayParamIn() [1/3]

template<typename T >

void gem5::arrayParamIn	(	CheckpointIn &	cp,
		const std::string &	name,
		CircleBuf< T > &	param
	)

Definition at line 257 of file circlebuf.hh.

References arrayParamIn(), gem5::CircleBuf< T >::flush(), name(), and gem5::CircleBuf< T >::write().

Referenced by arrayParamIn(), arrayParamIn(), TEST_F(), TEST_F(), TEST_F(), gem5::IGbE::DescCache< T >::unserialize(), gem5::CopyEngine::CopyEngineChannel::unserialize(), gem5::ps2::Device::unserialize(), gem5::Plic::unserialize(), gem5::Globals::unserialize(), gem5::MC146818::unserialize(), gem5::EthPacketData::unserialize(), and unserialize().

arrayParamIn() [2/3]

template<typename T >

void gem5::arrayParamIn	(	CheckpointIn &	cp,
		const std::string &	name,
		Fifo< T > &	param
	)

Definition at line 277 of file circlebuf.hh.

References arrayParamIn(), gem5::Fifo< T >::capacity(), fatal_if, gem5::Fifo< T >::flush(), name(), and gem5::Fifo< T >::write().

arrayParamIn() [3/3]

template<class T >

decltype(std::declval< T >().push_back(std::declval< typename T::value_type >()), void()) gem5::arrayParamIn	(	CheckpointIn &	cp,
		const std::string &	name,
		T &	param
	)

Definition at line 483 of file serialize.hh.

References name().

arrayParamOut() [1/2]

template<typename T >

void gem5::arrayParamOut	(	CheckpointOut &	cp,
		const std::string &	name,
		const CircleBuf< T > &	param
	)

Definition at line 247 of file circlebuf.hh.

References arrayParamOut, name(), gem5::CircleBuf< T >::peek(), and gem5::CircleBuf< T >::size().

arrayParamOut() [2/2]

template<typename T >

void gem5::arrayParamOut	(	CheckpointOut &	cp,
		const std::string &	name,
		const Fifo< T > &	param
	)

Definition at line 268 of file circlebuf.hh.

References arrayParamOut, name(), gem5::Fifo< T >::peek(), and gem5::Fifo< T >::size().

atomic_read()

ssize_t gem5::atomic_read	(	int	fd,
		void *	s,
		size_t	n
	)

Definition at line 38 of file atomicio.cc.

References gem5::ArmISA::fd, gem5::ArmISA::n, gem5::MipsISA::p, and gem5::ArmISA::s.

Referenced by TEST(), and TEST().

atomic_write()

ssize_t gem5::atomic_write	(	int	fd,
		const void *	s,
		size_t	n
	)

Definition at line 67 of file atomicio.cc.

References gem5::ArmISA::fd, gem5::ArmISA::n, gem5::MipsISA::p, and gem5::ArmISA::s.

Referenced by gem5::VncServer::accept(), gem5::Terminal::accept(), TEST(), gem5::VncServer::write(), and gem5::Terminal::write().

atSyscallPath()

template<class OS >

SyscallReturn gem5::atSyscallPath	(	ThreadContext *	tc,
		int	dirfd,
		std::string &	path
	)

Definition at line 352 of file syscall_emul.hh.

References gem5::ThreadContext::getProcessPtr(), and startswith().

bcdize()

static uint8_t gem5::bcdize ( uint8_t  val )

static

Definition at line 46 of file mc146818.cc.

References gem5::X86ISA::val.

Referenced by gem5::MC146818::setTime().

betoh()

template<typename T >

T gem5::betoh ( T  value )

inline

Definition at line 175 of file byteswap.hh.

Referenced by gem5::trace::SparcNativeTrace::check(), gem5::loader::DtbFile::findReleaseAddr(), gem5::prefetch::Base::PrefetchInfo::get(), gem5::Packet::getBE(), gtoh(), gem5::SparcISA::Decoder::moreBytes(), gem5::VncServer::recvCutText(), gem5::VncServer::recvKeyboardInput(), gem5::VncServer::recvPointerInput(), gem5::RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >::regtoh(), gem5::VncServer::requestFbUpdate(), gem5::UFSHostDevice::UFSSCSIDevice::SCSICMDHandle(), gem5::VncServer::setEncodings(), gem5::VncServer::setPixelFormat(), and gem5::SparcISA::TLB::translateFunctional().

betole()

template<typename T >

T gem5::betole ( T  value )

inline

Definition at line 165 of file byteswap.hh.

References swap_byte().

Referenced by TEST().

bindFunc()

SyscallReturn gem5::bindFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr<>	buf_ptr,
		int	addrlen
	)

Definition at line 1059 of file syscall_emul.cc.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and gem5::ArmISA::status.

bitsToFloat() [1/2]

static float gem5::bitsToFloat ( uint32_t  val )

inlinestatic

Definition at line 230 of file types.hh.

References bitsToFloat32(), and gem5::X86ISA::val.

bitsToFloat() [2/2]

static double gem5::bitsToFloat ( uint64_t  val )

inlinestatic

Definition at line 229 of file types.hh.

References bitsToFloat64(), and gem5::X86ISA::val.

Referenced by gem5::guest_abi::Argument< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::get().

bitsToFloat32()

static float gem5::bitsToFloat32 ( uint32_t  val )

inlinestatic

Definition at line 206 of file types.hh.

References gem5::ArmISA::f, gem5::ArmISA::i, gem5::ArmISA::u, and gem5::X86ISA::val.

Referenced by bitsToFloat(), and gem5::guest_abi::Argument< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::get().

bitsToFloat64()

static double gem5::bitsToFloat64 ( uint64_t  val )

inlinestatic

Definition at line 218 of file types.hh.

References gem5::ArmISA::f, gem5::ArmISA::i, gem5::ArmISA::u, and gem5::X86ISA::val.

Referenced by bitsToFloat(), gem5::guest_abi::Argument< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::get(), and updateKvmStateFPUCommon().

BitUnion32()

gem5::BitUnion32

(

IDR0

)

BitUnion64()

gem5::BitUnion64

(

XStateBV

)

brkFunc()

SyscallReturn gem5::brkFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	new_brk
	)

Target brk() handler: set brk address.

Definition at line 270 of file syscall_emul.cc.

References DPRINTF_SYSCALL, gem5::ThreadContext::getProcessPtr(), gem5::Process::memState, and gem5::MipsISA::p.

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

buildKey()

static Addr gem5::buildKey ( Addr  vpn, uint16_t  asid  )

static

Definition at line 68 of file tlb.cc.

References gem5::ArmISA::asid, and bits().

Referenced by gem5::RiscvISA::TLB::insert(), and gem5::RiscvISA::TLB::lookup().

cast_stat_info()

static const py::object gem5::cast_stat_info ( const statistics::Info *  info )

static

Definition at line 61 of file stats.cc.

References TRY_CAST.

Referenced by pybind_init_stats().

ccprintf() [1/4]

void gem5::ccprintf ( cp::Print &  print )

inline

Definition at line 130 of file cprintf.hh.

References gem5::cp::Print::endArgs().

Referenced by abortHandler(), gem5::Terminal::accept(), gem5::statistics::Text::begin(), ccprintf(), ccprintf(), ccprintf(), sc_core::sc_vector_base::checkIndex(), gem5::MemTest::completeRequest(), cprintf(), cprintf(), csprintf(), sc_core::sc_report_handler::default_handler(), gem5::X86ISA::X86FaultBase::describe(), gem5::X86ISA::PageFault::describe(), gem5::trace::Logger::dprintf_flag(), gem5::trace::IntelTraceRecord::dump(), gem5::Trie< Key, Value >::dump(), gem5::ProfileNode::dump(), gem5::Trie< Key, Value >::Node::dump(), gem5::FunctionProfile::dump(), gem5::trace::Logger::dump(), dumpDebugFlags(), gem5::ProtocolTester::dumpErrorLog(), gem5::statistics::Text::end(), gem5::memory::AbstractMemory::functionalAccess(), gem5::ArmISAInst::TmeImmOp64::generateDisassembly(), gem5::ArmISA::BranchRegReg::generateDisassembly(), gem5::ArmISA::BranchRegReg64::generateDisassembly(), gem5::ArmISA::BranchImmReg64::generateDisassembly(), gem5::ArmISA::BranchImmImmReg64::generateDisassembly(), gem5::ArmISA::DataXImmOnlyOp::generateDisassembly(), gem5::ArmISA::DataX1RegOp::generateDisassembly(), gem5::ArmISA::DataX1RegImmOp::generateDisassembly(), gem5::ArmISA::DataX1Reg2ImmOp::generateDisassembly(), gem5::ArmISA::DataX2RegOp::generateDisassembly(), gem5::ArmISA::DataX2RegImmOp::generateDisassembly(), gem5::ArmISA::DataX3RegOp::generateDisassembly(), gem5::ArmISA::DataXCondCompImmOp::generateDisassembly(), gem5::ArmISA::DataXCondCompRegOp::generateDisassembly(), gem5::ArmISA::DataXCondSelOp::generateDisassembly(), gem5::ArmISA::MicroIntImmOp::generateDisassembly(), gem5::ArmISA::MicroIntImmXOp::generateDisassembly(), gem5::ArmISA::MicroIntRegXOp::generateDisassembly(), gem5::ArmISA::MicroMemOp::generateDisassembly(), gem5::ArmISA::MicroMemPairOp::generateDisassembly(), gem5::ArmISA::SysDC64::generateDisassembly(), gem5::ArmISA::MemoryImm64::generateDisassembly(), gem5::ArmISA::MemoryDImm64::generateDisassembly(), gem5::ArmISA::MemoryDImmEx64::generateDisassembly(), gem5::ArmISA::MemoryPreIndex64::generateDisassembly(), gem5::ArmISA::MemoryPostIndex64::generateDisassembly(), gem5::ArmISA::MemoryReg64::generateDisassembly(), gem5::ArmISA::MemoryRaw64::generateDisassembly(), gem5::ArmISA::MemoryEx64::generateDisassembly(), gem5::ArmISA::MemoryLiteral64::generateDisassembly(), gem5::ArmISA::MemoryAtomicPair64::generateDisassembly(), gem5::MsrImmOp::generateDisassembly(), gem5::ImmOp::generateDisassembly(), gem5::RegImmOp::generateDisassembly(), gem5::RegImmRegOp::generateDisassembly(), gem5::RegRegRegImmOp::generateDisassembly(), gem5::RegRegImmOp::generateDisassembly(), gem5::RegImmImmOp::generateDisassembly(), gem5::RegRegImmImmOp::generateDisassembly(), gem5::RegImmRegShiftOp::generateDisassembly(), gem5::ImmOp64::generateDisassembly(), gem5::RegImmImmOp64::generateDisassembly(), gem5::RegRegImmImmOp64::generateDisassembly(), gem5::RegRegRegImmOp64::generateDisassembly(), gem5::MiscRegImmOp64::generateDisassembly(), gem5::ArmISA::PredMacroOp::generateDisassembly(), gem5::ArmISA::SmeAddOp::generateDisassembly(), gem5::ArmISA::SmeAddVlOp::generateDisassembly(), gem5::ArmISA::SmeLd1xSt1xOp::generateDisassembly(), gem5::ArmISA::SmeLdrStrOp::generateDisassembly(), gem5::ArmISA::SmeMovExtractOp::generateDisassembly(), gem5::ArmISA::SmeMovInsertOp::generateDisassembly(), gem5::ArmISA::SmeOPOp::generateDisassembly(), gem5::ArmISA::SmeRdsvlOp::generateDisassembly(), gem5::ArmISA::SmeZeroOp::generateDisassembly(), gem5::ArmISA::SveIndexIIOp::generateDisassembly(), gem5::ArmISA::SveIndexIROp::generateDisassembly(), gem5::ArmISA::SveIndexRIOp::generateDisassembly(), gem5::ArmISA::SveIndexRROp::generateDisassembly(), gem5::ArmISA::SvePredCountOp::generateDisassembly(), gem5::ArmISA::SvePredCountPredOp::generateDisassembly(), gem5::ArmISA::SveWhileOp::generateDisassembly(), gem5::ArmISA::SvePselOp::generateDisassembly(), gem5::ArmISA::SveCompTermOp::generateDisassembly(), gem5::ArmISA::SveUnaryPredOp::generateDisassembly(), gem5::ArmISA::SveUnaryUnpredOp::generateDisassembly(), gem5::ArmISA::SveUnaryWideImmUnpredOp::generateDisassembly(), gem5::ArmISA::SveUnaryWideImmPredOp::generateDisassembly(), gem5::ArmISA::SveBinImmUnpredConstrOp::generateDisassembly(), gem5::ArmISA::SveBinImmPredOp::generateDisassembly(), gem5::ArmISA::SveBinWideImmUnpredOp::generateDisassembly(), gem5::ArmISA::SveBinDestrPredOp::generateDisassembly(), gem5::ArmISA::SveBinConstrPredOp::generateDisassembly(), gem5::ArmISA::SveBinUnpredOp::generateDisassembly(), gem5::ArmISA::SveBinIdxUnpredOp::generateDisassembly(), gem5::ArmISA::SvePredLogicalOp::generateDisassembly(), gem5::ArmISA::SvePredBinPermOp::generateDisassembly(), gem5::ArmISA::SveCmpOp::generateDisassembly(), gem5::ArmISA::SveCmpImmOp::generateDisassembly(), gem5::ArmISA::SveTerPredOp::generateDisassembly(), gem5::ArmISA::SveTerUnpredOp::generateDisassembly(), gem5::ArmISA::SveTerImmUnpredOp::generateDisassembly(), gem5::ArmISA::SveReducOp::generateDisassembly(), gem5::ArmISA::SveOrdReducOp::generateDisassembly(), gem5::ArmISA::SvePtrueOp::generateDisassembly(), gem5::ArmISA::SveIntCmpOp::generateDisassembly(), gem5::ArmISA::SveIntCmpImmOp::generateDisassembly(), gem5::ArmISA::SveAdrOp::generateDisassembly(), gem5::ArmISA::SveElemCountOp::generateDisassembly(), gem5::ArmISA::SvePartBrkOp::generateDisassembly(), gem5::ArmISA::SvePartBrkPropOp::generateDisassembly(), gem5::ArmISA::SveSelectOp::generateDisassembly(), gem5::ArmISA::SveUnaryPredPredOp::generateDisassembly(), gem5::ArmISA::SveTblOp::generateDisassembly(), gem5::ArmISA::SveUnpackOp::generateDisassembly(), gem5::ArmISA::SvePredTestOp::generateDisassembly(), gem5::ArmISA::SvePredUnaryWImplicitSrcPredOp::generateDisassembly(), gem5::ArmISA::SveBinImmUnpredDestrOp::generateDisassembly(), gem5::ArmISA::SveBinImmIdxUnpredOp::generateDisassembly(), gem5::ArmISA::SveUnarySca2VecUnpredOp::generateDisassembly(), gem5::ArmISA::SveDotProdIdxOp::generateDisassembly(), gem5::ArmISA::SveDotProdOp::generateDisassembly(), gem5::ArmISA::SveComplexOp::generateDisassembly(), gem5::ArmISA::SveComplexIdxOp::generateDisassembly(), gem5::ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), gem5::ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), gem5::ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), gem5::ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), gem5::ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), gem5::ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), gem5::ArmISA::SveMemVecFillSpill::generateDisassembly(), gem5::ArmISA::SveMemPredFillSpill::generateDisassembly(), gem5::ArmISA::SveContigMemSS::generateDisassembly(), gem5::ArmISA::SveContigMemSI::generateDisassembly(), gem5::ArmISA::FpCondCompRegOp::generateDisassembly(), gem5::ArmISA::FpCondSelOp::generateDisassembly(), gem5::ArmISA::FpRegImmOp::generateDisassembly(), gem5::ArmISA::FpRegRegImmOp::generateDisassembly(), gem5::ArmISA::FpRegRegRegImmOp::generateDisassembly(), gem5::PowerISA::BranchOp::generateDisassembly(), gem5::PowerISA::BranchDispCondOp::generateDisassembly(), gem5::PowerISA::BranchRegCondOp::generateDisassembly(), gem5::PowerISA::CondLogicOp::generateDisassembly(), gem5::PowerISA::CondMoveOp::generateDisassembly(), gem5::PowerISA::FloatOp::generateDisassembly(), gem5::PowerISA::IntOp::generateDisassembly(), gem5::PowerISA::IntImmOp::generateDisassembly(), gem5::PowerISA::IntArithOp::generateDisassembly(), gem5::PowerISA::IntImmArithOp::generateDisassembly(), gem5::PowerISA::IntDispArithOp::generateDisassembly(), gem5::PowerISA::IntCompOp::generateDisassembly(), gem5::PowerISA::IntImmCompOp::generateDisassembly(), gem5::PowerISA::IntImmCompLogicOp::generateDisassembly(), gem5::PowerISA::IntLogicOp::generateDisassembly(), gem5::PowerISA::IntImmLogicOp::generateDisassembly(), gem5::PowerISA::IntShiftOp::generateDisassembly(), gem5::PowerISA::IntConcatShiftOp::generateDisassembly(), gem5::PowerISA::IntRotateOp::generateDisassembly(), gem5::PowerISA::IntConcatRotateOp::generateDisassembly(), gem5::PowerISA::IntTrapOp::generateDisassembly(), gem5::PowerISA::IntImmTrapOp::generateDisassembly(), gem5::PowerISA::MemDispOp::generateDisassembly(), gem5::PowerISA::MemDispShiftOp::generateDisassembly(), gem5::PowerISA::MemIndexOp::generateDisassembly(), gem5::PowerISA::MiscOp::generateDisassembly(), gem5::PowerISA::PowerStaticInst::generateDisassembly(), gem5::SparcISA::BlockMemMicro::generateDisassembly(), gem5::SparcISA::BlockMemImmMicro::generateDisassembly(), gem5::SparcISA::BranchDisp::generateDisassembly(), gem5::SparcISA::BranchImm13::generateDisassembly(), gem5::SparcISA::IntOpImm::generateDisassembly(), gem5::SparcISA::SetHi::generateDisassembly(), gem5::SparcISA::Mem::generateDisassembly(), gem5::SparcISA::MemImm::generateDisassembly(), gem5::SparcISA::RdPriv::generateDisassembly(), gem5::SparcISA::WrPriv::generateDisassembly(), gem5::SparcISA::WrPrivImm::generateDisassembly(), gem5::SparcISA::Trap::generateDisassembly(), gem5::X86ISA::X86MicroopBase::generateDisassembly(), gem5::X86ISA::InstOperands< Base, Operands >::generateDisassembly(), gem5::ListenSocketInet::listen(), gem5::ListenSocketUnix::listen(), gem5::trace::OstreamLogger::logMessage(), main(), gem5::minor::MinorDynInst::minorTraceInst(), gem5::statistics::VectorPrint::operator()(), gem5::statistics::DistPrint::operator()(), gem5::statistics::ScalarPrint::operator()(), operator<<(), operator<<(), operator<<(), gem5::X86ISA::operator<<(), gem5::loader::operator<<(), operator<<(), sc_core::operator<<(), gem5::networking::operator<<(), gem5::networking::operator<<(), gem5::networking::operator<<(), gem5::networking::operator<<(), sc_gem5::VcdTraceScope::output(), gem5::GenericISA::PCStateWithNext::output(), gem5::GenericISA::UPCState< InstWidth >::output(), gem5::GenericISA::DelaySlotPCState< InstWidth >::output(), gem5::GenericISA::DelaySlotUPCState< InstWidth >::output(), sc_gem5::VcdTraceValFloat< T >::output(), sc_gem5::VcdTraceValFxval< T >::output(), gem5::Logger::print(), gem5::CacheBlkPrintWrapper::print(), gem5::Packet::print(), gem5::X86ISA::CrOp< Base >::print(), gem5::X86ISA::DbgOp< Base >::print(), gem5::X86ISA::Imm8Op::print(), gem5::X86ISA::Imm64Op::print(), gem5::X86ISA::UpcOp::print(), gem5::X86ISA::FaultOp::print(), gem5::MSHR::TargetList::print(), gem5::WriteQueueEntry::TargetList::print(), gem5::MSHR::print(), gem5::WriteQueueEntry::print(), gem5::ruby::MessageBuffer::print(), gem5::ruby::Throttle::print(), gem5::trace::TarmacTracerRecord::TraceInstEntry::print(), gem5::trace::TarmacTracerRecord::TraceRegEntry::print(), gem5::trace::TarmacTracerRecord::TraceMemEntry::print(), gem5::trace::TarmacTracerRecordV8::TraceInstEntryV8::print(), gem5::trace::TarmacTracerRecordV8::TraceRegEntryV8::print(), gem5::trace::TarmacTracerRecordV8::TraceMemEntryV8::print(), gem5::ArmISA::ArmStaticInst::printCCReg(), gem5::ArmISA::ArmStaticInst::printDataInst(), gem5::ArmISA::ArmStaticInst::printExtendOperand(), gem5::ArmISA::ArmStaticInst::printFloatReg(), gem5::ArmISA::ArmStaticInst::printIntReg(), gem5::Packet::PrintReqState::printLabels(), gem5::X86ISA::X86StaticInst::printMem(), gem5::ArmISA::ArmStaticInst::printMemSymbol(), gem5::ArmISA::ArmStaticInst::printMiscReg(), gem5::X86ISA::X86StaticInst::printMnemonic(), gem5::SparcISA::SparcStaticInst::printMnemonic(), gem5::X86ISA::X86StaticInst::printMnemonic(), gem5::ArmISA::MemoryImm::printOffset(), gem5::ArmISA::MemoryReg::printOffset(), gem5::ArmISA::ArmStaticInst::printPFflags(), gem5::SparcISA::IntOp::printPseudoOps(), gem5::SparcISA::IntOpImm::printPseudoOps(), gem5::SparcISA::SparcStaticInst::printReg(), gem5::PowerISA::PowerStaticInst::printReg(), gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::X86StaticInst::printSegment(), gem5::ArmISA::ArmStaticInst::printTarget(), gem5::statistics::BasePrint::printUnits(), gem5::ArmISA::ArmStaticInst::printVecPredReg(), gem5::ArmISA::ArmStaticInst::printVecReg(), gem5::ArmISA::DumpStats::process(), gem5::ProtocolTester::ProtocolTester(), gem5::qemu::FwCfg::readItem(), gem5::X86ISA::FlatFloatRegClassOps::regName(), gem5::X86ISA::FlatIntRegClassOps::regName(), gem5::BaseCPU::regStats(), gem5::System::regStats(), sc_core::sc_report_compose_message(), gem5::Shader::ShaderStats::ShaderStats(), gem5::ArmISA::ArmStaticInst::shift_carry_imm(), gem5::ArmISA::ArmStaticInst::shift_carry_rs(), gem5::ArmISA::ArmStaticInst::shift_rm_imm(), gem5::ArmISA::ArmStaticInst::shift_rm_rs(), gem5::ArmISA::ArmStaticInst::shiftReg64(), gem5::ShowParam< MatStore< X, Y > >::show(), gem5::ShowParam< VecPredRegContainer< NumBits, Packed > >::show(), gem5::ShowParam< VecRegContainer< Sz > >::show(), gem5::ArmISA::Memory64::startDisassembly(), TEST(), sc_gem5::VcdTraceFile::trace(), gem5::BaseCPU::traceFunctionsInternal(), gem5::trace::ExeTracerRecord::traceInst(), and sc_gem5::VcdTraceFile::~VcdTraceFile().

ccprintf() [2/4]

template<typename T , typename ... Args>

void gem5::ccprintf	(	cp::Print &	print,
		const T &	value,
		const Args &...	args
	)

Definition at line 137 of file cprintf.hh.

References gem5::cp::Print::addArg(), and ccprintf().

ccprintf() [3/4]

template<typename ... Args>

void gem5::ccprintf	(	std::ostream &	stream,
		const char *	format,
		const Args &...	args
	)

Definition at line 146 of file cprintf.hh.

References ccprintf(), and gem5::ArmISA::format.

ccprintf() [4/4]

template<typename ... Args>

void gem5::ccprintf	(	std::ostream &	stream,
		const std::string &	format,
		const Args &...	args
	)

Definition at line 174 of file cprintf.hh.

References ccprintf(), and gem5::ArmISA::format.

change_thread_state()

void gem5::change_thread_state	(	ThreadID	tid,
		int	activate,
		int	priority
	)

Changes the status and priority of the thread with the given number.

Parameters

tid	The thread to change.
activate	The new active status.
priority	The new priority.

Definition at line 246 of file base.cc.

chdirFunc()

SyscallReturn gem5::chdirFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname
	)

Target chdir() handler.

Definition at line 916 of file syscall_emul.cc.

References gem5::Process::checkPathRedirect(), gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and startswith().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

checkSeg()

static void gem5::checkSeg ( const char *  name, const int  idx, const struct kvm_segment &  seg, struct kvm_sregs  sregs  )

static

Definition at line 430 of file x86_cpu.cc.

References gem5::X86ISA::misc_reg::Cs, gem5::X86ISA::misc_reg::Ds, gem5::X86ISA::misc_reg::Es, gem5::X86ISA::misc_reg::Fs, gem5::X86ISA::misc_reg::Gs, isCanonicalAddress(), name(), gem5::X86ISA::seg, gem5::X86ISA::misc_reg::Ss, gem5::X86ISA::misc_reg::Tr, gem5::X86ISA::misc_reg::Tsl, and warn.

chmodFunc()

template<class OS >

SyscallReturn gem5::chmodFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		mode_t	mode
	)

Target chmod() handler.

Definition at line 1271 of file syscall_emul.hh.

References gem5::ArmISA::mode.

chownFunc()

SyscallReturn gem5::chownFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		uint32_t	owner,
		uint32_t	group
	)

Target chown() handler.

Definition at line 512 of file syscall_emul.cc.

References chownImpl().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32().

chownImpl()

SyscallReturn gem5::chownImpl	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		std::string	path,
		uint32_t	owner,
		uint32_t	group
	)

Definition at line 523 of file syscall_emul.cc.

References gem5::Process::checkPathRedirect(), gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

Referenced by chownFunc(), and fchownatFunc().

clearDebugFlag()

void gem5::clearDebugFlag

(

const char *

string

)

Definition at line 199 of file debug.cc.

References gem5::debug::changeFlag().

Referenced by TEST().

clock_getresFunc()

template<class OS >

SyscallReturn gem5::clock_getresFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	clk_id,
		VPtr< typename OS::timespec >	tp
	)

Target clock_getres() function.

Definition at line 2279 of file syscall_emul.hh.

clock_gettimeFunc()

template<class OS >

SyscallReturn gem5::clock_gettimeFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	clk_id,
		VPtr< typename OS::timespec >	tp
	)

Target clock_gettime() function.

Definition at line 2265 of file syscall_emul.hh.

References getElapsedTimeNano(), htog(), and seconds_since_epoch.

clockFrequencyFixed()

bool gem5::clockFrequencyFixed

(

)

Definition at line 112 of file core.cc.

Referenced by pybind_init_core(), sc_core::sc_set_default_time_unit(), and sc_core::sc_set_time_resolution().

clone3Func()

template<class OS >

SyscallReturn gem5::clone3Func	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr< typename OS::tgt_clone_args >	cl_args,
		RegVal	size
	)

Definition at line 1864 of file syscall_emul.hh.

References flags.

cloneBackwardsFunc()

template<class OS >

SyscallReturn gem5::cloneBackwardsFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		RegVal	flags,
		RegVal	newStack,
		VPtr<>	ptidPtr,
		VPtr<>	tlsPtr,
		VPtr<>	ctidPtr
	)

Definition at line 1888 of file syscall_emul.hh.

References flags.

cloneFunc()

template<class OS >

SyscallReturn gem5::cloneFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		RegVal	flags,
		RegVal	newStack,
		VPtr<>	ptidPtr,
		VPtr<>	ctidPtr,
		VPtr<>	tlsPtr
	)

Definition at line 1880 of file syscall_emul.hh.

References flags.

closeFunc()

SyscallReturn gem5::closeFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd
	)

Target close() handler.

Definition at line 301 of file syscall_emul.cc.

References gem5::Process::fds, gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

composeBitVector()

template<class T >

uint64_t gem5::composeBitVector

(

T

vec

)

Definition at line 65 of file smbios.cc.

References gem5::X86ISA::val, and gem5::PowerISA::vec.

Referenced by gem5::X86ISA::smbios::BiosInformation::BiosInformation().

connectFunc()

SyscallReturn gem5::connectFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr<>	buf_ptr,
		int	addrlen
	)

Definition at line 1095 of file syscall_emul.cc.

References gem5::X86ISA::addr, gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and gem5::ArmISA::status.

copyOutStat64Buf()

template<typename OS , typename TgtStatPtr , typename HostStatPtr >

void gem5::copyOutStat64Buf	(	TgtStatPtr	tgt,
		HostStatPtr	host,
		bool	fakeTTY = false
	)

Definition at line 613 of file syscall_emul.hh.

References gem5::PowerISA::bo, and htog().

copyOutStatBuf()

template<typename OS , typename TgtStatPtr , typename HostStatPtr >

void gem5::copyOutStatBuf	(	TgtStatPtr	tgt,
		HostStatPtr	host,
		bool	fakeTTY = false
	)

Definition at line 564 of file syscall_emul.hh.

References gem5::PowerISA::bo, and htog().

copyOutStatfsBuf()

template<class OS , typename TgtStatPtr , typename HostStatPtr >

void gem5::copyOutStatfsBuf	(	TgtStatPtr	tgt,
		HostStatPtr	host
	)

Definition at line 635 of file syscall_emul.hh.

References gem5::PowerISA::bo, and htog().

copyOutStatxBuf()

template<typename OS , typename TgtStatPtr , typename HostStatPtr >

void gem5::copyOutStatxBuf	(	TgtStatPtr	tgt,
		HostStatPtr	host,
		bool	fakeTTY = false
	)

Definition at line 675 of file syscall_emul.hh.

References gem5::PowerISA::bo, and htog().

copyStringArray()

template<class AddrType >

void gem5::copyStringArray	(	std::vector< std::string > &	strings,
		AddrType	array_ptr,
		AddrType	data_ptr,
		const ByteOrder	bo,
		PortProxy &	memProxy
	)

Definition at line 43 of file process_impl.hh.

References gem5::PowerISA::bo, htog(), gem5::ArmISA::i, gem5::PortProxy::writeBlob(), and gem5::PortProxy::writeString().

Referenced by gem5::MipsProcess::argsInit(), gem5::PowerProcess::argsInit(), gem5::SparcProcess::argsInit(), gem5::ArmProcess::argsInit(), and gem5::X86ISA::X86Process::argsInit().

cprintf() [1/2]

template<typename ... Args>

void gem5::cprintf	(	const char *	format,
		const Args &...	args
	)

Definition at line 155 of file cprintf.hh.

References ccprintf(), and gem5::ArmISA::format.

Referenced by gem5::debug::breakpoint(), gem5::EventQueue::debugVerify(), sc_core::sc_report_handler::default_handler(), gem5::ActivityRecorder::dump(), gem5::o3::DependencyGraph< DynInstPtr >::dump(), gem5::o3::DynInst::dump(), gem5::o3::StoreSet::dump(), gem5::branch_prediction::BPredUnit::dump(), gem5::PCEventQueue::dump(), gem5::Event::dump(), gem5::EventQueue::dump(), gem5::Checker< DynInstPtr >::dumpAndExit(), gem5::o3::Rename::dumpHistory(), gem5::Checker< DynInstPtr >::dumpInsts(), gem5::o3::CPU::dumpInsts(), gem5::o3::InstructionQueue::dumpInsts(), gem5::o3::LSQUnit::dumpInsts(), gem5::o3::InstructionQueue::dumpLists(), gem5::o3::MemDepUnit::dumpLists(), fixClockFrequency(), gem5::EmbeddedPyBind::init(), main(), gem5::CPUProgressEvent::process(), and gem5::o3::InstructionQueue::~InstructionQueue().

cprintf() [2/2]

template<typename ... Args>

void gem5::cprintf	(	const std::string &	format,
		const Args &...	args
	)

Definition at line 180 of file cprintf.hh.

References ccprintf(), and gem5::ArmISA::format.

createImgWriter()

std::unique_ptr< ImgWriter > gem5::createImgWriter	(	enums::ImageFormat	type,
		const FrameBuffer *	fb
	)

Factory Function which allocates a ImgWriter object and returns a smart pointer to it.

The dynamic type of the object being pointed depends upon the enum type passed as a first parameter. If the enum contains an invalid value, the function will produce a warning and will default to Bitamp.

Parameters

type	Image writer type (e.g. Bitamp, Png)
fb	Pointer to a FrameBuffer object This contains the raw data which will be stored as an image when calling the appropriate object method

Returns

smart pointer to the allocated Image Writer

Definition at line 53 of file imgwriter.cc.

References gem5::ArmISA::fb, gem5::X86ISA::type, and warn.

Referenced by gem5::VncInput::setFrameBuffer().

csprintf() [1/2]

template<typename ... Args>

std::string gem5::csprintf	(	const char *	format,
		const Args &...	args
	)

Definition at line 161 of file cprintf.hh.

References ccprintf(), and gem5::ArmISA::format.

Referenced by gem5::TracingExtension::add(), gem5::fastmodel::PL330::allocateIrq(), gem5::SMMUv3DeviceInterface::atsRecvAtomic(), gem5::SMMUv3DeviceInterface::atsRecvTimingReq(), gem5::statistics::Text::beginGroup(), gem5::CxxConfigManager::bindObjectPorts(), gem5::CxxConfigManager::bindPort(), gem5::CxxConfigManager::bindRequestPort(), gem5::BaseSemihosting::callTmpNam(), gem5::SpatterGen::checkForSimExit(), gem5::CoherentXBar::CoherentXBar(), gem5::MemChecker::completeRead(), gem5::ComputeUnit::ComputeUnitStats::ComputeUnitStats(), gem5::fastmodel::ScxEvsCortexR52< Types >::CorePins::CorePins(), gem5::Linux::cpuOnline(), csprintf(), gem5::statistics::DataWrap< Derived, InfoProxyType >::DataWrap(), gem5::ArmISA::PMU::CounterState::debugCounter(), gem5::trace::CapstoneDisassembler::disassemble(), gem5::Pl111::dmaDone(), sc_core::sc_in_resolved::end_of_elaboration(), sc_core::sc_inout_resolved::end_of_elaboration(), sc_gem5::Module::endOfElaboration(), gem5::Linux::etcPasswd(), gem5::EtherSwitch::EtherSwitch(), gem5::CxxConfigManager::findObject(), gem5::CxxConfigManager::findObjectParams(), gem5::CxxConfigManager::findObjectType(), gem5::trace::TarmacTracerRecordV8::TraceRegEntryV8::formatReg(), gem5::UnknownOp::generateDisassembly(), gem5::McrMrcMiscInst::generateDisassembly(), gem5::McrMrcImplDefined::generateDisassembly(), gem5::UnknownOp64::generateDisassembly(), gem5::MiscRegImplDefined64::generateDisassembly(), gem5::DecoderFaultInst::generateDisassembly(), gem5::FailUnimplemented::generateDisassembly(), gem5::WarnUnimplemented::generateDisassembly(), gem5::PowerISA::MemOp::generateDisassembly(), gem5::RiscvISA::MemFenceMicro::generateDisassembly(), gem5::RiscvISA::Unknown::generateDisassembly(), gem5::SparcISA::FailUnimplemented::generateDisassembly(), gem5::SparcISA::WarnUnimplemented::generateDisassembly(), getEventQueue(), gem5::CxxConfigManager::getObject(), gem5::fastmodel::CortexR52::getPort(), gem5::fastmodel::GIC::getPort(), gem5::ArmSigInterruptPinGen::getPort(), gem5::RiscvISA::CmMacroInst::getRlistStr(), gem5::fastmodel::SignalReceiverInt::getSignalOut(), gem5::fastmodel::GIC::GIC(), gem5::X86ISA::I8042::I8042(), gem5::X86ISA::I82094AA::I82094AA(), gem5::X86ISA::I8254::I8254(), gem5::X86ISA::I8259::I8259(), gem5::o3::MemDepUnit::init(), gem5::o3::LSQUnit::init(), sc_gem5::VcdTraceFile::initialize(), gem5::Event::instanceString(), gem5::RiscvISA::Interrupts::Interrupts(), gem5::ArmISA::ArmFault::invoke64(), gem5::SMMUTranslationProcess::issuePrefetch(), gem5::ruby::MachineIDToString(), gem5::CopyEngine::CopyEngineChannel::name(), gem5::ruby::PerfectSwitch::name(), gem5::ruby::Throttle::name(), gem5::SimpleThread::name(), gem5::PciHost::DeviceInterface::name(), gem5::memory::DRAMInterface::Rank::name(), gem5::Event::name(), gem5::System::Threads::Thread::name(), gem5::NoncoherentXBar::NoncoherentXBar(), operator<<(), sc_gem5::VcdTraceScope::output(), gem5::ruby::Profiler::ProfilerStats::PerMachineTypeStats::PerMachineTypeStats(), gem5::ruby::Profiler::ProfilerStats::PerRequestTypeMachineTypeStats::PerRequestTypeMachineTypeStats(), gem5::ruby::Profiler::ProfilerStats::PerRequestTypeStats::PerRequestTypeStats(), gem5::fastmodel::PL330::PL330(), gem5::BaseTags::print(), gem5::SMMUEvent::print(), gem5::compression::DictionaryCompressor< T >::Pattern::print(), gem5::ReplaceableEntry::print(), gem5::ArmISA::TlbEntry::print(), gem5::CacheEntry::print(), gem5::branch_prediction::BTBEntry::print(), gem5::CacheBlk::print(), gem5::FALRUBlk::print(), gem5::SectorSubBlk::print(), gem5::SectorBlk::print(), gem5::CompressionBlk::print(), gem5::SuperBlk::print(), gem5::TaggedEntry::print(), gem5::trace::TarmacTracerRecord::TraceInstEntry::print(), gem5::trace::TarmacTracerRecordV8::TraceInstEntryV8::print(), gem5::Linux::procMeminfo(), gem5::ruby::Profiler::ProfilerStats::ProfilerStats(), gem5::ProtocolTester::ProtocolTester(), gem5::Serializable::ScopedCheckpointSection::pushName(), gem5::HDLcd::pxlFrameDone(), gem5::SMMUv3DeviceInterface::recvAtomic(), gem5::SMMUv3DeviceInterface::recvTimingReq(), gem5::RegClassOps::regName(), gem5::VecElemRegClassOps< ValueType >::regName(), gem5::ruby::garnet::GarnetNetwork::regStats(), gem5::ruby::SimpleNetwork::regStats(), gem5::ruby::Switch::regStats(), gem5::TrafficGen::resolveFile(), gem5::RiscvRTC::RTC::RTC(), gem5::ruby::RubyPort::RubyPort(), gem5::tlm::chi::TlmGenerator::Transaction::Expectation::run(), gem5::fastmodel::SCGIC::SCGIC(), gem5::ScheduleStage::ScheduleStageStats::ScheduleStageStats(), gem5::ScoreboardCheckStage::ScoreboardCheckStageStats::ScoreboardCheckStageStats(), gem5::fastmodel::ScxEvsCortexA76< Types >::ScxEvsCortexA76(), gem5::fastmodel::ScxEvsCortexR52< Types >::ScxEvsCortexR52(), gem5::BaseSemihosting::semiExit(), gem5::BaseRemoteGDB::send(), gem5::EtherSwitch::Interface::PortFifo::serialize(), gem5::ArmISA::PMU::serialize(), gem5::BaseSemihosting::serialize(), gem5::SparcISA::TLB::serialize(), gem5::X86ISA::TLB::serialize(), gem5::BaseCPU::serialize(), gem5::FlashDevice::serialize(), gem5::GenericTimer::serialize(), gem5::GicV2::serialize(), gem5::Gicv3::serialize(), gem5::CpuLocalTimer::serialize(), gem5::VGic::serialize(), gem5::DistIface::RecvScheduler::serialize(), gem5::IGbE::DescCache< T >::serialize(), gem5::sinic::Device::serialize(), gem5::CopyEngine::serialize(), gem5::PciDevice::serialize(), gem5::Iob::serialize(), gem5::VirtIODeviceBase::serialize(), gem5::EmulationPageTable::serialize(), gem5::memory::PhysicalMemory::serialize(), gem5::FDArray::serialize(), gem5::MemPools::serialize(), gem5::MemState::serialize(), gem5::System::serialize(), gem5::loader::SymbolTable::serialize(), gem5::EtherLink::Link::serialize(), gem5::PacketFifo::serialize(), gem5::CheckpointIn::setDir(), gem5::CxxConfigManager::setParam(), gem5::CxxConfigManager::setParamVector(), gem5::SimpleCache::SimpleCache(), gem5::statistics::Text::statName(), gem5::statistics::ScalarProxy< Stat >::str(), gem5::statistics::ConstVectorNode< T >::str(), gem5::statistics::SumNode< Op >::str(), gem5::statistics::BinaryNode< Op >::str(), gem5::ruby::Throttle::ThrottleStats::ThrottleStats(), gem5::AddrRange::to_string(), gem5::statistics::units::Rate< T1, T2 >::toString(), gem5::BaseCPU::traceFunctionsInternal(), gem5::tlm::chi::transactionToString(), gem5::EtherSwitch::Interface::PortFifo::unserialize(), gem5::ArmISA::PMU::unserialize(), gem5::BaseSemihosting::unserialize(), gem5::SparcISA::TLB::unserialize(), gem5::X86ISA::TLB::unserialize(), gem5::BaseCPU::unserialize(), gem5::FlashDevice::unserialize(), gem5::GenericTimer::unserialize(), gem5::GicV2::unserialize(), gem5::Gicv3::unserialize(), gem5::CpuLocalTimer::unserialize(), gem5::VGic::unserialize(), gem5::DistIface::RecvScheduler::unserialize(), gem5::IGbE::DescCache< T >::unserialize(), gem5::sinic::Device::unserialize(), gem5::CopyEngine::unserialize(), gem5::PciDevice::unserialize(), gem5::Iob::unserialize(), gem5::VirtIODeviceBase::unserialize(), gem5::EmulationPageTable::unserialize(), gem5::memory::PhysicalMemory::unserialize(), gem5::MemPools::unserialize(), gem5::MemState::unserialize(), gem5::System::unserialize(), gem5::FDArray::unserialize(), gem5::EtherLink::Link::unserialize(), gem5::PacketFifo::unserialize(), gem5::loader::SymbolTable::unserialize(), gem5::TypedRegClassOps< ValueType >::valString(), sc_core::wait(), gem5::WalkCache::WalkCacheStats::WalkCacheStats(), gem5::X86IdeController::X86IdeController(), and gem5::X86ISA::Cmos::X86RTC::X86RTC().

csprintf() [2/2]

template<typename ... Args>

std::string gem5::csprintf	(	const std::string &	format,
		const Args &...	args
	)

Definition at line 186 of file cprintf.hh.

References csprintf(), and gem5::ArmISA::format.

curEventQueue() [1/2]

EventQueue * gem5::curEventQueue ( )

inline

Definition at line 91 of file eventq.hh.

References _curEventQueue.

Referenced by abortHandler(), gem5::BaseGlobalEvent::deschedule(), doSimLoop(), gem5::BaseGlobalEvent::BarrierEvent::globalBarrier(), gem5::DistIface::RecvScheduler::init(), gem5::BaseKvmCPU::kvmRun(), gem5::GlobalSyncEvent::BarrierEvent::process(), gem5::DistIface::SyncEvent::process(), gem5::DistIface::RecvScheduler::pushPacket(), pybind_init_event(), gem5::DistIface::recvThreadFunc(), gem5::SyscallDesc::setupRetry(), and gem5::BaseKvmCPU::tick().

curEventQueue() [2/2]

void gem5::curEventQueue ( EventQueue *  q )

inline

Definition at line 972 of file eventq.hh.

curTick()

Tick gem5::curTick ( )

inline

The universal simulation clock.

Definition at line 46 of file cur_tick.hh.

References gem5::Gem5Internal::_curTickPtr.

Referenced by gem5::DmaPort::abortPending(), gem5::prefetch::SBOOE::access(), gem5::prefetch::SBOOE::Sandbox::access(), gem5::memory::DRAMSim2::accessAndRespond(), gem5::memory::DRAMsim3::accessAndRespond(), gem5::memory::MemCtrl::accessAndRespond(), gem5::FlashDevice::accessDevice(), gem5::SimpleCache::accessTiming(), gem5::FlashDevice::actionComplete(), gem5::o3::ThreadContext::activate(), gem5::SimpleThread::activate(), gem5::o3::CPU::activateContext(), gem5::o3::ElasticTrace::addDepTraceRecord(), gem5::ruby::CacheMemory::allocate(), gem5::BaseTrafficGen::allocateWaitingRespSlot(), gem5::ruby::garnet::SwitchAllocator::arbitrate_inports(), gem5::ruby::garnet::SwitchAllocator::arbitrate_outports(), gem5::o3::Fetch::buildInst(), gem5::memory::NVMInterface::burstReady(), gem5::BaseXBar::calcPacketTiming(), gem5::DistIface::RecvScheduler::calcReceiveTick(), gem5::BaseCache::calculateAccessLatency(), gem5::prefetch::SBOOE::calculatePrefetch(), gem5::ruby::garnet::NetworkInterface::calculateVC(), gem5::BaseSemihosting::callClock(), gem5::BaseSemihosting::callElapsed32(), gem5::BaseSemihosting::callElapsed64(), gem5::BaseSemihosting::callTime(), gem5::VncInput::captureFrameBuffer(), gem5::sinic::Device::changeConfig(), gem5::TraceCPU::checkAndSchedExitEvent(), gem5::TesterThread::checkDeadlock(), gem5::ruby::UncoalescedTable::checkDeadlock(), gem5::FlashDevice::checkDrain(), gem5::memory::DRAMInterface::Rank::checkDrainDone(), gem5::SpatterGen::checkForSimExit(), gem5::memory::DRAMInterface::checkRefreshState(), gem5::ruby::garnet::NetworkInterface::checkReschedule(), gem5::ruby::garnet::NetworkInterface::checkStallQueue(), gem5::IGbE::chkInterrupt(), gem5::memory::MemCtrl::chooseNextFRFCFS(), gem5::memory::NVMInterface::chooseRead(), gem5::BaseCache::CacheResponsePort::clearBlocked(), gem5::UFSHostDevice::clearInterrupt(), gem5::Intel8254Timer::Counter::CounterEvent::clocksLeft(), gem5::minor::Execute::commit(), gem5::o3::Commit::commitHead(), gem5::ruby::GPUCoalescer::completeHitCallback(), gem5::MemTest::completeRequest(), gem5::o3::LSQUnit::completeStore(), gem5::SMMUTranslationProcess::completeTransaction(), gem5::memory::DRAMInterface::Rank::computeStats(), gem5::PowerState::computeStats(), gem5::SDMAEngine::copyDone(), gem5::NSGigE::cpuInterrupt(), gem5::sinic::Base::cpuInterrupt(), gem5::NSGigE::cpuIntrPost(), gem5::sinic::Base::cpuIntrPost(), gem5::IGbE::cpuPostInt(), gem5::CPUProgressEvent::CPUProgressEvent(), gem5::Request::createMemManagement(), gem5::TraceCPU::dcacheRetryRecvd(), gem5::o3::Decode::decodeInsts(), gem5::PacketQueue::deferredPacketReady(), gem5::MSHR::delay(), gem5::prefetch::BOP::delayQueueEventWrapper(), gem5::memory::CfiMemory::dequeue(), gem5::memory::SimpleMemory::dequeue(), gem5::ruby::MessageBuffer::dequeue(), gem5::NSGigE::devIntrChangeMask(), gem5::sinic::Device::devIntrChangeMask(), gem5::NSGigE::devIntrPost(), gem5::sinic::Device::devIntrPost(), gem5::Linux::devRandom(), gem5::GPUDispatcher::dispatch(), gem5::o3::IEW::dispatchInsts(), gem5::GPUCommandProcessor::dispatchKernelObject(), gem5::Shader::dispatchWorkgroups(), gem5::Pl111::dmaDone(), gem5::DmaVirtDevice::dmaVirt(), gem5::SMMUProcess::doBroadcastSignal(), gem5::memory::DRAMInterface::doBurstAccess(), gem5::memory::NVMInterface::doBurstAccess(), gem5::IdeDisk::doDmaDataRead(), gem5::IdeDisk::doDmaDataWrite(), gem5::IdeDisk::doDmaRead(), gem5::IdeDisk::doDmaTransfer(), gem5::IdeDisk::doDmaWrite(), gem5::ArmISA::TableWalker::doL1DescriptorWrapper(), gem5::ArmISA::TableWalker::doL2DescriptorWrapper(), gem5::ArmISA::TableWalker::doLongDescriptorWrapper(), gem5::SMMUProcess::doSemaphoreUp(), doSimLoop(), gem5::ThermalModel::doStep(), gem5::ruby::StoreTrace::downgrade(), gem5::memory::HeteroMemCtrl::drain(), gem5::memory::MemCtrl::drain(), gem5::BaseKvmCPU::drainResume(), gem5::PCEventQueue::dump(), gem5::EventQueue::dump(), gem5::trace::TarmacParserRecord::dump(), gem5::CheckerCPU::dumpAndExit(), gem5::Checker< gem5::RefCountingPtr >::dumpInsts(), gem5::EtherDump::dumpPacket(), gem5::pseudo_inst::dumpresetstats(), gem5::pseudo_inst::dumpstats(), gem5::LdsState::earliestReturnTime(), gem5::RegisterFileCache::enqCacheInsertEvent(), gem5::RegisterFile::enqRegBusyEvent(), gem5::RegisterFile::enqRegFreeEvent(), gem5::EtherSwitch::Interface::enqueue(), gem5::TraceGen::enter(), gem5::Event::Event(), gem5::GPUDispatcher::exec(), gem5::GlobalMemPipeline::exec(), gem5::Shader::execScheduledAdds(), gem5::TraceCPU::ElasticDataGen::execute(), exitSimLoop(), gem5::o3::Fetch::fetch(), gem5::IGbE::DescCache< T >::fetchDescriptors(), gem5::IGbE::DescCache< T >::fetchDescriptors1(), gem5::o3::ElasticTrace::fetchReqTrace(), gem5::GoodbyeObject::fillBuffer(), gem5::UFSHostDevice::finalUTP(), gem5::AssociativeCache< Entry >::findVictim(), gem5::minor::LSQ::SplitDataRequest::finish(), gem5::o3::Fetch::finishTranslation(), gem5::ArmISA::flattenIntRegModeIndex(), gem5::ruby::garnet::NetworkInterface::flitisizeMessage(), gem5::memory::DRAMInterface::Rank::flushCmdList(), gem5::compression::FrequentValues::generateCodes(), gem5::CacheBlk::getAge(), getElapsedTimeMicro(), getElapsedTimeNano(), gem5::Queue< Entry >::getNext(), gem5::BaseCache::getNextQueueEntry(), gem5::prefetch::Multi::getPacket(), gem5::PowerState::getWeights(), gem5::MipsISA::haltThread(), gem5::RiscvISA::ISA::handleLockedWrite(), gem5::Checker< DynInstPtr >::handlePendingInt(), gem5::MemTraceProbe::handleRequest(), gem5::DmaPort::handleResp(), gem5::ArmISA::TableWalker::Port::handleResp(), gem5::GUPSGen::handleResponse(), gem5::ComputeUnit::DataPort::handleResponse(), gem5::SimpleCache::handleResponse(), gem5::MSHR::handleSnoop(), gem5::BaseCache::handleTimingReqHit(), gem5::X86ISA::GpuTLB::handleTranslationReturn(), gem5::VegaISA::GpuTLB::handleTranslationReturn(), gem5::ruby::garnet::OutputUnit::has_credit(), gem5::ruby::garnet::OutputUnit::has_free_vc(), gem5::DmaThread::hitCallback(), gem5::GpuWavefront::hitCallback(), gem5::ruby::RubyPort::MemResponsePort::hitCallback(), gem5::RubyDirectedTester::hitCallback(), gem5::TraceCPU::icacheRetryRecvd(), gem5::ruby::AbstractController::incomingTransactionEnd(), gem5::ruby::AbstractController::incomingTransactionStart(), increaseTick(), gem5::ruby::garnet::NetworkInterface::incrementStats(), gem5::ComputeUnit::injectGlobalMemFence(), gem5::ScalarMemPipeline::injectScalarMemFence(), gem5::prefetch::Queued::insert(), gem5::BaseTags::insertBlock(), gem5::AssociativeCache< Entry >::insertEntry(), gem5::prefetch::BOP::insertIntoDelayQueue(), gem5::GPUComputeDriver::ioctl(), gem5::minor::Execute::issue(), gem5::ruby::RubyPrefetcherProxy::issuePrefetch(), gem5::ruby::VIPERCoalescer::issueRequest(), gem5::GlobalMemPipeline::issueRequest(), gem5::LocalMemPipeline::issueRequest(), gem5::ruby::Sequencer::issueRequest(), gem5::X86ISA::GpuTLB::issueTLBLookup(), gem5::VegaISA::GpuTLB::issueTLBLookup(), gem5::EtherSwitch::Interface::learnSenderAddr(), gem5::memory::qos::MemCtrl::logRequest(), gem5::memory::qos::MemCtrl::logResponse(), gem5::EtherSwitch::Interface::lookupDestPort(), gem5::UFSHostDevice::LUNSignal(), gem5::LupioRTC::lupioRTCRead(), gem5::LupioTMR::lupioTMRCurrentTime(), gem5::LupioTMR::lupioTMRSet(), gem5::LupioTMR::lupioTMRWrite(), gem5::pseudo_inst::m5checkpoint(), gem5::pseudo_inst::m5exit(), gem5::pseudo_inst::m5fail(), gem5::SMMUTranslationProcess::main(), gem5::ruby::GPUCoalescer::makeRequest(), gem5::ruby::RubySystem::memWriteback(), gem5::memory::DRAMInterface::minBankPrep(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::nb_transport_bw(), gem5::TraceCPU::FixedRetryGen::nextExecute(), gem5::HybridGen::nextPacketTick(), gem5::LinearGen::nextPacketTick(), gem5::RandomGen::nextPacketTick(), gem5::StridedGen::nextPacketTick(), gem5::TraceGen::nextPacketTick(), gem5::Shader::notifyCuSleep(), gem5::prefetch::SBOOE::notifyFill(), gem5::GPUDispatcher::notifyWgCompl(), gem5::BaseXBar::Layer< SrcType, DstType >::occupyLayer(), gem5::free_bsd::onUDelay(), gem5::linux::onUDelay(), gem5::Linux::openSpecialFile(), gem5::CacheBlk::operator=(), gem5::ruby::AbstractController::outgoingTransactionEnd(), gem5::ruby::AbstractController::outgoingTransactionStart(), gem5::DistIface::packetOut(), gem5::ArmISA::TableWalker::pendingChange(), gem5::DVFSHandler::perfLevel(), gem5::statistics::periodicStatDump(), gem5::IGbE::RxDescCache::pktComplete(), gem5::IGbE::TxDescCache::pktComplete(), gem5::DistIface::RecvScheduler::popPacket(), gem5::IGbE::postInterrupt(), gem5::BaseSimpleCPU::preExecute(), gem5::statistics::AvgStor::prepare(), gem5::statistics::AvgSampleStor::prepare(), gem5::trace::TarmacTracerRecord::TraceInstEntry::print(), gem5::trace::TarmacTracerRecord::TraceRegEntry::print(), gem5::trace::TarmacTracerRecord::TraceMemEntry::print(), gem5::trace::TarmacTracerRecordV8::TraceInstEntryV8::print(), gem5::trace::TarmacTracerRecordV8::TraceRegEntryV8::print(), gem5::trace::TarmacTracerRecordV8::TraceMemEntryV8::print(), gem5::trace::TarmacParserRecord::printMismatchHeader(), gem5::CPUProgressEvent::process(), gem5::MC146818::RTCEvent::process(), gem5::MC146818::RTCTickEvent::process(), gem5::GlobalSyncEvent::process(), gem5::GlobalSimLoopExitEvent::process(), gem5::statistics::StatEvent::process(), gem5::DistIface::SyncEvent::process(), gem5::ArmISA::DumpStats::process(), gem5::linux::PanicOrOopsEvent::process(), gem5::memory::DRAMInterface::Rank::processActivateEvent(), gem5::HelloObject::processEvent(), gem5::Uart8250::processIntrEvent(), gem5::ComputeUnit::DataPort::processMemRespEvent(), gem5::SpatterGen::processNextGenEvent(), gem5::memory::qos::MemSinkCtrl::processNextReqEvent(), gem5::memory::MemCtrl::processNextReqEvent(), gem5::SpatterGen::processNextSendEvent(), gem5::memory::DRAMInterface::Rank::processPowerEvent(), gem5::memory::DRAMInterface::Rank::processPrechargeEvent(), gem5::TLBCoalescer::processProbeTLBEvent(), gem5::memory::NVMInterface::processReadReadyEvent(), gem5::memory::DRAMInterface::Rank::processRefreshEvent(), gem5::memory::MemCtrl::processRespondEvent(), gem5::EtherLink::Link::processTxQueue(), gem5::memory::DRAMInterface::Rank::processWakeUpEvent(), gem5::ArmISA::TableWalker::processWalk(), gem5::ArmISA::TableWalker::processWalkAArch64(), gem5::ArmISA::TableWalker::processWalkLPAE(), gem5::ArmISA::TableWalker::processWalkWrapper(), gem5::memory::NVMInterface::processWriteRespondEvent(), gem5::MSHR::promoteDeferredTargets(), gem5::Plic::propagateOutput(), gem5::memory::MemCtrl::pruneBurstTick(), gem5::memory::HBMCtrl::pruneColBurstTick(), gem5::memory::HBMCtrl::pruneRowBurstTick(), gem5::MemChecker::ByteTracker::pruneTransactions(), gem5::SDMAEngine::ptePdeDone(), gem5::EtherSwitch::Interface::PortFifo::push(), gem5::PowerDomain::pwrStateChangeCallback(), pybind_init_core(), gem5::memory::qos::MemCtrl::qosSchedule(), gem5::pseudo_inst::quiesceNs(), gem5::RegisterBank< BankByteOrder >::read(), gem5::o3::LSQUnit::read(), gem5::PL031::read(), gem5::RealViewCtrl::read(), gem5::CpuLocalTimer::Timer::read(), gem5::Sp804::Timer::read(), gem5::UFSHostDevice::readCallback(), gem5::memory::DRAMSim2::readComplete(), gem5::AMDGPUDevice::readConfig(), gem5::Pl111::readFramebuffer(), gem5::CheckerCPU::readMem(), gem5::X86ISA::Interrupts::readReg(), gem5::ruby::CHIGenericController::receiveAllRdyMessages(), gem5::o3::ElasticTrace::recordExecTick(), gem5::ruby::Sequencer::recordMissLatency(), gem5::o3::ElasticTrace::recordToCommTick(), gem5::BaseCache::recvAtomic(), gem5::TLBCoalescer::MemSidePort::recvReqRetry(), gem5::VegaTLBCoalescer::MemSidePort::recvReqRetry(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvTimingReq(), gem5::StubSlavePort::recvTimingReq(), gem5::TLBCoalescer::CpuSidePort::recvTimingReq(), gem5::VegaTLBCoalescer::CpuSidePort::recvTimingReq(), gem5::memory::CfiMemory::recvTimingReq(), gem5::CommMonitor::recvTimingReq(), gem5::MemCheckerMonitor::recvTimingReq(), gem5::memory::MemCtrl::recvTimingReq(), gem5::memory::qos::MemSinkCtrl::recvTimingReq(), gem5::ruby::RubyPort::MemResponsePort::recvTimingReq(), gem5::memory::SimpleMemory::recvTimingReq(), gem5::SimpleTimingPort::recvTimingReq(), gem5::memory::HBMCtrl::recvTimingReq(), gem5::memory::HeteroMemCtrl::recvTimingReq(), gem5::MemDelay::ResponsePort::recvTimingReq(), gem5::X86ISA::GpuTLB::MemSidePort::recvTimingResp(), gem5::VegaISA::GpuTLB::MemSidePort::recvTimingResp(), gem5::SpatterGen::recvTimingResp(), gem5::BaseTrafficGen::recvTimingResp(), gem5::ComputeUnit::DTLBPort::recvTimingResp(), gem5::BaseCache::recvTimingResp(), gem5::CommMonitor::recvTimingResp(), gem5::MemCheckerMonitor::recvTimingResp(), gem5::ruby::AbstractController::recvTimingResp(), gem5::ruby::RubyPort::MemRequestPort::recvTimingResp(), gem5::ruby::RubyPort::PioRequestPort::recvTimingResp(), gem5::ComputeUnit::ScalarDTLBPort::recvTimingResp(), gem5::MemDelay::RequestPort::recvTimingResp(), gem5::CoherentXBar::recvTimingResp(), gem5::NoncoherentXBar::recvTimingResp(), gem5::MemDelay::ResponsePort::recvTimingSnoopResp(), gem5::CoherentXBar::recvTimingSnoopResp(), gem5::o3::ElasticTrace::regEtraceListeners(), gem5::o3::ElasticTrace::regProbeListeners(), gem5::UFSHostDevice::requestHandler(), gem5::ruby::ALUFreeListArray::reserve(), gem5::ruby::BankedArray::reserve(), gem5::replacement_policy::BIP::reset(), gem5::replacement_policy::LRU::reset(), gem5::replacement_policy::MRU::reset(), gem5::statistics::AvgStor::reset(), gem5::Clocked::resetClock(), gem5::memory::DRAMInterface::Rank::resetStats(), gem5::memory::DRAMInterface::DRAMStats::resetStats(), gem5::Root::RootStats::resetStats(), gem5::pseudo_inst::resetstats(), gem5::memory::DRAMInterface::respondEvent(), gem5::Sp804::Timer::restartCounter(), gem5::Sp805::restartCounter(), gem5::CpuLocalTimer::Timer::restartTimerCounter(), gem5::CpuLocalTimer::Timer::restartWatchdogCounter(), gem5::MipsISA::restoreThread(), gem5::statistics::AvgStor::result(), gem5::BasePixelPump::PixelEvent::resume(), gem5::DistIface::RecvScheduler::resumeRecvTicks(), gem5::SMMUTranslationProcess::resumeTransaction(), gem5::PL031::resyncMatch(), gem5::EtherTapBase::retransmit(), gem5::BaseTrafficGen::retryReq(), gem5::Root::RootStats::RootStats(), gem5::pseudo_inst::rpns(), gem5::ruby::HTMSequencer::rubyHtmCallback(), gem5::DistIface::SyncNode::run(), gem5::DistIface::SyncSwitch::run(), gem5::NSGigE::rxKick(), gem5::sinic::Device::rxKick(), gem5::CommMonitor::samplePeriodic(), gem5::HSAPacketProcessor::schedAQLProcessing(), gem5::TraceCPU::schedIcacheNext(), schedRelBreak(), gem5::PacketQueue::schedSendEvent(), gem5::PacketQueue::schedSendTiming(), gem5::Shader::ScheduleAdd(), gem5::GPUDispatcher::scheduleDispatch(), gem5::MC146818::RTCEvent::scheduleIntr(), gem5::Uart8250::scheduleIntr(), gem5::SpatterGen::scheduleNextGenEvent(), gem5::ruby::garnet::NetworkInterface::scheduleOutputPort(), gem5::memory::DRAMInterface::Rank::schedulePowerEvent(), gem5::o3::InstructionQueue::scheduleReadyInsts(), gem5::BaseTrafficGen::scheduleUpdate(), gem5::GPUComputeDriver::DriverWakeupEvent::scheduleWakeup(), gem5::memory::DRAMInterface::Rank::scheduleWakeUpEvent(), gem5::HWScheduler::schedWakeup(), gem5::ruby::garnet::OutputUnit::select_free_vc(), gem5::Iris::ThreadContext::semihostingEvent(), gem5::EtherBus::send(), gem5::ruby::garnet::SwitchAllocator::send_allowed(), gem5::tlm::chi::CacheController::sendCompAck(), gem5::tlm::chi::CacheController::sendDataMsg(), gem5::ComputeUnit::sendInvL2(), gem5::ruby::CHIGenericController::sendMessage(), gem5::X86ISA::IntRequestPort< Device >::sendMessage(), gem5::GUPSGen::sendNextReq(), gem5::ComputeUnit::sendRequest(), gem5::tlm::chi::CacheController::sendRequestMsg(), gem5::memory::DRAMSim2::sendResponse(), gem5::memory::DRAMsim3::sendResponse(), gem5::tlm::chi::CacheController::sendResponseMsg(), gem5::EtherTapBase::sendSimulated(), gem5::ArmISA::TableWalker::Port::sendTimingReq(), gem5::NSGigE::serialize(), gem5::sinic::Device::serialize(), gem5::Globals::serialize(), gem5::Intel8254Timer::Counter::serialize(), gem5::MC146818::serialize(), gem5::statistics::AvgStor::set(), gem5::PowerState::set(), gem5::Request::setAccessLatency(), gem5::CheckpointIn::setDir(), gem5::Pl011::setInterrupts(), gem5::ruby::CacheMemory::setMRU(), gem5::ruby::CacheMemory::setMRU(), gem5::ruby::CacheMemory::setMRU(), gem5::X86ISA::Interrupts::setReg(), gem5::Wavefront::setStatus(), gem5::CacheBlk::setTickInserted(), gem5::Intel8254Timer::Counter::CounterEvent::setTo(), gem5::Request::setTranslateLatency(), gem5::SyscallDesc::setupRetry(), gem5::Request::setVirt(), gem5::Event::setWhen(), simulate(), gem5::SMMUTranslationProcess::smmuTranslation(), gem5::o3::Rename::sortInsts(), gem5::DistIface::SyncEvent::start(), gem5::IdeDisk::startDma(), gem5::Intel8254Timer::Counter::startup(), gem5::MC146818::startup(), gem5::BaseKvmCPU::startup(), gem5::SpatterGen::startup(), gem5::CommMonitor::startup(), gem5::memory::DRAMInterface::startup(), gem5::memory::DRAMSim2::startup(), gem5::memory::DRAMsim3::startup(), gem5::memory::HBMCtrl::startup(), gem5::memory::MemCtrl::startup(), gem5::ruby::RubySystem::startup(), gem5::ThermalModel::startup(), sc_gem5::Kernel::startup(), gem5::StatTester::startup(), gem5::memory::DRAMInterface::Rank::startup(), gem5::ruby::StoreTrace::store(), gem5::BasePixelPump::PixelEvent::suspend(), gem5::o3::ThreadContext::suspend(), gem5::SimpleThread::suspend(), takeCheckpoint(), TEST(), TEST(), TEST(), gem5::ruby::CacheMemory::testCacheAccess(), gem5::BaseKvmCPU::tick(), gem5::AtomicSimpleCPU::tick(), gem5::GarnetSyntheticTraffic::tick(), gem5::IGbE::tick(), gem5::memory::DRAMSim2::tick(), gem5::memory::DRAMsim3::tick(), timesFunc(), gem5::Root::timeSync(), gem5::Root::timeSyncEnable(), gem5::replacement_policy::LRU::touch(), gem5::replacement_policy::MRU::touch(), gem5::BaseCPU::traceFunctionsInternal(), gem5::trace::InstPBTrace::traceInst(), gem5::BaseTrafficGen::transition(), gem5::prefetch::Queued::translationComplete(), gem5::X86ISA::GpuTLB::translationReturn(), gem5::VegaISA::GpuTLB::translationReturn(), gem5::EtherSwitch::Interface::transmit(), gem5::NSGigE::transmit(), gem5::DistEtherLink::TxLink::transmit(), gem5::EtherLink::Link::transmit(), gem5::ruby::ALUFreeListArray::tryAccess(), gem5::ruby::BankedArray::tryAccess(), gem5::ruby::CacheMemory::tryCacheAccess(), gem5::Bridge::BridgeResponsePort::trySendTiming(), gem5::Bridge::BridgeRequestPort::trySendTiming(), gem5::SerialLink::SerialLinkResponsePort::trySendTiming(), gem5::SerialLink::SerialLinkRequestPort::trySendTiming(), gem5::EtherLink::Link::txDone(), gem5::NSGigE::txKick(), gem5::sinic::Device::txKick(), gem5::NSGigE::unserialize(), gem5::sinic::Device::unserialize(), gem5::BaseTrafficGen::update(), gem5::Clocked::update(), gem5::o3::ElasticTrace::updateCommitOrderDep(), gem5::statistics::updateEvents(), gem5::o3::IEW::updateExeInstStats(), gem5::GPUCommandProcessor::updateHsaEventData(), gem5::GPUCommandProcessor::updateHsaMailboxData(), gem5::VGic::updateIntState(), gem5::GicV2::updateIntState(), gem5::GPUDispatcher::updateInvCounter(), gem5::o3::ElasticTrace::updateIssueOrderDep(), gem5::X86ISA::GpuTLB::updatePageFootprint(), gem5::TLBCoalescer::updatePhysAddresses(), gem5::VegaTLBCoalescer::updatePhysAddresses(), gem5::memory::DRAMInterface::Rank::updatePowerStats(), gem5::CommMonitor::MonitorStats::updateReqStats(), gem5::SystemCounter::updateTick(), gem5::SystemCounter::updateValue(), gem5::Checker< DynInstPtr >::validateInst(), gem5::Checker< DynInstPtr >::validateState(), gem5::Checker< DynInstPtr >::verify(), gem5::HDLcd::virtRefresh(), gem5::o3::InstructionQueue::wakeDependents(), gem5::RubyDirectedTester::wakeup(), gem5::RubyTester::wakeup(), gem5::ruby::garnet::CrossbarSwitch::wakeup(), gem5::ruby::garnet::InputUnit::wakeup(), gem5::ruby::garnet::NetworkBridge::wakeup(), gem5::ruby::garnet::NetworkInterface::wakeup(), gem5::ruby::garnet::NetworkLink::wakeup(), gem5::ruby::garnet::OutputUnit::wakeup(), gem5::ruby::garnet::Router::wakeup(), gem5::ruby::GPUCoalescer::wakeup(), gem5::ArmISA::TableWalker::walk(), gem5::SystemCounter::whenValue(), gem5::System::workItemBegin(), gem5::System::workItemEnd(), gem5::RegisterBank< BankByteOrder >::write(), gem5::EnergyCtrl::write(), gem5::PL031::write(), gem5::UFSHostDevice::write(), gem5::IGbE::DescCache< T >::writeback(), gem5::IGbE::DescCache< T >::writeback1(), gem5::o3::LSQUnit::writebackStores(), gem5::memory::DRAMSim2::writeComplete(), gem5::MC146818::writeData(), gem5::UFSHostDevice::writeDevice(), gem5::SDMAEngine::writeDone(), gem5::Uart8250::writeIer(), gem5::CheckerCPU::writeMem(), gem5::AMDGPUGfx::writeMMIO(), and gem5::MipsISA::yieldThread().

cxxConfigDirectory()

std::map< std::string, CxxConfigDirectoryEntry * > & gem5::cxxConfigDirectory

(

)

Directory of all SimObject classes config details.

Definition at line 47 of file cxx_config.cc.

Referenced by gem5::CxxConfigParams::AddToConfigDir::AddToConfigDir(), and gem5::CxxConfigManager::findObjectType().

debug_serialize()

void gem5::debug_serialize

(

const std::string &

cpt_dir

)

Definition at line 189 of file sim_object.cc.

References gem5::SimObject::serializeAll().

debugDumpStats()

void gem5::debugDumpStats

(

)

Definition at line 337 of file statistics.cc.

References gem5::statistics::dump().

divideFromConf()

int gem5::divideFromConf

(

uint32_t

conf

)

Definition at line 71 of file interrupts.cc.

References gem5::ArmISA::shift.

Referenced by gem5::X86ISA::Interrupts::readReg(), and gem5::X86ISA::Interrupts::setReg().

doClone()

template<class OS >

SyscallReturn gem5::doClone	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		RegVal	flags,
		RegVal	newStack,
		VPtr<>	ptidPtr,
		VPtr<>	ctidPtr,
		VPtr<>	tlsPtr
	)

Note that ProcessParams is generated by swig and there are no other examples of how to create anything but this default constructor. The fields are manually initialized instead of passing parameters to the constructor.

Definition at line 1747 of file syscall_emul.hh.

References gem5::ThreadContext::activate(), gem5::ConstProxyPtr< T, Proxy >::addr(), gem5::Process::assignThreadContext(), gem5::BufferArg::bufferPtr(), gem5::Process::childClearTID, gem5::ThreadContext::clearArchRegs(), gem5::ThreadContext::contextId(), gem5::BaseBufferArg::copyOut(), gem5::ThreadContext::cpuId(), DPRINTF, DPRINTF_SYSCALL, fatal, gem5::System::Threads::findFree(), flags, gem5::ThreadContext::getProcessPtr(), gem5::ThreadContext::getSystemPtr(), gem5::EmulationPageTable::initState(), gem5::Process::initState(), gem5::System::maxPID, gem5::MipsISA::p, gem5::Process::pid(), gem5::Process::pTable, gem5::SyscallDesc::returnInto(), gem5::Process::revokeThreadContext(), gem5::ThreadContext::setProcessPtr(), gem5::ThreadContext::setUseForClone(), gem5::EmulationPageTable::shared, gem5::Process::sigchld, gem5::ThreadContext::suspend(), gem5::ThreadContext::threadId(), gem5::System::threads, and gem5::Process::useForClone.

doExitCleanup()

void gem5::doExitCleanup

(

)

Do C++ simulator exit processing.

Exported to Python to be invoked when simulator terminates via Python's atexit mechanism.

Definition at line 153 of file core.cc.

References exitCallbacks(), and gem5::CallbackQueue::process().

Referenced by pybind_init_core().

doSimLoop()

Event * gem5::doSimLoop

(

EventQueue *

eventq

)

forward declaration

The main per-thread simulation loop.

This loop is executed by all simulation threads (the main thread and the subordinate threads) in parallel.

Definition at line 289 of file simulate.cc.

References async_event, async_exception, async_exit, async_io, async_statdump, async_statreset, curEventQueue(), curTick(), gem5::EventQueue::empty(), exitSimLoop(), getEventQueue(), gem5::EventQueue::handleAsyncInsertions(), gem5::X86ISA::lock, gem5::EventQueue::nextTick(), pollQueue, gem5::statistics::schedStatEvent(), gem5::PollQueue::service(), and gem5::EventQueue::serviceOne().

Referenced by simulate(), and gem5::SimulatorThreads::thread_main().

dumpDebugFlags()

void gem5::dumpDebugFlags

(

std::ostream &

os

)

Definition at line 205 of file debug.cc.

References ccprintf(), gem5::ArmISA::f, gem5::ArmISA::i, and gem5::X86ISA::os.

Referenced by TEST(), and TEST().

dumpFpuCommon()

template<typename T >

static void gem5::dumpFpuCommon ( const T &  fpu )

static

Definition at line 309 of file x86_cpu.cc.

References gem5::X86ISA::BusyBit, gem5::X86ISA::CC0Bit, gem5::X86ISA::CC1Bit, gem5::X86ISA::CC2Bit, gem5::X86ISA::CC3Bit, gem5::X86ISA::DEBit, dumpFpuSpec(), gem5::X86ISA::ErrSummaryBit, gem5::ArmISA::i, gem5::X86ISA::IEBit, inform, gem5::X86ISA::loadFloat80(), gem5::X86ISA::OEBit, gem5::X86ISA::PEBit, gem5::X86ISA::StackFaultBit, gem5::X86ISA::UEBit, and gem5::X86ISA::ZEBit.

Referenced by dumpKvm(), and dumpKvm().

dumpFpuSpec() [1/2]

static void gem5::dumpFpuSpec ( const struct FXSave &  xs )

static

Definition at line 293 of file x86_cpu.cc.

References inform, and gem5::ArmISA::xs.

Referenced by dumpFpuCommon().

dumpFpuSpec() [2/2]

static void gem5::dumpFpuSpec ( const struct kvm_fpu &  fpu )

static

Definition at line 301 of file x86_cpu.cc.

References inform.

dumpKvm() [1/9]

static void gem5::dumpKvm ( const char *  reg_name, const struct kvm_dtable &  dtable  )

static

Definition at line 245 of file x86_cpu.cc.

References inform.

dumpKvm() [2/9]

static void gem5::dumpKvm ( const char *  reg_name, const struct kvm_segment &  seg  )

static

Definition at line 233 of file x86_cpu.cc.

References inform, and gem5::X86ISA::seg.

dumpKvm() [3/9]

static void gem5::dumpKvm ( const struct kvm_fpu &  fpu )

static

Definition at line 359 of file x86_cpu.cc.

References dumpFpuCommon(), and inform.

dumpKvm() [4/9]

static void gem5::dumpKvm ( const struct kvm_msrs &  msrs )

static

Definition at line 373 of file x86_cpu.cc.

References gem5::ArmISA::e, gem5::ArmISA::i, and inform.

dumpKvm() [5/9]

static void gem5::dumpKvm ( const struct kvm_regs &  regs )

static

Definition at line 217 of file x86_cpu.cc.

References FOREACH_IREG, and inform.

Referenced by gem5::X86KvmCPU::dumpDebugRegs(), gem5::X86KvmCPU::dumpFpuRegs(), gem5::X86KvmCPU::dumpIntRegs(), gem5::X86KvmCPU::dumpMSRs(), gem5::X86KvmCPU::dumpSpecRegs(), gem5::X86KvmCPU::dumpVCpuEvents(), gem5::X86KvmCPU::dumpXCRs(), and gem5::X86KvmCPU::dumpXSave().

dumpKvm() [6/9]

static void gem5::dumpKvm ( const struct kvm_sregs &  sregs )

static

Definition at line 252 of file x86_cpu.cc.

References FOREACH_DTABLE, FOREACH_SEGMENT, FOREACH_SREG, gem5::ArmISA::i, and inform.

dumpKvm() [7/9]

static void gem5::dumpKvm ( const struct kvm_vcpu_events &  events )

static

Definition at line 398 of file x86_cpu.cc.

References inform.

dumpKvm() [8/9]

static void gem5::dumpKvm ( const struct kvm_xcrs &  regs )

static

Definition at line 385 of file x86_cpu.cc.

References gem5::ArmISA::i, and inform.

dumpKvm() [9/9]

static void gem5::dumpKvm ( const struct kvm_xsave &  xsave )

static

Definition at line 366 of file x86_cpu.cc.

References dumpFpuCommon(), and inform.

dumpMainQueue()

void gem5::dumpMainQueue

(

)

Definition at line 390 of file eventq.cc.

References gem5::Event::dump(), gem5::ArmISA::i, mainEventQueue, and numMainEventQueues.

dumprstStatsHandler()

void gem5::dumprstStatsHandler

(

int

sigtype

)

Definition at line 128 of file init_signals.cc.

References async_event, async_statdump, async_statreset, getEventQueue(), and gem5::EventQueue::wakeup().

Referenced by initSignals().

dumpSimcall() [1/2]

template<typename ABI , typename Ret , typename ... Args>

std::string gem5::dumpSimcall	(	std::string	name,
		ThreadContext *	tc,
		Ret(*)(ThreadContext *, Args...)	target
	)

Definition at line 126 of file guest_abi.hh.

References name().

dumpSimcall() [2/2]

template<typename ABI , typename Ret , typename ... Args>

std::string gem5::dumpSimcall	(	std::string	name,
		ThreadContext *	tc,
		std::function< Ret(ThreadContext *, Args...)>	target = std::function<Ret(ThreadContext *, Args...)>()
	)

Definition at line 111 of file guest_abi.hh.

References gem5::guest_abi::dumpArgsFrom(), name(), gem5::guest_abi::prepareForFunction(), gem5::ArmISA::ss, and state.

Referenced by gem5::SyscallDescABI< ABI >::buildDumper(), and gem5::BaseSemihosting::SemiCallBase< Semihosting, Abi32, Abi64 >::buildDumper().

dumpStatsHandler()

void gem5::dumpStatsHandler

(

int

sigtype

)

Stats signal handler.

Definition at line 119 of file init_signals.cc.

References async_event, async_statdump, getEventQueue(), and gem5::EventQueue::wakeup().

Referenced by initSignals().

dup2Func()

SyscallReturn gem5::dup2Func	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	old_tgt_fd,
		int	new_tgt_fd
	)

Target dup2() handler.

We need a valid host file descriptor number to be able to pass into the second parameter for dup2 (newfd), but we don't know what the viable numbers are; we execute the open call to retrieve one.

Definition at line 585 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

dupFunc()

SyscallReturn gem5::dupFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd
	)

FIXME: The file description is not shared among file descriptors created with dup.

Target dup() handler.

Really, it's difficult to maintain fields like file offset or flags since an update to such a field won't be reflected in the metadata for the fd entries that we maintain for checkpoint restoration.

Definition at line 565 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

eat_end_white()

void gem5::eat_end_white ( std::string &  s )

inline

Definition at line 60 of file str.hh.

References gem5::ArmISA::s.

Referenced by eat_white(), gem5::IniFile::load(), TEST(), and TEST().

eat_lead_white()

void gem5::eat_lead_white ( std::string &  s )

inline

Definition at line 50 of file str.hh.

References gem5::ArmISA::s.

Referenced by eat_white(), TEST(), TEST(), and TEST().

eat_white()

void gem5::eat_white ( std::string &  s )

inline

Definition at line 68 of file str.hh.

References eat_end_white(), eat_lead_white(), and gem5::ArmISA::s.

Referenced by gem5::IniFile::Section::add(), gem5::IniFile::add(), gem5::IniFile::load(), gem5::pseudo_inst::loadsymbol(), and TEST().

emptyStrings()

template<typename T >

bool gem5::emptyStrings

(

const T &

labels

)

Check if all strings in a container are empty.

Definition at line 52 of file hdf5.cc.

References gem5::ArmISA::s.

Referenced by gem5::statistics::Hdf5::appendVectorInfo(), and gem5::statistics::Hdf5::visit().

EndBitUnion() [1/3]

gem5::EndBitUnion

(

IDR0

)

EndBitUnion() [2/3]

gem5::EndBitUnion

(

IRQCtrl

)

Definition at line 139 of file smmu_v3_defs.hh.

References gem5::PowerISA::cr1, data, SMMU_REG_SIZE, and SMMU_SECURE_SZ.

EndBitUnion() [3/3]

gem5::EndBitUnion

(

XStateBV

)

Definition at line 137 of file x86_cpu.cc.

References reserved.

eventfdFunc()

template<class OS >

SyscallReturn gem5::eventfdFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		unsigned	initval,
		int	in_flags
	)

Target eventfd() function.

Definition at line 2985 of file syscall_emul.hh.

References flags, gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and warnUnsupportedOS().

eventqDump()

void gem5::eventqDump

(

)

Dump all the events currently on the event queue.

Definition at line 110 of file debug.cc.

References gem5::ArmISA::i, mainEventQueue, and numMainEventQueues.

exclude() [1/2]

static AddrRangeList gem5::exclude ( const AddrRangeList &  base, AddrRangeList  to_exclude  )

inlinestatic

Definition at line 784 of file addr_range.hh.

References gem5::X86ISA::base.

Referenced by exclude(), operator-(), operator-(), TEST(), and TEST().

exclude() [2/2]

static AddrRangeList gem5::exclude ( const AddrRangeList &  base, const AddrRange &  to_exclude  )

inlinestatic

Definition at line 796 of file addr_range.hh.

References gem5::X86ISA::base, and exclude().

execveFunc()

template<class OS >

SyscallReturn gem5::execveFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		VPtr<>	argv_mem_loc,
		VPtr<>	envp_mem_loc
	)

If we were a thread created by a clone with vfork set, wake up the thread that created us

Note that ProcessParams is generated by swig and there are no other examples of how to create anything but this default constructor. The fields are manually initialized instead of passing parameters to the constructor.

Prevent process object creation with identical PIDs (which will trip a fatal check in Process constructor). The execve call is supposed to take over the currently executing process' identity but replace whatever it is doing with a new process image. Instead of hijacking the process object in the simulator, we create a new process object and bind to the previous process' thread below (hijacking the thread).

Work through the file descriptor array and close any files marked close-on-exec.

Definition at line 2347 of file syscall_emul.hh.

References gem5::ThreadContext::activate(), gem5::Process::assignThreadContext(), gem5::ArmISA::b, gem5::ThreadContext::clearArchRegs(), gem5::ThreadContext::contextId(), gem5::Process::fds, gem5::ThreadContext::getProcessPtr(), gem5::ArmISA::i, gem5::Process::init(), gem5::Process::initState(), gem5::MipsISA::p, gem5::ThreadContext::setProcessPtr(), gem5::Process::sigchld, gem5::ThreadContext::status(), gem5::ThreadContext::Suspended, and gem5::PortProxy::tryReadString().

exitCallbacks()

CallbackQueue & gem5::exitCallbacks ( )

inline

Queue of C++ callbacks to invoke on simulator exit.

Definition at line 133 of file core.cc.

Referenced by doExitCleanup(), and registerExitCallback().

exitFunc()

SyscallReturn gem5::exitFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	status
	)

Target exit() handler: terminate current context.

Definition at line 251 of file syscall_emul.cc.

References exitImpl(), and gem5::ArmISA::status.

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

exitFutexWake()

static void gem5::exitFutexWake ( ThreadContext *  tc, VPtr<>  addr, uint64_t  tgid  )

static

Definition at line 106 of file syscall_emul.cc.

References gem5::X86ISA::addr, gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyOut(), gem5::System::futexMap, gem5::ThreadContext::getSystemPtr(), and gem5::FutexMap::wakeup().

Referenced by exitImpl().

exitGroupFunc()

SyscallReturn gem5::exitGroupFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	status
	)

Target exit_group() handler: terminate simulation. (exit all threads)

Definition at line 257 of file syscall_emul.cc.

References exitImpl(), and gem5::ArmISA::status.

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), gem5::ArmISA::SyscallTable64::SyscallTable64(), and tgkillFunc().

exitImpl()

static SyscallReturn gem5::exitImpl ( SyscallDesc *  desc, ThreadContext *  tc, bool  group, int  status  )

static

Threads in a thread group require special handing. For instance, we send the SIGCHLD signal so that it appears that it came from the head of the group. We also only delete file descriptors if we are the last thread in the thread group.

Check if we share thread group with the pointer; this denotes that we are not the last thread active in the thread group. Note that setting this to false also prevents further iterations of the loop.

If p is trying to exit_group and both walk and p are in the same thread group (i.e., sharing the same tgid), we need to halt walk's thread context. After all threads except p are halted, p becomes the last thread in the group.

If p is not doing exit_group and there exists another active thread context in the group, last_thread is set to false to prevent the parent thread from killing all threads in the group.

A corner case exists which involves execve(). After execve(), the execve will enable SIGCHLD in the process. The problem occurs when the exiting process is the root process in the system; there is no parent to receive the signal. We obviate this problem by setting the root process' ppid to zero in the Python configuration files. We really should handle the root/execve specific case more gracefully.

Run though FD array of the exiting process and close all file descriptors except for the standard file descriptors. (The standard file descriptors are shared with gem5.)

If we were a thread created by a clone with vfork set, wake up the thread that created us

check to see if there is no more active thread in the system. If so, exit the simulation loop

Even though we are terminating the final thread context, dist-gem5 requires the simulation to remain active and provide synchronization messages to the switch process. So we just halt the last thread context and return. The simulation will be terminated by dist-gem5 in a coordinated manner once all nodes have signaled their readiness to exit. For non dist-gem5 simulations, readyToExit() always returns true.

Definition at line 120 of file syscall_emul.cc.

References gem5::ThreadContext::activate(), exitFutexWake(), exitSimLoop(), gem5::ThreadContext::getProcessPtr(), gem5::ThreadContext::getSystemPtr(), gem5::ThreadContext::halt(), gem5::ThreadContext::Halted, gem5::ThreadContext::Halting, gem5::ArmISA::i, gem5::MipsISA::p, gem5::Process::pid(), gem5::DistIface::readyToExit(), gem5::System::signalList, gem5::System::Threads::size(), gem5::ArmISA::status, gem5::ThreadContext::status(), gem5::ThreadContext::Suspended, gem5::X86ISA::system, gem5::System::systemList, gem5::Process::tgid(), and gem5::System::threads.

Referenced by exitFunc(), and exitGroupFunc().

exitNowHandler()

void gem5::exitNowHandler

(

int

sigtype

)

Exit signal handler.

Definition at line 139 of file init_signals.cc.

References async_event, async_exit, getEventQueue(), and gem5::EventQueue::wakeup().

Referenced by initSigInt().

exitSimLoop()

void gem5::exitSimLoop	(	const std::string &	message,
		int	exit_code = 0,
		Tick	when = curTick(),
		Tick	repeat = 0,
		bool	serialize = false
	)

Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (curTick()).

The message and exit_code parameters are saved in the SimLoopExitEvent to indicate why the exit occurred.

Definition at line 88 of file sim_events.cc.

References curTick(), serialize(), simQuantum, and warn_if.

Referenced by gem5::TraceCPU::checkAndSchedExitEvent(), gem5::ProtocolTester::checkExit(), gem5::SpatterGen::checkForSimExit(), gem5::MemTest::completeRequest(), gem5::GPUCommandProcessor::dispatchKernelObject(), doSimLoop(), gem5::trace::TarmacParserRecord::dump(), gem5::ruby::CacheRecorder::enqueueNextFetchRequest(), gem5::ruby::CacheRecorder::enqueueNextFlushRequest(), gem5::ExitGen::enter(), exitImpl(), gem5::GoodbyeObject::fillBuffer(), gem5::GUPSGen::handleResponse(), gem5::BaseCache::incMissCount(), gem5::pseudo_inst::m5checkpoint(), gem5::pseudo_inst::m5exit(), gem5::pseudo_inst::m5fail(), gem5::Shader::notifyCuSleep(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::DistIface::SyncEvent::process(), gem5::LocalSimLoopExitEvent::process(), gem5::CountedExitEvent::process(), gem5::linux::PanicOrOopsEvent::process(), pybind_init_event(), gem5::ArmISA::PMU::raiseInterrupt(), gem5::AMDGPUDevice::readConfig(), gem5::DistIface::recvThreadFunc(), gem5::BaseSemihosting::semiExit(), gem5::TCPIface::sendTCP(), gem5::ArmISA::PMU::setControlReg(), gem5::DrainManager::signalDrainDone(), gem5::pseudo_inst::switchcpu(), takeCheckpoint(), gem5::GarnetSyntheticTraffic::tick(), gem5::ComputeUnit::updateInstStats(), gem5::RubyDirectedTester::wakeup(), gem5::RubyTester::wakeup(), gem5::pseudo_inst::workbegin(), gem5::pseudo_inst::workend(), gem5::Pl011::write(), and gem5::SimpleUart::write().

exitSimLoopNow()

void gem5::exitSimLoopNow	(	const std::string &	message,
		int	exit_code,
		Tick	repeat,
		bool	serialize
	)

Schedule an event as above, but make it high priority so it runs before any normal events which are schedule at the current time.

Definition at line 99 of file sim_events.cc.

Referenced by gem5::PcCountTrackerManager::checkCount(), gem5::LooppointAnalysisManager::countBackwardBranch(), gem5::LupioSYS::lupioSYSWrite(), sc_gem5::Scheduler::pause(), sc_gem5::Scheduler::stop(), and gem5::GlobalInstTracker::updateAndCheckInstCount().

faccessatFunc()

template<class OS >

SyscallReturn gem5::faccessatFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	dirfd,
		VPtr<>	pathname,
		int	mode
	)

Target facessat() handler.

Definition at line 1046 of file syscall_emul.hh.

References accessImpl(), and gem5::ArmISA::mode.

fallocateFunc()

template<typename OS >

SyscallReturn gem5::fallocateFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		int	mode,
		typename OS::off_t	offset,
		typename OS::off_t	len
	)

Definition at line 3157 of file syscall_emul.hh.

References gem5::ThreadContext::getProcessPtr(), gem5::ArmISA::len, gem5::ArmISA::mode, gem5::ArmISA::offset, gem5::MipsISA::p, and warnUnsupportedOS().

fchmodatFunc()

template<class OS >

SyscallReturn gem5::fchmodatFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	dirfd,
		VPtr<>	pathname,
		mode_t	mode
	)

Target chmod() handler.

Definition at line 1239 of file syscall_emul.hh.

References gem5::Process::checkPathRedirect(), gem5::ThreadContext::getProcessPtr(), and gem5::ArmISA::mode.

fchmodFunc()

template<class OS >

SyscallReturn gem5::fchmodFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		uint32_t	mode
	)

Target fchmod() handler.

Definition at line 1352 of file syscall_emul.hh.

References gem5::ThreadContext::getProcessPtr(), gem5::ArmISA::mode, and gem5::MipsISA::p.

fchownatFunc()

template<class OS >

SyscallReturn gem5::fchownatFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	dirfd,
		VPtr<>	pathname,
		uint32_t	owner,
		uint32_t	group,
		int	flags
	)

Target fchownat() handler.

Definition at line 1169 of file syscall_emul.hh.

References chownImpl().

fchownFunc()

SyscallReturn gem5::fchownFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		uint32_t	owner,
		uint32_t	group
	)

Target fchown() handler.

Definition at line 540 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

fcntl64Func()

SyscallReturn gem5::fcntl64Func	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		int	cmd
	)

Target fcntl64() handler.

Definition at line 655 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and warn.

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

fcntlFunc()

SyscallReturn gem5::fcntlFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		int	cmd,
		guest_abi::VarArgs< int >	varargs
	)

Target fcntl() handler.

Definition at line 613 of file syscall_emul.cc.

References gem5::guest_abi::VarArgs< Types >::get(), gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and warn.

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

fcntlHelper() [1/2]

static int gem5::fcntlHelper ( int  fd, int  cmd  )

static

Definition at line 215 of file pollevent.cc.

References gem5::ArmISA::fd, and panic.

fcntlHelper() [2/2]

template<class ArgT >

static int gem5::fcntlHelper ( int  fd, int  cmd, ArgT  arg  )

static

Definition at line 204 of file pollevent.cc.

References gem5::ArmISA::fd, and panic.

Referenced by gem5::PollQueue::setupAsyncIO().

findLsbSet()

template<size_t N>

constexpr int gem5::findLsbSet ( std::bitset< N >  bs )

constexpr

Definition at line 382 of file bitfield.hh.

References gem5::X86ISA::bs, findLsbSet(), gem5::ArmISA::i, and gem5::ArmISA::mask.

fixClockFrequency()

void gem5::fixClockFrequency

(

)

Definition at line 84 of file core.cc.

References cprintf().

Referenced by sc_core::sc_time::from_value(), and pybind_init_core().

floatToBits() [1/2]

static uint64_t gem5::floatToBits ( double  val )

inlinestatic

Definition at line 202 of file types.hh.

References floatToBits64(), and gem5::X86ISA::val.

Referenced by gem5::guest_abi::Argument< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::get(), gem5::guest_abi::Result< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::store(), gem5::guest_abi::Result< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::store(), TEST(), and TEST().

floatToBits() [2/2]

static uint32_t gem5::floatToBits ( float  val )

inlinestatic

Definition at line 203 of file types.hh.

References floatToBits32(), and gem5::X86ISA::val.

floatToBits32()

static uint32_t gem5::floatToBits32 ( float  val )

inlinestatic

Definition at line 179 of file types.hh.

References gem5::ArmISA::f, gem5::ArmISA::i, gem5::ArmISA::u, and gem5::X86ISA::val.

Referenced by floatToBits(), TEST(), and TEST().

floatToBits64()

static uint64_t gem5::floatToBits64 ( double  val )

inlinestatic

Definition at line 191 of file types.hh.

References gem5::ArmISA::f, gem5::ArmISA::i, gem5::ArmISA::u, and gem5::X86ISA::val.

Referenced by floatToBits(), TEST(), TEST(), and updateThreadContextFPUCommon().

forceSegAccessed()

static void gem5::forceSegAccessed ( struct kvm_segment &  seg )

static

Definition at line 793 of file x86_cpu.cc.

References gem5::X86ISA::seg, and SEG_TYPE_BIT_ACCESSED.

Referenced by gem5::X86KvmCPU::updateKvmStateSRegs().

formatParamList()

static std::string gem5::formatParamList ( const std::vector< std::string > &  param_values )

static

Definition at line 111 of file cxx_manager.cc.

References gem5::ArmISA::i.

Referenced by gem5::CxxConfigManager::findObject(), gem5::CxxConfigManager::findObjectParams(), and gem5::CxxConfigManager::setParamVector().

fstat64Func()

template<class OS >

SyscallReturn gem5::fstat64Func	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr< typename OS::tgt_stat64 >	tgt_stat
	)

Target fstat64() handler.

Definition at line 1605 of file syscall_emul.hh.

References gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

fstatat64Func()

template<class OS >

SyscallReturn gem5::fstatat64Func	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	dirfd,
		VPtr<>	pathname,
		VPtr< typename OS::tgt_stat64 >	tgt_stat
	)

Target fstatat64() handler.

Definition at line 1520 of file syscall_emul.hh.

References gem5::Process::checkPathRedirect(), gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

fstatfsFunc()

template<class OS >

SyscallReturn gem5::fstatfsFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr< typename OS::tgt_statfs >	tgt_stat
	)

Target fstatfs() handler.

Definition at line 1898 of file syscall_emul.hh.

References gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

fstatFunc()

template<class OS >

SyscallReturn gem5::fstatFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr< typename OS::tgt_stat >	tgt_stat
	)

Target fstat() handler.

Definition at line 1692 of file syscall_emul.hh.

References DPRINTF_SYSCALL, gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

ftruncate64Func()

SyscallReturn gem5::ftruncate64Func	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		int64_t	length
	)

Target ftruncate64() handler.

Definition at line 482 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

ftruncateFunc()

template<typename OS >

SyscallReturn gem5::ftruncateFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		typename OS::off_t	length
	)

Target ftruncate() handler.

Definition at line 3201 of file syscall_emul.hh.

References gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

futexFunc()

template<class OS >

SyscallReturn gem5::futexFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	uaddr,
		int	op,
		int	val,
		int	timeout,
		VPtr<>	uaddr2,
		int	val3
	)

Futex system call Implemented by Daniel Sanchez Used by printf's in multi-threaded apps.

Definition at line 377 of file syscall_emul.hh.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), gem5::BaseBufferArg::copyOut(), gem5::System::futexMap, gem5::ThreadContext::getProcessPtr(), gem5::ThreadContext::getSystemPtr(), gem5::X86ISA::op, gem5::FutexMap::requeue(), gem5::FutexMap::suspend(), gem5::FutexMap::suspend_bitset(), gem5::X86ISA::val, gem5::FutexMap::wakeup(), gem5::FutexMap::wakeup_bitset(), and warn.

futimesatFunc()

template<class OS >

SyscallReturn gem5::futimesatFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	dirfd,
		VPtr<>	pathname,
		VPtr< typename OS::timeval[2]>	tp
	)

Target futimesat() handler.

Definition at line 2306 of file syscall_emul.hh.

References gem5::Process::checkPathRedirect(), gem5::ThreadContext::getProcessPtr(), gtoh(), and gem5::ArmISA::i.

GEM5_ALIGNED()

typedef gem5::GEM5_ALIGNED

(

8

)

Referenced by gem5::VegaISA::ScalarOperand< DataType, Const, NumDwords >::setBit().

genTagExtractor() [1/3]

static constexpr auto gem5::genTagExtractor ( BaseIndexingPolicy *  ip )

staticconstexpr

This helper generates an a tag extractor function object which will be typically used by Replaceable entries indexed with the BaseIndexingPolicy.

It allows to "decouple" indexing from tagging. Those entries would call the functor without directly holding a pointer to the indexing policy which should reside in the cache.

Definition at line 227 of file base.hh.

References gem5::X86ISA::addr.

genTagExtractor() [2/3]

static constexpr auto gem5::genTagExtractor ( BTBIndexingPolicy *  ip )

staticconstexpr

This helper generates a tag extractor function object which will be typically used by Replaceable entries indexed with the BaseIndexingPolicy.

It allows to "decouple" indexing from tagging. Those entries would call the functor without directly holding a pointer to the indexing policy which should reside in the cache.

Definition at line 281 of file btb_entry.hh.

References gem5::X86ISA::addr.

Referenced by gem5::prefetch::Stride::allocateNewContext(), and gem5::BaseSetAssoc::tagsInit().

genTagExtractor() [3/3]

static constexpr auto gem5::genTagExtractor ( TaggedIndexingPolicy *  ip )

staticconstexpr

This helper generates an a tag extractor function object which will be typically used by Replaceable entries indexed with the TaggedIndexingPolicy.

It allows to "decouple" indexing from tagging. Those entries would call the functor without directly holding a pointer to the indexing policy which should reside in the cache.

Definition at line 246 of file tagged_entry.hh.

References gem5::X86ISA::addr.

get_max_tick()

Tick gem5::get_max_tick

(

)

Get the maximum simulation tick.

Returns

The maximum simulation tick.

Definition at line 264 of file simulate.cc.

References MaxTick, simulate_limit_event, and gem5::BaseGlobalEvent::when().

Referenced by pybind_init_event().

getClockFrequency()

Tick gem5::getClockFrequency

(

)

Definition at line 121 of file core.cc.

Referenced by pybind_init_core().

getcpuFunc()

SyscallReturn gem5::getcpuFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr< uint32_t >	cpu,
		VPtr< uint32_t >	node,
		VPtr< uint32_t >	tcache
	)

Definition at line 1457 of file syscall_emul.cc.

References gem5::ThreadContext::contextId(), gem5::System::getGuestByteOrder(), gem5::ThreadContext::getSystemPtr(), and htog().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

getcwdFunc()

template<class OS >

SyscallReturn gem5::getcwdFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	buf_ptr,
		typename OS::size_t	size
	)

Target getcwd() handler.

Definition at line 974 of file syscall_emul.hh.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyOut(), gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

getegidFunc()

SyscallReturn gem5::getegidFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc
	)

Target getegid() handler.

Definition at line 864 of file syscall_emul.cc.

References gem5::Process::egid(), and gem5::ThreadContext::getProcessPtr().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

getElapsedTimeMicro()

template<class T1 , class T2 >

void gem5::getElapsedTimeMicro	(	T1 &	sec,
		T2 &	usec
	)

Helper function to convert current elapsed time to seconds and microseconds.

Definition at line 520 of file syscall_emul.hh.

References curTick(), and gem5::sim_clock::as_int::us.

Referenced by getrusageFunc(), gettimeofdayFunc(), and timeFunc().

getElapsedTimeNano()

template<class T1 , class T2 >

void gem5::getElapsedTimeNano	(	T1 &	sec,
		T2 &	nsec
	)

Helper function to convert current elapsed time to seconds and nanoseconds.

Definition at line 533 of file syscall_emul.hh.

References curTick(), and gem5::sim_clock::as_int::ns.

Referenced by clock_gettimeFunc().

geteuidFunc()

SyscallReturn gem5::geteuidFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc
	)

Target geteuid() handler.

Definition at line 850 of file syscall_emul.cc.

References gem5::Process::euid(), and gem5::ThreadContext::getProcessPtr().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

getEventQueue()

EventQueue * gem5::getEventQueue

(

uint32_t

index

)

Function for returning eventq queue for the provided index.

The function allocates a new queue in case one does not exist for the index, provided that the index is with in bounds.

Definition at line 62 of file eventq.cc.

References csprintf(), gem5::MipsISA::index, mainEventQueue, and numMainEventQueues.

Referenced by doSimLoop(), dumprstStatsHandler(), dumpStatsHandler(), exitNowHandler(), ioHandler(), pybind_init_event(), and gem5::PollQueue::setupAsyncIO().

getFpRound()

static RoundingMode gem5::getFpRound ( )

inline

Definition at line 45 of file fenv.cc.

References gem5::ArmISA::rm, roundOps, and gem5::RiscvISA::x.

getgidFunc()

SyscallReturn gem5::getgidFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc
	)

Target getgid() handler.

Definition at line 857 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), and gem5::Process::gid().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

gethostnameFunc()

SyscallReturn gem5::gethostnameFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	buf_ptr,
		int	name_len
	)

Target gethostname() handler.

Definition at line 338 of file syscall_emul.cc.

References hostname, and name().

getMem()

template<ByteOrder Order, class MemT >

void gem5::getMem	(	PacketPtr	pkt,
		MemT &	mem,
		trace::InstRecord *	traceData
	)

Extract the data returned from a timing mode read.

Definition at line 78 of file memhelpers.hh.

References gem5::Packet::get(), mem, and gem5::trace::InstRecord::setData().

getMemBE()

template<class MemT >

void gem5::getMemBE	(	PacketPtr	pkt,
		MemT &	mem,
		trace::InstRecord *	traceData
	)

Definition at line 94 of file memhelpers.hh.

References mem.

getMemLE()

template<class MemT >

void gem5::getMemLE	(	PacketPtr	pkt,
		MemT &	mem,
		trace::InstRecord *	traceData
	)

Definition at line 87 of file memhelpers.hh.

References mem.

getMiscRegName()

static std::string gem5::getMiscRegName ( RegIndex  index )

inlinestatic

Definition at line 72 of file ua2005.cc.

References gem5::MipsISA::index, gem5::ArmISA::miscRegName, and gem5::SparcISA::NumMiscRegs.

Referenced by gem5::SparcISA::ISA::setFSReg().

getpagesizeFunc()

SyscallReturn gem5::getpagesizeFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc
	)

Target getpagesize() handler.

Definition at line 263 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), gem5::EmulationPageTable::pageSize(), and gem5::Process::pTable.

getpeernameFunc()

SyscallReturn gem5::getpeernameFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr<>	sockAddrPtr,
		VPtr<>	addrlenPtr
	)

Definition at line 1407 of file syscall_emul.cc.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), gem5::BaseBufferArg::copyOut(), gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

getpgrpFunc()

SyscallReturn gem5::getpgrpFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc
	)

Target getpgrpFunc() handler.

Definition at line 781 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), and gem5::Process::pgid().

getpidFunc()

SyscallReturn gem5::getpidFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc
	)

Target getpid() handler.

Definition at line 822 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), and gem5::Process::tgid().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

getppidFunc()

SyscallReturn gem5::getppidFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc
	)

Target getppid() handler.

Definition at line 836 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), and gem5::Process::ppid().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

getrandomFunc()

template<typename OS >

SyscallReturn gem5::getrandomFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	buf_ptr,
		typename OS::size_t	count,
		unsigned int	flags
	)

Definition at line 3217 of file syscall_emul.hh.

References gem5::BaseBufferArg::copyOut(), gem5::X86ISA::count, gem5::Random::genRandom(), and gem5::ArmISA::i.

getrlimitFunc()

template<class OS >

SyscallReturn gem5::getrlimitFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		unsigned	resource,
		VPtr< typename OS::rlimit >	rlp
	)

Target getrlimit() handler.

Definition at line 2193 of file syscall_emul.hh.

References gem5::PowerISA::bo, gem5::ThreadContext::getSystemPtr(), htog(), gem5::System::Threads::size(), gem5::System::threads, and warn.

getrusageFunc()

template<class OS >

SyscallReturn gem5::getrusageFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	who,
		VPtr< typename OS::rusage >	rup
	)

Target getrusage() function.

Definition at line 2447 of file syscall_emul.hh.

References getElapsedTimeMicro(), htog(), and warn.

getsocknameFunc()

SyscallReturn gem5::getsocknameFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr<>	addrPtr,
		VPtr<>	lenPtr
	)

Definition at line 1368 of file syscall_emul.cc.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), gem5::BaseBufferArg::copyOut(), gem5::ThreadContext::getProcessPtr(), gem5::ArmISA::len, gem5::MipsISA::p, gem5::ArmISA::sa, and gem5::ArmISA::status.

getsockoptFunc()

SyscallReturn gem5::getsockoptFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		int	level,
		int	optname,
		VPtr<>	valPtr,
		VPtr<>	lenPtr
	)

Definition at line 1326 of file syscall_emul.cc.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyOut(), gem5::ThreadContext::getProcessPtr(), gem5::ArmISA::len, gem5::X86ISA::level, gem5::MipsISA::p, gem5::ArmISA::status, and gem5::X86ISA::val.

gettidFunc()

SyscallReturn gem5::gettidFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc
	)

Target gettid() handler.

Definition at line 829 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), and gem5::Process::pid().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

gettimeofdayFunc()

template<class OS >

SyscallReturn gem5::gettimeofdayFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr< typename OS::timeval >	tp,
		VPtr<>	tz_ptr
	)

Target gettimeofday() handler.

Definition at line 2292 of file syscall_emul.hh.

References getElapsedTimeMicro(), htog(), and seconds_since_epoch.

getuidFunc()

SyscallReturn gem5::getuidFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc
	)

Definition at line 843 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), and gem5::Process::uid().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

getUintX()

std::pair< std::uint64_t, bool > gem5::getUintX	(	const void *	buf,
		std::size_t	bytes,
		ByteOrder	endian
	)

Definition at line 41 of file bufval.cc.

References gtoh().

Referenced by gem5::Packet::getUintX(), printUintX(), TEST(), TEST(), and TEST().

gtoh()

template<typename T >

T gem5::gtoh ( T  value, ByteOrder  guest_byte_order  )

inline

Definition at line 194 of file byteswap.hh.

References betoh(), and letoh().

Referenced by amoMemAtomic(), futimesatFunc(), gem5::guest_abi::Argument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::get(), gem5::guest_abi::Argument< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::get(), getUintX(), gem5::PowerProcess::initState(), gem5::RiscvSemihosting::isSemihostingEBreak(), gem5::guest_abi::Aapcs32ArgumentBase::loadFromStack(), gem5::PowerISA::Decoder::moreBytes(), gem5::VirtQueue::VirtRing< T >::read(), gem5::PortProxy::read(), gem5::VirtQueue::VirtRing< T >::readHeader(), readMemAtomic(), readMemAtomic(), readvFunc(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::setRegs(), gem5::PowerISA::RemoteGDB::Power64GdbRegCache::setRegs(), gem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::store(), gem5::guest_abi::Result< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::store(), TEST(), gem5::VirtDescriptor::update(), writeMemAtomic(), writeMemAtomic(), and writevFunc().

htmFailureToStr() [1/2]

std::string gem5::htmFailureToStr

(

HtmCacheFailure

rc

)

Convert enum into string to be used for debug purposes.

Definition at line 60 of file htm.cc.

References FAIL_OTHER, FAIL_REMOTE, FAIL_SELF, NO_FAIL, and gem5::PowerISA::rc.

htmFailureToStr() [2/2]

std::string gem5::htmFailureToStr

(

HtmFailureFaultCause

cause

)

Convert enum into string to be used for debug purposes.

Definition at line 44 of file htm.cc.

References EXCEPTION, EXPLICIT, MEMORY, NEST, OTHER, and SIZE.

Referenced by gem5::o3::LSQUnit::completeDataAccess(), gem5::TimingSimpleCPU::completeDataAccess(), gem5::ruby::HTMSequencer::htmCallback(), gem5::ruby::HTMSequencer::HTMSequencer(), and gem5::o3::LSQUnit::writeback().

htobe()

template<typename T >

T gem5::htobe ( T  value )

inline

Definition at line 174 of file byteswap.hh.

Referenced by gem5::SparcProcess::argsInit(), gem5::VncServer::checkProtocolVersion(), gem5::VncServer::checkSecurity(), gem5::loader::ElfObject::determineOpSys(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::getRegs(), gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), gem5::SparcISA::getresuidFunc(), htog(), gem5::RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >::htoreg(), gem5::VncServer::sendFrameBufferResized(), gem5::VncServer::sendFrameBufferUpdate(), gem5::VncServer::sendServerInit(), gem5::Packet::setBE(), gem5::qemu::FwCfg::Directory::update(), and gem5::MmDisk::write().

htog()

template<typename T >

T gem5::htog ( T  value, ByteOrder  guest_byte_order  )

inline

Definition at line 187 of file byteswap.hh.

References htobe(), and htole().

Referenced by _llseekFunc(), gem5::PowerProcess::argsInit(), clock_gettimeFunc(), copyOutStat64Buf(), copyOutStatBuf(), copyOutStatfsBuf(), copyOutStatxBuf(), copyStringArray(), gem5::ArmISA::TableWalker::doL1Descriptor(), gem5::ArmISA::TableWalker::doL2Descriptor(), gem5::ArmISA::TableWalker::doLongDescriptor(), gem5::guest_abi::Argument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::get(), gem5::guest_abi::Argument< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::get(), getcpuFunc(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::getRegs(), gem5::PowerISA::RemoteGDB::Power64GdbRegCache::getRegs(), getrlimitFunc(), getrusageFunc(), gettimeofdayFunc(), gem5::VirtIOBlock::RequestQueue::onNotifyDescriptor(), prlimitFunc(), gem5::VirtIOBlock::readConfig(), gem5::VirtIOConsole::readConfig(), readvFunc(), gem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::store(), gem5::guest_abi::Result< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::store(), TEST(), timeFunc(), timesFunc(), gem5::VirtIO9PBase::VirtIO9PBase(), gem5::VirtQueue::VirtRing< T >::write(), gem5::PortProxy::write(), gem5::VirtQueue::VirtRing< T >::writeHeader(), writeMemAtomic(), writeMemAtomic(), writeMemTiming(), and writeMemTiming().

htole()

template<typename T >

T gem5::htole ( T  value )

inline

Definition at line 172 of file byteswap.hh.

References swap_byte().

Referenced by gem5::IdeController::Channel::accessBMI(), gem5::MipsProcess::argsInit(), gem5::ArmProcess::argsInit(), gem5::X86ISA::X86Process::argsInit(), gem5::ArmISA::ArmStaticInst::cSwap(), gem5::loader::ElfObject::determineOpSys(), gem5::qemu::FwCfgItemE820::FwCfgItemE820(), htog(), htop9(), gem5::RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >::htoreg(), gem5::X86ISA::FsWorkload::initState(), gem5::X86ISA::FsLinux::initState(), gem5::PciDevice::PciDevice(), gem5::PciVirtIO::PciVirtIO(), gem5::IGbE::RxDescCache::pktComplete(), gem5::X86ISA::Interrupts::read(), gem5::Packet::setLE(), gem5::PciDevice::writeConfig(), gem5::X86ISA::writeMemAtomic(), gem5::X86ISA::writeMemTiming(), gem5::X86ISA::smbios::SMBiosStructure::writeOut(), gem5::X86ISA::smbios::BiosInformation::writeOut(), gem5::X86ISA::smbios::SMBiosTable::writeOut(), writeOutField(), gem5::X86ISA::writePackedMem(), gem5::IGbE::RxDescCache::writePacket(), gem5::X86ISA::E820Table::writeTo(), and writeVal().

htop9() [1/2]

template<>

P9MsgHeader gem5::htop9 ( P9MsgHeader  v )

inline

Definition at line 85 of file fs9p.hh.

References htop9(), and gem5::ArmISA::v.

htop9() [2/2]

template<typename T >

T gem5::htop9 ( T  v )

inline

Convert host byte order to p9 byte order (LE)

Definition at line 73 of file fs9p.hh.

References htole(), and gem5::ArmISA::v.

Referenced by htop9(), gem5::VirtIO9PProxy::recvTMsg(), and gem5::VirtIO9PBase::sendRMsg().

ignore()

static void gem5::ignore ( const char *  expr )

static

Definition at line 79 of file debug.cc.

References gem5::trace::getDebugLogger(), and ignore().

Referenced by gem5::SparcISA::TLB::doMmuRegWrite(), ignore(), pybind_init_debug(), and tokenize().

ignoreFunc()

SyscallReturn gem5::ignoreFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc
	)

Handler for unimplemented syscalls that we never intend to implement (signal handling, etc.) and should not affect the correct behavior of the program.

Prints a warning. Return success to the target program.

Definition at line 84 of file syscall_emul.cc.

References gem5::SyscallDesc::name(), and warn.

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

ignoreWarnOnceFunc()

SyscallReturn gem5::ignoreWarnOnceFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc
	)

Like above, but only prints a warning once per syscall desc it's used with.

Definition at line 91 of file syscall_emul.cc.

References gem5::SyscallDesc::name(), and warn.

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

init_drain()

static void gem5::init_drain ( py::module_ &  m_native )

static

Definition at line 90 of file core.cc.

References Drained, Draining, gem5::Drainable::drainState(), gem5::DrainManager::instance(), gem5::DrainManager::isDrained(), gem5::ArmISA::m, gem5::Drainable::notifyFork(), gem5::DrainManager::preCheckpointRestore(), gem5::DrainManager::resume(), Running, gem5::DrainManager::signalDrainDone(), gem5::DrainManager::state(), and gem5::DrainManager::tryDrain().

Referenced by pybind_init_core().

init_loader()

static void gem5::init_loader ( py::module_ &  m_native )

static

Definition at line 219 of file core.cc.

References gem5::ArmISA::m, and gem5::loader::setInterpDir().

Referenced by pybind_init_core().

init_net()

static void gem5::init_net ( py::module_ &  m_native )

static

Definition at line 193 of file core.cc.

References gem5::ArmISA::m.

Referenced by pybind_init_core().

init_pc()

static void gem5::init_pc ( py::module_ &  m_native )

static

Definition at line 168 of file core.cc.

References gem5::PcCountPair::getCount(), gem5::PcCountPair::getPC(), gem5::ArmISA::m, and gem5::PcCountPair::to_string().

Referenced by pybind_init_core(), and gem5::Wavefront::start().

init_range()

static void gem5::init_range ( py::module_ &  m_native )

static

Definition at line 135 of file core.cc.

References gem5::AddrRange::end(), gem5::AddrRange::exclude(), gem5::AddrRange::granularity(), gem5::AddrRange::interleaved(), gem5::AddrRange::intersects(), gem5::AddrRange::isSubset(), gem5::ArmISA::m, gem5::AddrRange::mergesWith(), RangeEx(), RangeIn(), RangeSize(), gem5::AddrRange::size(), gem5::AddrRange::start(), gem5::AddrRange::stripes(), gem5::AddrRange::to_string(), and gem5::AddrRange::valid().

Referenced by pybind_init_core().

init_serialize()

static void gem5::init_serialize ( py::module_ &  m_native )

static

Definition at line 122 of file core.cc.

References gem5::ArmISA::m.

Referenced by pybind_init_core().

init_socket()

static void gem5::init_socket ( py::module_ &  m_native )

static

Definition at line 227 of file core.cc.

References listenSocketEmptyConfig(), listenSocketInetConfig(), listenSocketUnixAbstractConfig(), and listenSocketUnixFileConfig().

Referenced by pybind_init_core().

initiateMemAMO()

template<class XC , class MemT >

Fault gem5::initiateMemAMO	(	XC *	xc,
		trace::InstRecord *	traceData,
		Addr	addr,
		MemT &	mem,
		Request::Flags	flags,
		AtomicOpFunctor *	_amo_op
	)

Do atomic read-modify-wrote (AMO) in timing mode.

Definition at line 360 of file memhelpers.hh.

References gem5::X86ISA::addr, and flags.

initiateMemRead() [1/2]

template<class XC >

Fault gem5::initiateMemRead	(	XC *	xc,
		Addr	addr,
		std::size_t	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable
	)

Definition at line 55 of file memhelpers.hh.

References gem5::X86ISA::addr, and flags.

Referenced by initiateMemRead().

initiateMemRead() [2/2]

template<class XC , class MemT >

Fault gem5::initiateMemRead	(	XC *	xc,
		trace::InstRecord *	traceData,
		Addr	addr,
		MemT &	mem,
		Request::Flags	flags
	)

Initiate a read from memory in timing mode.

Note that the 'mem' parameter is unused; only the type of that parameter is used to determine the size of the access.

Definition at line 67 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, and initiateMemRead().

initMemReqHelper()

template<typename T , int N>

void gem5::initMemReqHelper ( GPUDynInstPtr  gpuDynInst, MemCmd  mem_req_type, bool  is_atomic = false  )

inline

Helper function for instructions declared in op_encodings.

This function takes in all of the arguments for a given memory request we are trying to initialize, then submits the request or requests depending on if the original request is aligned or unaligned.

the base address of the cache line where the the last byte of the request will be stored.

if the base cache line address of the last byte is greater than the address of the first byte then we have a misaligned access.

Definition at line 51 of file gpu_mem_helpers.hh.

References gem5::Packet::addr, gem5::Packet::dataStatic(), DPRINTF, gem5::VegaISA::NumVecElemPerVecReg(), roundDown(), and gem5::MipsISA::vaddr.

initMemReqScalarHelper()

template<typename T , int N>

void gem5::initMemReqScalarHelper ( GPUDynInstPtr  gpuDynInst, MemCmd  mem_req_type  )

inline

Helper function for scalar instructions declared in op_encodings.

This function takes in all of the arguments for a given memory request we are trying to initialize, then submits the request or requests depending on if the original request is aligned or unaligned.

the base address of the cache line where the the last byte of the request will be stored.

if the base cache line address of the last byte is greater than the address of the first byte then we have a misaligned access.

Definition at line 189 of file gpu_mem_helpers.hh.

References gem5::Packet::dataStatic(), DPRINTF, flags, gem5::Request::HAS_NO_ADDR, roundDown(), gem5::Flags< T >::set(), and gem5::MipsISA::vaddr.

initScratchReqHelper()

template<int N>

void gem5::initScratchReqHelper ( GPUDynInstPtr  gpuDynInst, MemCmd  mem_req_type  )

inline

Definition at line 134 of file gpu_mem_helpers.hh.

References gem5::Packet::dataStatic(), gem5::VegaISA::NumVecElemPerVecReg(), panic_if, roundDown(), gem5::ArmISA::stride, and gem5::MipsISA::vaddr.

initSigInt()

void gem5::initSigInt

(

)

Definition at line 221 of file init_signals.cc.

References exitNowHandler(), installSignalHandler(), and old_int_sa.

Referenced by simulate().

initSignals()

void gem5::initSignals

(

)

Definition at line 188 of file init_signals.cc.

References abortHandler(), dumprstStatsHandler(), dumpStatsHandler(), installSignalHandler(), ioHandler(), segvHandler(), setupAltStack(), and warn.

Referenced by main().

installSignalHandler()

static void gem5::installSignalHandler ( int  signal, void(*)(int sigtype)  handler, int  flags = SA_RESTART, struct sigaction *  old_sa = NULL  )

static

Definition at line 86 of file init_signals.cc.

References flags, panic, and gem5::ArmISA::sa.

Referenced by initSigInt(), and initSignals().

invalidRegClass()

constexpr RegClass gem5::invalidRegClass ( InvalidRegClass  , "invalid"  , 0  , debug::InvalidReg    )

inlineconstexpr

invokeSimcall() [1/6]

template<typename ABI , bool store_ret, typename Ret , typename ... Args>

Ret gem5::invokeSimcall	(	ThreadContext *	tc,
		Ret(*)(ThreadContext *, Args...)	target
	)

Definition at line 71 of file guest_abi.hh.

invokeSimcall() [2/6]

template<typename ABI , typename Ret , typename ... Args>

Ret gem5::invokeSimcall	(	ThreadContext *	tc,
		Ret(*)(ThreadContext *, Args...)	target
	)

Definition at line 79 of file guest_abi.hh.

invokeSimcall() [3/6]

template<typename ABI , bool store_ret, typename Ret , typename ... Args>

Ret gem5::invokeSimcall	(	ThreadContext *	tc,
		std::function< Ret(ThreadContext *, Args...)>	target
	)

Definition at line 50 of file guest_abi.hh.

References gem5::guest_abi::callFrom(), gem5::guest_abi::prepareForFunction(), and state.

Referenced by gem5::SyscallDescABI< ABI >::buildExecutor().

invokeSimcall() [4/6]

template<typename ABI , typename Ret , typename ... Args>

Ret gem5::invokeSimcall	(	ThreadContext *	tc,
		std::function< Ret(ThreadContext *, Args...)>	target
	)

Definition at line 63 of file guest_abi.hh.

invokeSimcall() [5/6]

template<typename ABI , typename ... Args>

void gem5::invokeSimcall	(	ThreadContext *	tc,
		std::function< void(ThreadContext *, Args...)>	target
	)

Definition at line 86 of file guest_abi.hh.

References gem5::guest_abi::callFrom(), gem5::guest_abi::prepareForArguments(), and state.

invokeSimcall() [6/6]

template<typename ABI , typename ... Args>

void gem5::invokeSimcall	(	ThreadContext *	tc,
		void(*)(ThreadContext *, Args...)	target
	)

Definition at line 98 of file guest_abi.hh.

ioctlFunc()

template<class OS >

SyscallReturn gem5::ioctlFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		unsigned	req,
		VPtr<>	addr
	)

Target ioctl() handler.

For the most part, programs call ioctl() only to find out if their stdout is a tty, to determine whether to do line or block buffering. We always claim that output fds are not TTYs to provide repeatable results.

For lack of a better return code, return ENOTTY. Ideally, we should return something better here, but at least we issue the warning.

Definition at line 739 of file syscall_emul.hh.

References gem5::X86ISA::addr, gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), gem5::BaseBufferArg::copyOut(), DPRINTF_SYSCALL, gem5::ThreadContext::getProcessPtr(), gem5::EmulatedDriver::ioctl(), gem5::MipsISA::p, gem5::ThreadContext::pcState(), gem5::ArmISA::status, and warn.

ioHandler()

static void gem5::ioHandler ( int  sigtype )

static

Definition at line 175 of file init_signals.cc.

References async_event, async_io, getEventQueue(), and gem5::EventQueue::wakeup().

Referenced by initSignals().

isAnyActiveElement()

bool gem5::isAnyActiveElement ( const std::vector< bool >::const_iterator &  it_start, const std::vector< bool >::const_iterator &  it_end  )

inline

Test if there is any active element in an enablement range.

Definition at line 89 of file utils.hh.

Referenced by gem5::o3::LSQ::LSQRequest::addReq(), gem5::CheckerCPU::genMemFragmentRequest(), gem5::AtomicSimpleCPU::genMemFragmentRequest(), gem5::minor::LSQ::SplitDataRequest::makeFragmentRequests(), and gem5::minor::LSQ::SingleDataRequest::startAddrTranslation().

isCanonicalAddress()

static bool gem5::isCanonicalAddress ( uint64_t  addr )

static

Definition at line 419 of file x86_cpu.cc.

References gem5::X86ISA::addr.

Referenced by checkSeg().

isRomMicroPC()

static bool gem5::isRomMicroPC ( MicroPC  upc )

inlinestatic

Definition at line 166 of file types.hh.

References MicroPCRomBit.

Referenced by gem5::TimingSimpleCPU::fetch(), gem5::o3::Fetch::fetch(), gem5::o3::Fetch::pipelineIcacheAccesses(), gem5::BaseSimpleCPU::preExecute(), TEST(), TEST(), gem5::AtomicSimpleCPU::tick(), and gem5::Checker< DynInstPtr >::verify().

KVM_REG64_TTBR0()

static const uint64_t gem5::KVM_REG64_TTBR0 ( regCp64(15, 0, 2)  )

static

Referenced by gem5::ArmKvmCPU::updateKvmStateCoProc(), and gem5::ArmKvmCPU::updateTCStateCoProc().

KVM_REG64_TTBR1()

static const uint64_t gem5::KVM_REG64_TTBR1 ( regCp64(15, 1, 2)  )

static

Referenced by gem5::ArmKvmCPU::updateKvmStateCoProc(), and gem5::ArmKvmCPU::updateTCStateCoProc().

kvmFPReg()

constexpr uint64_t gem5::kvmFPReg ( const int  num )

constexpr

Definition at line 84 of file armv8_cpu.cc.

References SIMD_REG.

Referenced by gem5::ArmV8KvmCPU::dump(), gem5::ArmV8KvmCPU::updateKvmState(), and gem5::ArmV8KvmCPU::updateThreadContext().

kvmXReg()

constexpr uint64_t gem5::kvmXReg ( const int  num )

constexpr

Definition at line 77 of file armv8_cpu.cc.

References INT_REG.

Referenced by gem5::ArmV8KvmCPU::dump(), gem5::ArmV8KvmCPU::updateKvmState(), and gem5::ArmV8KvmCPU::updateThreadContext().

letobe()

template<typename T >

T gem5::letobe ( T  value )

inline

Definition at line 166 of file byteswap.hh.

References swap_byte().

Referenced by gem5::ArmISA::ArmStaticInst::cSwap(), and TEST().

letoh()

template<typename T >

T gem5::letoh ( T  value )

inline

Definition at line 173 of file byteswap.hh.

References swap_byte().

Referenced by gem5::IdeController::Channel::accessBMI(), gem5::ArmISA::ArmStaticInst::cSwap(), gem5::IdeController::dispatchAccess(), gem5::prefetch::Base::PrefetchInfo::get(), gem5::PciDevice::getAddrRanges(), gem5::Packet::getLE(), gtoh(), gem5::pseudo_inst::initParam(), gem5::PciDevice::interruptLine(), gem5::ArmISA::Decoder::moreBytes(), gem5::MipsISA::Decoder::moreBytes(), gem5::RiscvISA::Decoder::moreBytes(), gem5::X86ISA::Decoder::moreBytes(), p9toh(), gem5::X86ISA::readMemAtomic(), gem5::X86ISA::readPackedMemAtomic(), gem5::RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >::regtoh(), SafeReadSwap(), SafeWriteSwap(), gem5::MipsISA::sys_setsysinfoFunc(), gem5::trace::InstPBTrace::traceInst(), gem5::trace::ArmNativeTrace::ThreadState::update(), gem5::trace::X86NativeTrace::ThreadState::update(), gem5::X86ISA::Interrupts::write(), gem5::PciDevice::writeConfig(), gem5::X86ISA::writeMemAtomic(), gem5::X86ISA::writeMemAtomic(), and gem5::X86ISA::smbios::SMBiosTable::writeOut().

linkFunc()

SyscallReturn gem5::linkFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		VPtr<>	new_pathname
	)

Target link() handler.

Definition at line 368 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and gem5::PortProxy::tryReadString().

listenFunc()

SyscallReturn gem5::listenFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		int	backlog
	)

Definition at line 1080 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and gem5::ArmISA::status.

listenSocketEmptyConfig()

static ListenSocketConfig gem5::listenSocketEmptyConfig ( )

inlinestatic

Definition at line 137 of file socket.hh.

Referenced by init_socket(), and gem5::ListenSocketConfig::parseIni().

listenSocketInetConfig()

ListenSocketConfig gem5::listenSocketInetConfig

(

int

port

)

Definition at line 260 of file socket.cc.

References name().

Referenced by init_socket(), and gem5::ListenSocketConfig::parseIni().

listenSocketUnixAbstractConfig()

ListenSocketConfig gem5::listenSocketUnixAbstractConfig

(

std::string

path

)

Definition at line 400 of file socket.cc.

References name().

Referenced by gem5::memory::SharedMemoryServer::ListenSocketEvent::BaseShmPollEvent(), init_socket(), and gem5::ListenSocketConfig::parseIni().

listenSocketUnixFileConfig()

ListenSocketConfig gem5::listenSocketUnixFileConfig	(	std::string	dir,
		std::string	fname
	)

Definition at line 370 of file socket.cc.

References name().

Referenced by gem5::memory::SharedMemoryServer::ListenSocketEvent::BaseShmPollEvent(), init_socket(), and gem5::ListenSocketConfig::parseIni().

lseekFunc()

template<class OS >

SyscallReturn gem5::lseekFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		typename OS::off_t	offs,
		int	whence
	)

Target lseek() handler.

Definition at line 1006 of file syscall_emul.hh.

References gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

lstat64Func()

template<class OS >

SyscallReturn gem5::lstat64Func	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		VPtr< typename OS::tgt_stat64 >	tgt_stat
	)

Target lstat64() handler.

Definition at line 1661 of file syscall_emul.hh.

References gem5::Process::checkPathRedirect(), and gem5::ThreadContext::getProcessPtr().

lstatFunc()

template<class OS >

SyscallReturn gem5::lstatFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		VPtr< typename OS::tgt_stat >	tgt_stat
	)

Target lstat() handler.

Definition at line 1635 of file syscall_emul.hh.

References gem5::Process::checkPathRedirect(), and gem5::ThreadContext::getProcessPtr().

makeKvmCpuid()

static struct kvm_cpuid_entry2 gem5::makeKvmCpuid ( uint32_t  function, uint32_t  index, CpuidResult &  result, uint32_t  flags = 0  )

static

Definition at line 1504 of file x86_cpu.cc.

References gem5::ArmISA::e, flags, and gem5::MipsISA::index.

Referenced by gem5::X86KvmCPU::updateCPUID().

mappingParamIn()

template<class T >

void gem5::mappingParamIn	(	CheckpointIn &	cp,
		const char *	sectionName,
		const char *const	names[],
		T *	param,
		unsigned	size
	)

Restore mappingParamOut.

Keys missing from the checkpoint are ignored.

Definition at line 530 of file serialize.hh.

References gem5::Serializable::currentSection(), gem5::ArmISA::i, optParamIn(), gem5::X86ISA::val, and gem5::CheckpointIn::visitSection().

Referenced by TEST_F(), and TEST_F().

mappingParamOut()

template<class T >

void gem5::mappingParamOut	(	CheckpointOut &	os,
		const char *	sectionName,
		const char *const	names[],
		const T *	param,
		unsigned	size
	)

Serialize a mapping represented as two arrays: one containing names and the other containing values.

Parameters

names	array of keys
param	array of values
size	size of the names and param arrays

Definition at line 516 of file serialize.hh.

References gem5::ArmISA::i, gem5::X86ISA::os, and paramOut().

Referenced by TEST_F(), and TEST_F().

memUsage()

uint64_t gem5::memUsage

(

)

Determine the simulator process' total virtual memory usage.

Returns

Virtual memory usage in kilobytes

Definition at line 76 of file hostinfo.cc.

References procInfo().

Referenced by gem5::Root::RootStats::RootStats().

mkdiratFunc()

template<class OS >

SyscallReturn gem5::mkdiratFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	dirfd,
		VPtr<>	pathname,
		mode_t	mode
	)

Target mkdirat() handler.

Definition at line 1188 of file syscall_emul.hh.

References mkdirImpl(), and gem5::ArmISA::mode.

mkdirFunc()

SyscallReturn gem5::mkdirFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		mode_t	mode
	)

Target mkdir() handler.

Definition at line 410 of file syscall_emul.cc.

References mkdirImpl(), and gem5::ArmISA::mode.

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

mkdirImpl()

SyscallReturn gem5::mkdirImpl	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		std::string	path,
		mode_t	mode
	)

Definition at line 420 of file syscall_emul.cc.

References gem5::Process::checkPathRedirect(), gem5::ThreadContext::getProcessPtr(), gem5::ArmISA::mode, and gem5::MipsISA::p.

Referenced by mkdiratFunc(), and mkdirFunc().

mknodatFunc()

template<class OS >

SyscallReturn gem5::mknodatFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	dirfd,
		VPtr<>	pathname,
		mode_t	mode,
		dev_t	dev
	)

Target mknodat() handler.

Definition at line 1206 of file syscall_emul.hh.

References mknodImpl(), and gem5::ArmISA::mode.

mknodFunc()

SyscallReturn gem5::mknodFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		mode_t	mode,
		dev_t	dev
	)

Target mknod() handler.

Definition at line 894 of file syscall_emul.cc.

References mknodImpl(), and gem5::ArmISA::mode.

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

mknodImpl()

SyscallReturn gem5::mknodImpl	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		std::string	path,
		mode_t	mode,
		dev_t	dev
	)

Definition at line 905 of file syscall_emul.cc.

References gem5::Process::checkPathRedirect(), gem5::ThreadContext::getProcessPtr(), gem5::ArmISA::mode, and gem5::MipsISA::p.

Referenced by mknodatFunc(), and mknodFunc().

mkutctime()

time_t gem5::mkutctime

(

struct tm *

time

)

Definition at line 154 of file time.cc.

References fatal, and gem5::ArmISA::tz.

Referenced by gem5::BaseSemihosting::BaseSemihosting(), gem5::DumbTOD::DumbTOD(), and gem5::MC146818::tickClock().

mmap2Func()

template<class OS >

SyscallReturn gem5::mmap2Func	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	start,
		typename OS::size_t	length,
		int	prot,
		int	tgt_flags,
		int	tgt_fd,
		typename OS::off_t	offset
	)

Target mmap2() handler.

Definition at line 2181 of file syscall_emul.hh.

References gem5::ThreadContext::getProcessPtr(), gem5::ArmISA::offset, gem5::EmulationPageTable::pageSize(), gem5::X86ISA::prot, and gem5::Process::pTable.

mmapFunc()

template<class OS >

SyscallReturn gem5::mmapFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	start,
		typename OS::size_t	length,
		int	prot,
		int	tgt_flags,
		int	tgt_fd,
		typename OS::off_t	offset
	)

Target mmap() handler.

Maintain the symbol table for dynamic executables. The loader will call mmap to map the images into its address space and we intercept that here. We can verify that we are executing inside the loader by checking the program counter value. XXX: with multiprogrammed workloads or multi-node configurations, this will not work since there is a single global symbol table.

Not TGT_MAP_FIXED means we can start wherever we want.

If the application provides us with a hint, we should make some small amount of effort to accomodate it. Basically, we check if every single VA within the requested range is unused. If it is, we give the application the range. If not, we fall back to extending the global mmap region.

Extend global mmap region to give us some room for the app.

We only allow mappings to overwrite existing mappings if TGT_MAP_FIXED is set. Otherwise it shouldn't be a problem because we ignore the start hint if TGT_MAP_FIXED is not set.

We might already have some old VMAs mapped to this region, so make sure to clear em out!

Figure out a human-readable name for the mapping.

Setup the correct VMA for this region. The physical pages will be mapped lazily.

Definition at line 1995 of file syscall_emul.hh.

References gem5::loader::createObjectFile(), gem5::loader::debugSymbolTable, DPRINTF_SYSCALL, gem5::ThreadContext::getProcessPtr(), gem5::loader::SymbolTable::insert(), gem5::PCStateBase::instAddr(), gem5::EmulatedDriver::mmap(), gem5::ArmISA::offset, gem5::MipsISA::p, gem5::EmulationPageTable::pageSize(), gem5::ThreadContext::pcState(), gem5::X86ISA::prot, gem5::Process::pTable, roundUp(), and warn_once.

mremapFunc()

template<class OS >

SyscallReturn gem5::mremapFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	start,
		typename OS::size_t	old_length,
		typename OS::size_t	new_length,
		int	flags,
		guest_abi::VarArgs< uint64_t >	varargs
	)

Target mremap() handler.

Definition at line 1371 of file syscall_emul.hh.

References flags, gem5::guest_abi::VarArgs< Types >::get(), gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, gem5::EmulationPageTable::pageSize(), gem5::Process::pTable, roundUp(), and warn.

mulSigned()

template<typename T >

static constexpr std::pair< std::make_signed_t< T >, std::make_signed_t< T > > gem5::mulSigned ( std::make_signed_t< T >  val_a, std::make_signed_t< T >  val_b  )

staticconstexpr

Definition at line 241 of file intmath.hh.

mulSignedManual()

template<typename T >

static constexpr std::enable_if_t< sizeof(T)==sizeof(uint64_t)> gem5::mulSignedManual ( std::make_signed_t< T > &  high, std::make_signed_t< T > &  low, std::make_signed_t< T >  val_a, std::make_signed_t< T >  val_b  )

staticconstexpr

Definition at line 198 of file intmath.hh.

References high.

mulUnsigned()

template<typename T >

static constexpr std::pair< std::make_unsigned_t< T >, std::make_unsigned_t< T > > gem5::mulUnsigned ( std::make_unsigned_t< T >  val_a, std::make_unsigned_t< T >  val_b  )

staticconstexpr

Definition at line 232 of file intmath.hh.

munmapFunc()

template<typename OS >

SyscallReturn gem5::munmapFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	start,
		typename OS::size_t	length
	)

Target munmap() handler.

Definition at line 3135 of file syscall_emul.hh.

References gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and roundUp().

newfstatatFunc()

template<class OS >

SyscallReturn gem5::newfstatatFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	dirfd,
		VPtr<>	pathname,
		VPtr< typename OS::tgt_stat64 >	tgt_stat,
		int	flags
	)

Target newfstatat() handler.

Definition at line 1481 of file syscall_emul.hh.

References gem5::Process::checkPathRedirect(), flags, gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and warn_if.

newVarStruct()

template<typename Struct , typename Entry >

static auto gem5::newVarStruct ( size_t  entries )

static

Definition at line 208 of file x86_cpu.cc.

References gem5::MipsISA::p.

normalize()

static std::string gem5::normalize ( const std::string &  directory )

static

Definition at line 106 of file process.cc.

Referenced by gem5::Process::absolutePath().

normalizePath()

static std::string gem5::normalizePath ( std::string  path )

static

Definition at line 39 of file redirect_path.cc.

References startswith().

Referenced by gem5::RedirectPath::RedirectPath().

normalMicroPC()

static MicroPC gem5::normalMicroPC ( MicroPC  upc )

inlinestatic

Definition at line 160 of file types.hh.

Referenced by gem5::X86ISAInst::MicrocodeRom::fetchMicroop(), and TEST().

onKickSignal()

static void gem5::onKickSignal ( int  signo, siginfo_t *  si, void *  data  )

static

Dummy handler for KVM kick signals.

Note

This function is usually not called since the kernel doesn't seem to deliver signals when the signal is only unmasked when running in KVM. This doesn't matter though since we are only interested in getting KVM to exit, which happens as expected. See setupSignalHandler() and kvmRun() for details about KVM signal handling.

Definition at line 1234 of file base.cc.

Referenced by gem5::BaseKvmCPU::setupSignalHandler().

openatFunc()

template<class OS >

SyscallReturn gem5::openatFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_dirfd,
		VPtr<>	pathname,
		int	tgt_flags,
		int	mode
	)

Target open() handler.

Retrieve the simulated process' memory proxy and then read in the path string from that memory space into the host's working memory space.

Translate target flags into host flags. Flags exist which are not ported between architectures which can cause check failures.

If the simulated process called open or openat with AT_FDCWD specified, take the current working directory value which was passed into the process class as a Python parameter and append the current path to create a full path. Otherwise, openat with a valid target directory file descriptor has been called. If the path option, which was passed in as a parameter, is not absolute, retrieve the directory file descriptor's path and prepend it to the path passed in as a parameter. In every case, we should have a full path (which is relevant to the host) to work with after this block has been passed.

Since this is an emulated environment, we create pseudo file descriptors for device requests that have been registered with the process class through Python; this allows us to create a file descriptor for subsequent ioctl or mmap calls.

Fall through here for pass through to host devices, such as /dev/zero

We make several attempts resolve a call to open.

1) Resolve any path redirection before hand. This will set the path up with variable 'redir_path' which may contain a modified path or the original path value. This should already be done in prior code. 2) Try to handle the access using 'special_paths'. Some special_paths and files cannot be called on the host and need to be handled as special cases inside the simulator. These special_paths are handled by C++ routines to provide output back to userspace. 3) If the full path that was created above does not match any of the special cases, pass it through to the open call on the HOST to let the host open the file on our behalf. Again, the openImpl tries to USE_THE_HOST_FILESYSTEM_OPEN (with a possible redirection to the faux-filesystem files). The faux-filesystem is dynamically created during simulator configuration using Python functions. 4) If the host cannot open the file, the open attempt failed in "3)". Return the host's error code back through the system call to the simulated process. If running a debug trace, also notify the user that the open call failed.

Any success will set sim_fd to something other than -1 and skip the next conditions effectively bypassing them.

The file was opened successfully and needs to be recorded in the process' file descriptor array so that it can be retrieved later. The target file descriptor that is chosen will be the lowest unused file descriptor. Return the indirect target file descriptor back to the simulated process to act as a handle for the opened file.

Definition at line 814 of file syscall_emul.hh.

References DPRINTF_SYSCALL, gem5::ThreadContext::getProcessPtr(), gem5::RiscvISA::local, gem5::ArmISA::mode, gem5::SyscallDesc::name(), gem5::EmulatedDriver::open(), gem5::MipsISA::p, startswith(), and warn_if.

openFunc()

template<class OS >

SyscallReturn gem5::openFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		int	tgt_flags,
		int	mode
	)

Target open() handler.

Definition at line 964 of file syscall_emul.hh.

References gem5::ArmISA::mode.

operator!=() [1/5]

static bool gem5::operator!= ( const PCStateBase &  a, const PCStateBase &  b  )

inlinestatic

Definition at line 169 of file pcstate.hh.

References gem5::ArmISA::a, and gem5::ArmISA::b.

operator!=() [2/5]

template<class T >

bool gem5::operator!= ( const RefCountingPtr< T > &  l, const RefCountingPtr< T > &  r  )

inline

Check for inequality of two reference counting pointers.

Definition at line 294 of file refcnt.hh.

References gem5::MipsISA::l, and gem5::MipsISA::r.

operator!=() [3/5]

template<class T >

bool gem5::operator!= ( const RefCountingPtr< T > &  l, const T *  r  )

inline

Check for inequality of of a reference counting pointers and a regular pointer.

Definition at line 303 of file refcnt.hh.

References gem5::MipsISA::l, and gem5::MipsISA::r.

operator!=() [4/5]

template<class T >

bool gem5::operator!= ( const T *  l, const RefCountingPtr< T > &  r  )

inline

Check for inequality of of a reference counting pointers and a regular pointer.

Definition at line 312 of file refcnt.hh.

References gem5::MipsISA::l, and gem5::MipsISA::r.

operator!=() [5/5]

bool gem5::operator!= ( const Time &  l, const Time &  r  )

inline

Definition at line 213 of file time.hh.

References gem5::MipsISA::l, and gem5::MipsISA::r.

operator&()

auto gem5::operator& ( TypeTLB  lhs, TypeTLB  rhs  )

inline

Implementing the "&" bitwise operator for TypeTLB allows us to handle TypeTLB::unified efficiently.

For example if I want to check if a TLB is storing instruction entries I can do this with:

tlb->type() & TypeTLB::instruction

which will cover both TypeTLB::instruction and TypeTLB::unified TLBs

Definition at line 139 of file tlb.hh.

operator*() [1/2]

constexpr Temperature gem5::operator* ( const double &  lhs, const Temperature &  rhs  )

constexpr

Definition at line 167 of file temperature.hh.

operator*() [2/2]

constexpr Temperature gem5::operator* ( const Temperature &  lhs, const double &  rhs  )

constexpr

Definition at line 161 of file temperature.hh.

operator+() [1/3]

template<typename T , typename Proxy , typename A >

std::enable_if_t< std::is_integral_v< A >, ConstProxyPtr< T, Proxy > > gem5::operator+	(	A	a,
		const ConstProxyPtr< T, Proxy > &	other
	)

Definition at line 232 of file proxy_ptr.hh.

References gem5::ArmISA::a.

operator+() [2/3]

template<typename T , typename Proxy , typename A >

std::enable_if_t< std::is_integral_v< A >, ProxyPtr< T, Proxy > > gem5::operator+	(	A	a,
		const ProxyPtr< T, Proxy > &	other
	)

Definition at line 355 of file proxy_ptr.hh.

References gem5::ArmISA::a.

operator+() [3/3]

Time gem5::operator+ ( const Time &  l, const Time &  r  )

inline

Definition at line 247 of file time.hh.

References gem5::MipsISA::l, and gem5::MipsISA::r.

operator-() [1/5]

static AddrRangeList gem5::operator- ( const AddrRange &  range, const AddrRange &  to_exclude  )

inlinestatic

Definition at line 778 of file addr_range.hh.

References gem5::AddrRange::exclude().

operator-() [2/5]

static AddrRangeList gem5::operator- ( const AddrRange &  range, const AddrRangeList &  to_exclude  )

inlinestatic

Definition at line 772 of file addr_range.hh.

References gem5::AddrRange::exclude().

operator-() [3/5]

static AddrRangeList gem5::operator- ( const AddrRangeList &  base, const AddrRange &  to_exclude  )

inlinestatic

Definition at line 815 of file addr_range.hh.

References gem5::X86ISA::base, and exclude().

operator-() [4/5]

static AddrRangeList gem5::operator- ( const AddrRangeList &  base, const AddrRangeList &  to_exclude  )

inlinestatic

Definition at line 802 of file addr_range.hh.

References gem5::X86ISA::base, and exclude().

operator-() [5/5]

Time gem5::operator- ( const Time &  l, const Time &  r  )

inline

Definition at line 255 of file time.hh.

References gem5::MipsISA::l, and gem5::MipsISA::r.

operator-=() [1/2]

static AddrRangeList gem5::operator-= ( AddrRangeList &  base, const AddrRange &  to_exclude  )

inlinestatic

Definition at line 821 of file addr_range.hh.

References gem5::X86ISA::base.

operator-=() [2/2]

static AddrRangeList gem5::operator-= ( AddrRangeList &  base, const AddrRangeList &  to_exclude  )

inlinestatic

Definition at line 808 of file addr_range.hh.

References gem5::X86ISA::base.

operator/()

constexpr Temperature gem5::operator/ ( const Temperature &  lhs, const double &  rhs  )

constexpr

Definition at line 173 of file temperature.hh.

operator<()

bool gem5::operator< ( const Time &  l, const Time &  r  )

inline

Definition at line 218 of file time.hh.

References gem5::MipsISA::l, and gem5::MipsISA::r.

operator<<() [1/17]

std::ostream & gem5::operator<<	(	std::ostream &	os,
		const BaseSemihosting::InPlaceArg &	ipa
	)

Definition at line 876 of file semihosting.cc.

References gem5::BaseSemihosting::InPlaceArg::addr, ccprintf(), operator<<(), gem5::X86ISA::os, and gem5::BaseSemihosting::InPlaceArg::size.

Referenced by gem5::ruby::operator<<(), operator<<(), gem5::ruby::operator<<(), operator<<(), operator<<(), gem5::pseudo_inst::operator<<(), gem5::ruby::operator<<(), operator<<(), operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), operator<<(), operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::garnet::operator<<(), gem5::ruby::garnet::operator<<(), gem5::ruby::garnet::operator<<(), gem5::ruby::garnet::operator<<(), gem5::ruby::garnet::operator<<(), operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::networking::operator<<(), gem5::networking::operator<<(), gem5::networking::operator<<(), and gem5::networking::operator<<().

operator<<() [2/17]

template<typename T , typename Proxy >

std::ostream & gem5::operator<<	(	std::ostream &	os,
		const ConstProxyPtr< T, Proxy > &	vptr
	)

Definition at line 388 of file proxy_ptr.hh.

References gem5::ConstProxyPtr< T, Proxy >::addr(), ccprintf(), and gem5::X86ISA::os.

operator<<() [3/17]

static std::ostream & gem5::operator<< ( std::ostream &  os, const DummyMatRegContainer &  d  )

inlinestatic

Definition at line 563 of file matrix.hh.

References operator<<(), and gem5::X86ISA::os.

Referenced by operator<<().

operator<<() [4/17]

static std::ostream & gem5::operator<< ( std::ostream &  os, const DummyVecPredRegContainer &  d  )

inlinestatic

Definition at line 416 of file vec_pred_reg.hh.

References operator<<(), and gem5::X86ISA::os.

operator<<() [5/17]

static std::ostream & gem5::operator<< ( std::ostream &  os, const DummyVecRegContainer &  d  )

inlinestatic

Definition at line 309 of file vec_reg.hh.

References operator<<(), and gem5::X86ISA::os.

operator<<() [6/17]

static std::ostream & gem5::operator<< ( std::ostream &  os, const ListenSocket &  socket  )

inlinestatic

Definition at line 105 of file socket.hh.

References gem5::X86ISA::os, and gem5::ListenSocket::output().

operator<<() [7/17]

static std::ostream & gem5::operator<< ( std::ostream &  os, const PCStateBase &  pc  )

inlinestatic

Definition at line 155 of file pcstate.hh.

References operator<<(), gem5::X86ISA::os, and gem5::MipsISA::pc.

Referenced by operator<<().

operator<<() [8/17]

std::ostream & gem5::operator<< ( std::ostream &  os, const Pixel &  pxl  )

inline

Definition at line 227 of file pixel.hh.

References csprintf(), operator<<(), gem5::X86ISA::os, and gem5::PixelConverter::rgba8888_le.

operator<<() [9/17]

static std::ostream & gem5::operator<< ( std::ostream &  os, const Port &  port  )

inlinestatic

Definition at line 155 of file port.hh.

References gem5::Port::name(), and gem5::X86ISA::os.

operator<<() [10/17]

std::ostream & gem5::operator<<	(	std::ostream &	os,
		const RegId &	rid
	)

Definition at line 290 of file reg_class.hh.

operator<<() [11/17]

std::ostream & gem5::operator<<	(	std::ostream &	os,
		const TranslationGen::Range &	range
	)

Definition at line 54 of file translation_gen.test.cc.

References ccprintf(), dummyFault1, dummyFault2, gem5::TranslationGen::Range::fault, operator<<(), gem5::X86ISA::os, gem5::TranslationGen::Range::paddr, gem5::TranslationGen::Range::size, and gem5::TranslationGen::Range::vaddr.

operator<<() [12/17]

std::ostream & gem5::operator<< ( std::ostream &  out, const Check &  obj  )

inline

Definition at line 91 of file Check.hh.

References operator<<(), and gem5::Check::print().

operator<<() [13/17]

std::ostream & gem5::operator<< ( std::ostream &  out, const CheckTable &  obj  )

inline

Definition at line 78 of file CheckTable.hh.

References operator<<(), and gem5::CheckTable::print().

operator<<() [14/17]

std::ostream & gem5::operator<<	(	std::ostream &	out,
		const Cycles &	cycles
	)

Definition at line 34 of file types.cc.

operator<<() [15/17]

std::ostream & gem5::operator<< ( std::ostream &  out, const RubyTester &  obj  )

inline

Definition at line 157 of file RubyTester.hh.

References operator<<(), and gem5::RubyTester::print().

operator<<() [16/17]

std::ostream & gem5::operator<<	(	std::ostream &	out,
		const Temperature &	temp
	)

Definition at line 67 of file temperature.cc.

operator<<() [17/17]

std::ostream & gem5::operator<< ( std::ostream &  out, const Time &  time  )

inline

Definition at line 262 of file time.hh.

References gem5::Time::date(), and operator<<().

operator<=()

bool gem5::operator<= ( const Time &  l, const Time &  r  )

inline

Definition at line 225 of file time.hh.

References gem5::MipsISA::l, and gem5::MipsISA::r.

operator==() [1/6]

static bool gem5::operator== ( const PCStateBase &  a, const PCStateBase &  b  )

inlinestatic

Definition at line 163 of file pcstate.hh.

References gem5::ArmISA::a, and gem5::ArmISA::b.

operator==() [2/6]

bool gem5::operator== ( const Pixel &  lhs, const Pixel &  rhs  )

inline

Definition at line 73 of file pixel.hh.

References gem5::Pixel::blue, gem5::Pixel::green, gem5::Pixel::padding, and gem5::Pixel::red.

operator==() [3/6]

template<class T >

bool gem5::operator== ( const RefCountingPtr< T > &  l, const RefCountingPtr< T > &  r  )

inline

Check for equality of two reference counting pointers.

Definition at line 268 of file refcnt.hh.

References gem5::MipsISA::l, and gem5::MipsISA::r.

operator==() [4/6]

template<class T >

bool gem5::operator== ( const RefCountingPtr< T > &  l, const T *  r  )

inline

Check for equality of of a reference counting pointers and a regular pointer.

Definition at line 277 of file refcnt.hh.

References gem5::MipsISA::l, and gem5::MipsISA::r.

operator==() [5/6]

template<class T >

bool gem5::operator== ( const T *  l, const RefCountingPtr< T > &  r  )

inline

Check for equality of of a reference counting pointers and a regular pointer.

Definition at line 286 of file refcnt.hh.

References gem5::MipsISA::l, and gem5::MipsISA::r.

operator==() [6/6]

bool gem5::operator== ( const Time &  l, const Time &  r  )

inline

Definition at line 207 of file time.hh.

References gem5::MipsISA::l, and gem5::MipsISA::r.

operator>()

bool gem5::operator> ( const Time &  l, const Time &  r  )

inline

Definition at line 233 of file time.hh.

References gem5::MipsISA::l, and gem5::MipsISA::r.

operator>=()

bool gem5::operator>= ( const Time &  l, const Time &  r  )

inline

Definition at line 240 of file time.hh.

References gem5::MipsISA::l, and gem5::MipsISA::r.

output()

static void gem5::output ( const char *  filename )

static

Definition at line 60 of file debug.cc.

References gem5::OutputDirectory::create(), gem5::OutputDirectory::find(), gem5::trace::setDebugLogger(), simout, and gem5::OutputStream::stream().

Referenced by gem5::ArmISA::Crypto::aesAddRoundKey(), gem5::ArmISA::Crypto::aesDecrypt(), gem5::ArmISA::Crypto::aesEncrypt(), gem5::ArmISA::Crypto::aesInvMixColumns(), gem5::ArmISA::Crypto::aesInvShiftRows(), gem5::ArmISA::Crypto::aesInvSubBytes(), gem5::ArmISA::Crypto::aesMixColumns(), gem5::ArmISA::Crypto::aesShiftRows(), gem5::ArmISA::Crypto::aesSubBytes(), gem5::ArmISA::RemoteGDB::getXferFeaturesRead(), gem5::ArmISA::Crypto::load2Reg(), gem5::ArmISA::Crypto::load3Reg(), pybind_init_debug(), gem5::X86ISA::I8259::requestInterrupt(), reverseBits(), gem5::ArmISA::Crypto::sha1C(), gem5::ArmISA::Crypto::sha1H(), gem5::ArmISA::Crypto::sha1M(), gem5::ArmISA::Crypto::sha1Op(), gem5::ArmISA::Crypto::sha1P(), gem5::ArmISA::Crypto::sha1Su0(), gem5::ArmISA::Crypto::sha1Su1(), gem5::ArmISA::Crypto::sha256H(), gem5::ArmISA::Crypto::sha256H2(), gem5::ArmISA::Crypto::sha256Su0(), gem5::ArmISA::Crypto::sha256Su1(), gem5::ArmISA::Crypto::store1Reg(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), and TEST().

p9toh() [1/2]

template<>

P9MsgHeader gem5::p9toh ( P9MsgHeader  v )

inline

Definition at line 76 of file fs9p.hh.

References p9toh(), and gem5::ArmISA::v.

p9toh() [2/2]

template<typename T >

T gem5::p9toh ( T  v )

inline

Convert p9 byte order (LE) to host byte order.

Definition at line 69 of file fs9p.hh.

References letoh(), and gem5::ArmISA::v.

Referenced by gem5::VirtIO9PBase::FSQueue::onNotifyDescriptor(), p9toh(), and gem5::VirtIO9PProxy::serverDataReady().

paramIn() [1/2]

template<>

void gem5::paramIn	(	CheckpointIn &	cp,
		const std::string &	name,
		ExtMachInst &	machInst
	)

Definition at line 72 of file types.cc.

References gem5::X86ISA::ExtMachInst::addrSize, gem5::X86ISA::ExtMachInst::displacement, gem5::X86ISA::ExtMachInst::dispSize, gem5::X86ISA::ExtMachInst::immediate, gem5::X86ISA::ExtMachInst::legacy, gem5::X86ISA::ExtMachInst::mode, gem5::X86ISA::ExtMachInst::modRM, name(), gem5::X86ISA::ExtMachInst::op, gem5::X86ISA::ExtMachInst::opcode, gem5::X86ISA::ExtMachInst::opSize, paramIn(), gem5::X86ISA::ExtMachInst::rex, gem5::X86ISA::ExtMachInst::sib, gem5::X86ISA::ExtMachInst::stackSize, gem5::X86ISA::ExtMachInst::type, and gem5::X86ISA::ExtMachInst::vex.

Referenced by gem5::BaseSemihosting::FileBase::create(), paramIn(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), gem5::ArmISA::TlbEntry::unserialize(), gem5::ArmISA::PMU::unserialize(), gem5::BaseSemihosting::unserialize(), gem5::SparcISA::TLB::unserialize(), gem5::FlashDevice::unserialize(), gem5::ArchTimer::unserialize(), gem5::Pl050::unserialize(), gem5::Pl011::unserialize(), gem5::igbreg::Regs::unserialize(), gem5::sinic::Device::unserialize(), gem5::copy_engine_reg::Regs::unserialize(), gem5::copy_engine_reg::ChanRegs::unserialize(), gem5::PciDevice::unserialize(), gem5::Clint::unserialize(), gem5::Plic::unserialize(), gem5::Uart8250::unserialize(), gem5::Iob::unserialize(), gem5::IdeDisk::unserialize(), gem5::VirtQueue::unserialize(), gem5::X86ISA::I8237::unserialize(), gem5::MultiLevelPageTable< EntryTypes >::unserialize(), gem5::EmulationPageTable::unserialize(), gem5::Globals::unserialize(), gem5::MemPool::unserialize(), gem5::MemState::unserialize(), gem5::FDArray::unserialize(), gem5::Time::unserialize(), gem5::Intel8254Timer::Counter::unserialize(), gem5::MC146818::unserialize(), gem5::EtherLink::Link::unserialize(), gem5::EthPacketData::unserialize(), gem5::PacketFifoEntry::unserialize(), gem5::PacketFifo::unserialize(), gem5::IdeController::Channel::unserialize(), and gem5::loader::SymbolTable::unserialize().

paramIn() [2/2]

template<>

void gem5::paramIn	(	CheckpointIn &	cp,
		const std::string &	name,
		X86ISA::ExtMachInst &	machInst
	)

Definition at line 72 of file types.cc.

References gem5::X86ISA::ExtMachInst::addrSize, gem5::X86ISA::ExtMachInst::displacement, gem5::X86ISA::ExtMachInst::dispSize, gem5::X86ISA::ExtMachInst::immediate, gem5::X86ISA::ExtMachInst::legacy, gem5::X86ISA::ExtMachInst::mode, gem5::X86ISA::ExtMachInst::modRM, name(), gem5::X86ISA::ExtMachInst::op, gem5::X86ISA::ExtMachInst::opcode, gem5::X86ISA::ExtMachInst::opSize, paramIn(), gem5::X86ISA::ExtMachInst::rex, gem5::X86ISA::ExtMachInst::sib, gem5::X86ISA::ExtMachInst::stackSize, gem5::X86ISA::ExtMachInst::type, and gem5::X86ISA::ExtMachInst::vex.

Referenced by gem5::BaseSemihosting::FileBase::create(), paramIn(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), gem5::ArmISA::TlbEntry::unserialize(), gem5::ArmISA::PMU::unserialize(), gem5::BaseSemihosting::unserialize(), gem5::SparcISA::TLB::unserialize(), gem5::FlashDevice::unserialize(), gem5::ArchTimer::unserialize(), gem5::Pl050::unserialize(), gem5::Pl011::unserialize(), gem5::igbreg::Regs::unserialize(), gem5::sinic::Device::unserialize(), gem5::copy_engine_reg::Regs::unserialize(), gem5::copy_engine_reg::ChanRegs::unserialize(), gem5::PciDevice::unserialize(), gem5::Clint::unserialize(), gem5::Plic::unserialize(), gem5::Uart8250::unserialize(), gem5::Iob::unserialize(), gem5::IdeDisk::unserialize(), gem5::VirtQueue::unserialize(), gem5::X86ISA::I8237::unserialize(), gem5::MultiLevelPageTable< EntryTypes >::unserialize(), gem5::EmulationPageTable::unserialize(), gem5::Globals::unserialize(), gem5::MemPool::unserialize(), gem5::MemState::unserialize(), gem5::FDArray::unserialize(), gem5::Time::unserialize(), gem5::Intel8254Timer::Counter::unserialize(), gem5::MC146818::unserialize(), gem5::EtherLink::Link::unserialize(), gem5::EthPacketData::unserialize(), gem5::PacketFifoEntry::unserialize(), gem5::PacketFifo::unserialize(), gem5::IdeController::Channel::unserialize(), and gem5::loader::SymbolTable::unserialize().

paramInImpl()

template<class T >

bool gem5::paramInImpl	(	CheckpointIn &	cp,
		const std::string &	name,
		T &	param
	)

Definition at line 336 of file serialize.hh.

References gem5::Serializable::currentSection(), gem5::CheckpointIn::find(), and name().

Referenced by optParamIn(), and paramIn().

paramOut() [1/2]

template<>

void gem5::paramOut	(	CheckpointOut &	cp,
		const std::string &	name,
		const X86ISA::ExtMachInst &	machInst
	)

Definition at line 40 of file types.cc.

References gem5::X86ISA::ExtMachInst::addrSize, gem5::X86ISA::ExtMachInst::displacement, gem5::X86ISA::ExtMachInst::dispSize, gem5::X86ISA::ExtMachInst::immediate, gem5::X86ISA::ExtMachInst::legacy, gem5::X86ISA::ExtMachInst::mode, gem5::X86ISA::ExtMachInst::modRM, name(), gem5::X86ISA::ExtMachInst::op, gem5::X86ISA::ExtMachInst::opcode, gem5::X86ISA::ExtMachInst::opSize, paramOut(), gem5::X86ISA::ExtMachInst::rex, gem5::X86ISA::ExtMachInst::sib, gem5::X86ISA::ExtMachInst::stackSize, gem5::X86ISA::ExtMachInst::type, and gem5::X86ISA::ExtMachInst::vex.

Referenced by mappingParamOut(), paramOut(), gem5::ArmISA::TlbEntry::serialize(), gem5::BaseSemihosting::serialize(), gem5::BaseSemihosting::FileBase::serialize(), gem5::FlashDevice::serialize(), gem5::ArchTimer::serialize(), gem5::GenericTimer::serialize(), gem5::Pl050::serialize(), gem5::Pl011::serialize(), gem5::igbreg::Regs::serialize(), gem5::sinic::Device::serialize(), gem5::copy_engine_reg::Regs::serialize(), gem5::copy_engine_reg::ChanRegs::serialize(), gem5::PciDevice::serialize(), gem5::Clint::serialize(), gem5::Plic::serialize(), gem5::Uart8250::serialize(), gem5::Iob::serialize(), gem5::IdeDisk::serialize(), gem5::X86ISA::I8237::serialize(), gem5::MultiLevelPageTable< EntryTypes >::serialize(), gem5::EmulationPageTable::serialize(), gem5::FDArray::serialize(), gem5::Globals::serialize(), gem5::MemPool::serialize(), gem5::MemState::serialize(), gem5::System::serialize(), gem5::Ticked::serialize(), gem5::loader::SymbolTable::serialize(), gem5::Time::serialize(), gem5::Intel8254Timer::Counter::serialize(), gem5::MC146818::serialize(), gem5::EtherLink::Link::serialize(), gem5::EthPacketData::serialize(), gem5::PacketFifoEntry::serialize(), gem5::PacketFifo::serialize(), gem5::IdeController::Channel::serialize(), TEST_F(), TEST_F(), and TEST_F().

paramOut() [2/2]

template<>

void gem5::paramOut	(	CheckpointOut &	cp,
		const std::string &	name,
		ExtMachInst const &	machInst
	)

Definition at line 40 of file types.cc.

References gem5::X86ISA::ExtMachInst::addrSize, gem5::X86ISA::ExtMachInst::displacement, gem5::X86ISA::ExtMachInst::dispSize, gem5::X86ISA::ExtMachInst::immediate, gem5::X86ISA::ExtMachInst::legacy, gem5::X86ISA::ExtMachInst::mode, gem5::X86ISA::ExtMachInst::modRM, name(), gem5::X86ISA::ExtMachInst::op, gem5::X86ISA::ExtMachInst::opcode, gem5::X86ISA::ExtMachInst::opSize, paramOut(), gem5::X86ISA::ExtMachInst::rex, gem5::X86ISA::ExtMachInst::sib, gem5::X86ISA::ExtMachInst::stackSize, gem5::X86ISA::ExtMachInst::type, and gem5::X86ISA::ExtMachInst::vex.

Referenced by mappingParamOut(), paramOut(), gem5::ArmISA::TlbEntry::serialize(), gem5::BaseSemihosting::serialize(), gem5::BaseSemihosting::FileBase::serialize(), gem5::FlashDevice::serialize(), gem5::ArchTimer::serialize(), gem5::GenericTimer::serialize(), gem5::Pl050::serialize(), gem5::Pl011::serialize(), gem5::igbreg::Regs::serialize(), gem5::sinic::Device::serialize(), gem5::copy_engine_reg::Regs::serialize(), gem5::copy_engine_reg::ChanRegs::serialize(), gem5::PciDevice::serialize(), gem5::Clint::serialize(), gem5::Plic::serialize(), gem5::Uart8250::serialize(), gem5::Iob::serialize(), gem5::IdeDisk::serialize(), gem5::X86ISA::I8237::serialize(), gem5::MultiLevelPageTable< EntryTypes >::serialize(), gem5::EmulationPageTable::serialize(), gem5::FDArray::serialize(), gem5::Globals::serialize(), gem5::MemPool::serialize(), gem5::MemState::serialize(), gem5::System::serialize(), gem5::Ticked::serialize(), gem5::loader::SymbolTable::serialize(), gem5::Time::serialize(), gem5::Intel8254Timer::Counter::serialize(), gem5::MC146818::serialize(), gem5::EtherLink::Link::serialize(), gem5::EthPacketData::serialize(), gem5::PacketFifoEntry::serialize(), gem5::PacketFifo::serialize(), gem5::IdeController::Channel::serialize(), TEST_F(), TEST_F(), and TEST_F().

pipe2Func()

SyscallReturn gem5::pipe2Func	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	tgt_addr,
		int	flags
	)

Target pipe() handler.

Now patch the read object to record the target file descriptor chosen as the write end of the pipe.

On some architectures, it's possible to use more than one register for a return value. In those cases, pipe returns its values rather than write them into a buffer.

Copy the target file descriptors into buffer space and then copy the buffer space back into the target address space.

Definition at line 696 of file syscall_emul.cc.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyOut(), flags, gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, gem5::PipeFDEntry::read, and gem5::PipeFDEntry::write.

Referenced by pipeFunc(), and pipePseudoFunc().

pipeFunc()

SyscallReturn gem5::pipeFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	tgt_addr
	)

Target pipe() handler.

Definition at line 690 of file syscall_emul.cc.

References pipe2Func().

pipePseudoFunc()

SyscallReturn gem5::pipePseudoFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc
	)

Pseudo Funcs - These functions use a different return convension, returning a second value in a register other than the normal return register.

Definition at line 684 of file syscall_emul.cc.

References pipe2Func().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

pollFunc()

template<class OS >

SyscallReturn gem5::pollFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	fdsPtr,
		int	nfds,
		int	tmout
	)

Record the target file descriptors in a local variable. We need to replace them with host file descriptors but we need a temporary copy for later. Afterwards, replace each target file descriptor in the poll_fd array with its host_fd.

We cannot allow an infinite poll to occur or it will inevitably cause a deadlock in the gem5 simulator with clone. We must pass in tmout with a non-negative value, however it also makes no sense to poll on the underlying host for any other time than tmout a zero timeout.

If blocking indefinitely, check the signal list to see if a signal would break the poll out of the retry cycle and try to return the signal interrupt instead.

Replace each host_fd in the returned poll_fd array with its original target file descriptor.

Copy out the pollfd struct because the host may have updated fields in the structure.

Definition at line 1278 of file syscall_emul.hh.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), gem5::BaseBufferArg::copyOut(), gem5::ArmISA::fd, gem5::ThreadContext::getProcessPtr(), gem5::ThreadContext::getSystemPtr(), gem5::MipsISA::index, gem5::MipsISA::p, gem5::SyscallReturn::retry(), gem5::System::signalList, and gem5::ArmISA::status.

pread64Func()

template<class OS >

SyscallReturn gem5::pread64Func	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr<>	bufPtr,
		typename OS::size_t	nbytes,
		typename OS::off_t	offset
	)

Definition at line 2137 of file syscall_emul.hh.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyOut(), gem5::ThreadContext::getProcessPtr(), gem5::ArmISA::offset, and gem5::MipsISA::p.

print_backtrace()

void gem5::print_backtrace

(

)

Print a gem5 post-mortem report.

Note

This is usually called from a signal handler. Implementations must support this use case.

Definition at line 54 of file backtrace_glibc.cc.

References STATIC_ERR.

Referenced by abortHandler(), gem5::trace::OstreamLogger::logMessage(), and segvHandler().

printByteBuf()

std::string gem5::printByteBuf	(	const void *	buf,
		std::size_t	bytes,
		ByteOrder	endian,
		std::size_t	chunk_size
	)

Definition at line 99 of file bufval.cc.

References gem5::ArmISA::i.

Referenced by TEST(), TEST(), TEST(), and gem5::RegClassOps::valString().

printSize()

void gem5::printSize	(	std::ostream &	stream,
		size_t	size
	)

Definition at line 292 of file fa_lru.cc.

References gem5::RiscvISA::div().

Referenced by gem5::FALRU::CacheTracking::CacheTracking().

printSystems()

void gem5::printSystems

(

)

Definition at line 416 of file system.cc.

References gem5::System::printSystems().

printUintX()

std::pair< std::string, bool > gem5::printUintX	(	const void *	buf,
		std::size_t	bytes,
		ByteOrder	endian
	)

Definition at line 82 of file bufval.cc.

References getUintX(), and gem5::X86ISA::val.

Referenced by TEST(), TEST(), TEST(), and gem5::RegClassOps::valString().

prlimitFunc()

template<class OS >

SyscallReturn gem5::prlimitFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	pid,
		int	resource,
		VPtr<>	n,
		VPtr< typename OS::rlimit >	rlp
	)

Definition at line 2229 of file syscall_emul.hh.

References gem5::PowerISA::bo, htog(), gem5::ArmISA::n, and warn.

procInfo()

uint64_t gem5::procInfo	(	const char *	filename,
		const char *	target
	)

Definition at line 47 of file hostinfo.cc.

References gem5::ArmISA::format, gem5::ArmISA::fp, and startswith().

Referenced by memUsage().

pwrite64Func()

template<class OS >

SyscallReturn gem5::pwrite64Func	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr<>	bufPtr,
		typename OS::size_t	nbytes,
		typename OS::off_t	offset
	)

Definition at line 2159 of file syscall_emul.hh.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), gem5::ThreadContext::getProcessPtr(), gem5::ArmISA::offset, and gem5::MipsISA::p.

py_interact()

void gem5::py_interact

(

)

Definition at line 37 of file py_interact.cc.

pybind_init_core() [1/2]

void gem5::pybind_init_core

(

py::module_ &

m_native

)

Definition at line 241 of file core.cc.

References gem5::ListenSocket::allDisabled(), clockFrequencyFixed(), compileDate, curTick(), gem5::ListenSocket::disableAll(), doExitCleanup(), gem5::Logger::FATAL, fixClockFrequency(), gem5::Temperature::fromCelsius(), gem5::Temperature::fromFahrenheit(), gem5::Temperature::fromKelvin(), gem5Version, getClockFrequency(), gem5::Logger::HACK, gem5::Logger::INFO, init_drain(), init_loader(), init_net(), init_pc(), init_range(), init_serialize(), init_socket(), gem5::ListenSocket::loopbackOnly(), MaxTick, gem5::Logger::PANIC, pybindSimObjectResolver, gem5::Random::reseedAll(), gem5::ArmISA::s, gem5::SimObject::serializeAll(), setClockFrequency(), gem5::Logger::setLevel(), setOutputDir(), gem5::SimObject::setSimObjectResolver(), gem5::ArmISA::t, gem5::Temperature::toCelsius(), gem5::Temperature::toFahrenheit(), gem5::Temperature::toKelvin(), and gem5::Logger::WARN.

Referenced by gem5::EmbeddedPyBind::initAll().

pybind_init_core() [2/2]

void gem5::pybind_init_core

(

pybind11::module_ &

m_native

)

pybind_init_debug() [1/2]

void gem5::pybind_init_debug

(

py::module_ &

m_native

)

Definition at line 87 of file debug.cc.

References activate(), gem5::debug::allFlags(), gem5::debug::Flag::desc(), gem5::trace::disable(), gem5::debug::Flag::disable(), gem5::trace::enable(), gem5::debug::Flag::enable(), ignore(), gem5::debug::SimpleFlag::isFormat(), gem5::debug::CompoundFlag::kids(), gem5::debug::Flag::name(), output(), schedBreak(), state, gem5::debug::Flag::tracing(), and gem5::debug::AllFlagsFlag::version().

Referenced by gem5::EmbeddedPyBind::initAll().

pybind_init_debug() [2/2]

void gem5::pybind_init_debug

(

pybind11::module_ &

m_native

)

pybind_init_event() [1/2]

void gem5::pybind_init_event

(

py::module_ &

m_native

)

Definition at line 104 of file event.cc.

References curEventQueue(), gem5::EventBase::Default_Pri, gem5::EventQueue::deschedule(), gem5::Event::dump(), gem5::EventQueue::dump(), gem5::ArmISA::e, gem5::PowerISA::eq, exitSimLoop(), get_max_tick(), gem5::GlobalSimLoopExitEvent::getCause(), gem5::GlobalSimLoopExitEvent::getCode(), getEventQueue(), gem5::Event::isExitEvent(), gem5::ArmISA::m, MaxTick, gem5::Event::name(), PRIO, gem5::Event::priority(), gem5::ArmISA::q, gem5::EventQueue::reschedule(), gem5::Event::scheduled(), set_max_tick(), simulate(), gem5::Event::squash(), gem5::Event::squashed(), gem5::ArmISA::t, terminateEventQueueThreads(), and gem5::Event::when().

Referenced by gem5::EmbeddedPyBind::initAll().

pybind_init_event() [2/2]

void gem5::pybind_init_event

(

pybind11::module_ &

m_native

)

pybind_init_stats() [1/2]

void gem5::pybind_init_stats

(

py::module_ &

m_native

)

Definition at line 108 of file stats.cc.

References gem5::statistics::Group::addStatGroup(), gem5::statistics::Info::baseCheck(), gem5::statistics::Output::begin(), gem5::statistics::Output::beginGroup(), gem5::statistics::DistData::bucket_size, cast_stat_info(), gem5::statistics::Info::check(), gem5::statistics::SparseHistData::cmap, gem5::statistics::Vector2dInfo::cvec, gem5::statistics::DistData::cvec, gem5::statistics::DistInfo::data, gem5::statistics::SparseHistInfo::data, gem5::statistics::Info::desc, gem5::statistics::enable(), gem5::statistics::Info::enable(), gem5::statistics::enabled(), gem5::statistics::Output::end(), gem5::statistics::Output::endGroup(), gem5::statistics::Info::flags, gem5::statistics::Group::getStatGroups(), gem5::statistics::Group::getStats(), gem5::statistics::units::Base::getUnitString(), gem5::statistics::Info::id, gem5::statistics::initHDF5(), gem5::statistics::initSimStats(), gem5::statistics::initText(), gem5::Flags< T >::isSet(), gem5::statistics::DistData::logs, gem5::ArmISA::m, gem5::statistics::DistData::max_val, gem5::statistics::DistData::min_val, gem5::statistics::Info::name, name(), gem5::statistics::nozero, gem5::statistics::DistData::overflow, gem5::statistics::periodicStatDump(), gem5::statistics::Group::preDumpStats(), gem5::statistics::Info::prepare(), gem5::statistics::processDumpQueue(), gem5::statistics::processResetQueue(), gem5::statistics::registerPythonStatsHandlers(), gem5::statistics::Group::regStats(), gem5::statistics::Info::reset(), gem5::statistics::Group::resetStats(), gem5::statistics::Group::resolveStat(), gem5::statistics::ScalarInfo::result(), gem5::statistics::schedStatEvent(), gem5::statistics::DistData::squares, gem5::statistics::statsList(), gem5::statistics::FormulaInfo::str(), gem5::statistics::VectorInfo::subdescs, gem5::statistics::Vector2dInfo::subdescs, gem5::statistics::VectorInfo::subnames, gem5::statistics::Vector2dInfo::subnames, gem5::statistics::DistData::sum, gem5::statistics::ScalarInfo::total(), gem5::statistics::DistData::underflow, gem5::statistics::Info::unit, gem5::statistics::updateEvents(), gem5::statistics::Output::valid(), gem5::statistics::ScalarInfo::value(), gem5::statistics::Info::visit(), gem5::statistics::Vector2dInfo::x, gem5::statistics::Vector2dInfo::y, gem5::statistics::Vector2dInfo::y_subnames, and gem5::statistics::Info::zero().

pybind_init_stats() [2/2]

void gem5::pybind_init_stats

(

pybind11::module_ &

m_native

)

Referenced by gem5::EmbeddedPyBind::initAll().

pybind_init_tracers()

void gem5::pybind_init_tracers

(

py::module_ &

m_native

)

Definition at line 85 of file pygen.cc.

References gem5::ArmISA::m.

quote()

std::string gem5::quote ( const std::string &  s )

inline

Definition at line 209 of file str.hh.

References quote(), and gem5::ArmISA::s.

Referenced by quote(), TEST(), TEST(), TEST(), and TEST().

raiseFatalSignal()

static void gem5::raiseFatalSignal ( int  signo )

static

Definition at line 102 of file init_signals.cc.

References STATIC_ERR.

Referenced by abortHandler(), and segvHandler().

readFunc()

template<class OS >

SyscallReturn gem5::readFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr<>	buf_ptr,
		typename OS::size_t	nbytes
	)

Definition at line 2793 of file syscall_emul.hh.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyOut(), gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and gem5::SyscallReturn::retry().

readlinkatFunc()

template<class OS >

SyscallReturn gem5::readlinkatFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	dirfd,
		VPtr<>	pathname,
		VPtr<>	buf_ptr,
		typename OS::size_t	bufsiz
	)

Target readlinkat() handler.

Definition at line 1064 of file syscall_emul.hh.

References gem5::BufferArg::bufferPtr(), gem5::Process::checkPathRedirect(), gem5::BaseBufferArg::copyOut(), fatal, gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and warn_once.

readlinkFunc()

template<class OS >

SyscallReturn gem5::readlinkFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		VPtr<>	buf_ptr,
		typename OS::size_t	bufsiz
	)

Target readlink() handler.

Definition at line 1130 of file syscall_emul.hh.

readMemAtomic() [1/3]

template<class XC >

Fault gem5::readMemAtomic	(	XC *	xc,
		Addr	addr,
		uint8_t *	mem,
		std::size_t	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable
	)

Read from memory in atomic mode.

Definition at line 102 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, and mem.

Referenced by readMemAtomic(), and readMemAtomic().

readMemAtomic() [2/3]

template<ByteOrder Order, class XC , class MemT >

Fault gem5::readMemAtomic	(	XC *	xc,
		trace::InstRecord *	traceData,
		Addr	addr,
		MemT &	mem,
		Request::Flags	flags
	)

Read from memory in atomic mode.

Definition at line 112 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, gtoh(), mem, NoFault, readMemAtomic(), and gem5::trace::InstRecord::setData().

readMemAtomic() [3/3]

template<ByteOrder Order, class XC , class MemT >

Fault gem5::readMemAtomic	(	XC *	xc,
		trace::InstRecord *	traceData,
		Addr	addr,
		MemT &	mem,
		size_t	size,
		Request::Flags	flags
	)

Read from memory in atomic mode.

Definition at line 130 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, gtoh(), mem, NoFault, readMemAtomic(), and gem5::trace::InstRecord::setData().

readMemAtomicBE()

template<class XC , class MemT >

Fault gem5::readMemAtomicBE	(	XC *	xc,
		trace::InstRecord *	traceData,
		Addr	addr,
		MemT &	mem,
		Request::Flags	flags
	)

Definition at line 166 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, and mem.

readMemAtomicLE() [1/2]

template<class XC , class MemT >

Fault gem5::readMemAtomicLE	(	XC *	xc,
		trace::InstRecord *	traceData,
		Addr	addr,
		MemT &	mem,
		Request::Flags	flags
	)

Definition at line 147 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, and mem.

readMemAtomicLE() [2/2]

template<class XC , class MemT >

Fault gem5::readMemAtomicLE	(	XC *	xc,
		trace::InstRecord *	traceData,
		Addr	addr,
		MemT &	mem,
		size_t	size,
		Request::Flags	flags
	)

Definition at line 156 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, and mem.

readvFunc()

template<class OS >

SyscallReturn gem5::readvFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr<>	tiov_base,
		typename OS::size_t	count
	)

Target readv() handler.

Definition at line 1922 of file syscall_emul.hh.

References gem5::X86ISA::count, gem5::ThreadContext::getProcessPtr(), gtoh(), htog(), gem5::ArmISA::i, gem5::MipsISA::p, gem5::PortProxy::readBlob(), and gem5::PortProxy::writeBlob().

recvfromFunc()

template<class OS >

SyscallReturn gem5::recvfromFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr<>	buf_ptr,
		typename OS::size_t	buf_len,
		int	flags,
		VPtr<>	addr_ptr,
		VPtr<>	addrlen_ptr
	)

Definition at line 3037 of file syscall_emul.hh.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), gem5::BaseBufferArg::copyOut(), flags, gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and gem5::ArmISA::sa.

recvmsgFunc()

SyscallReturn gem5::recvmsgFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr<>	msgPtr,
		int	flags
	)

struct msghdr { void *msg_name; // optional address socklen_t msg_namelen; // size of address struct iovec *msg_iov; // iovec array size_t msg_iovlen; // number entries in msg_iov i // entries correspond to buffer void *msg_control; // ancillary data size_t msg_controllen; // ancillary data buffer len int msg_flags; // flags on received message };

struct iovec { void *iov_base; // starting address size_t iov_len; // number of bytes to transfer };

The plan with this system call is to replace all of the pointers in the structure and the substructure with BufferArg class pointers. We will copy every field from the structures into our BufferArg classes.

We will use these address place holders to retain the pointers which we are going to replace with our own buffers in our simulator address space.

Record msg_name pointer then replace with buffer pointer.

Record msg_iov pointer then replace with buffer pointer. Also, setup an array of buffer pointers for the iovec structs record and replace their pointers with buffer pointers.

Record msg_control pointer then replace with buffer pointer.

Definition at line 1117 of file syscall_emul.cc.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), gem5::BaseBufferArg::copyOut(), flags, gem5::ThreadContext::getProcessPtr(), gem5::ArmISA::i, and gem5::MipsISA::p.

registerExitCallback()

void gem5::registerExitCallback

(

const std::function< void()> &

)

Register an exit callback.

Register a callback to be called when Python exits.

Defined in sim/main.cc.

Definition at line 143 of file core.cc.

References exitCallbacks().

Referenced by gem5::BaseTags::BaseTags(), gem5::CowDiskImage::CowDiskImage(), gem5::trace::InstPBTrace::createTraceFile(), gem5::memory::DRAMSysWrapper::DRAMSysWrapper(), gem5::MemTraceProbe::MemTraceProbe(), gem5::memory::PhysicalMemory::PhysicalMemory(), gem5::tlm::chi::TlmGenerator::TlmGenerator(), and gem5::VirtIO9PDiod::VirtIO9PDiod().

renameatFunc()

template<class OS >

SyscallReturn gem5::renameatFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	olddirfd,
		VPtr<>	oldpath,
		int	newdirfd,
		VPtr<>	newpath
	)

Target renameat() handler.

Definition at line 1141 of file syscall_emul.hh.

References renameImpl(), and gem5::PortProxy::tryReadString().

renameFunc()

SyscallReturn gem5::renameFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	oldpath,
		VPtr<>	newpath
	)

Target rename() handler.

Definition at line 430 of file syscall_emul.cc.

References renameImpl(), and gem5::PortProxy::tryReadString().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

renameImpl()

SyscallReturn gem5::renameImpl	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		std::string	old_name,
		std::string	new_name
	)

Definition at line 446 of file syscall_emul.cc.

References gem5::Process::checkPathRedirect(), gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

Referenced by renameatFunc(), and renameFunc().

replace()

std::string gem5::replace ( const std::string &  s, char  from, char  to  )

inline

Definition at line 256 of file str.hh.

References gem5::ArmISA::s, and gem5::PowerISA::to.

replaceUpgrade()

static void gem5::replaceUpgrade ( PacketPtr  pkt )

static

Definition at line 190 of file mshr.cc.

References gem5::Packet::allocate(), gem5::Packet::cmd, DPRINTF, gem5::Packet::hasData(), gem5::Packet::hasRespData(), gem5::MemCmd::ReadExReq, gem5::MemCmd::SCUpgradeFailReq, gem5::MemCmd::SCUpgradeReq, gem5::MemCmd::StoreCondFailReq, gem5::MemCmd::StoreCondReq, and gem5::MemCmd::UpgradeReq.

Referenced by gem5::MSHR::allocateTarget(), and gem5::MSHR::TargetList::replaceUpgrades().

restoreSigInt()

void gem5::restoreSigInt

(

)

Definition at line 227 of file init_signals.cc.

References old_int_sa.

Referenced by simulate().

rmdirFunc()

SyscallReturn gem5::rmdirFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname
	)

Definition at line 945 of file syscall_emul.cc.

References rmdirImpl().

rmdirImpl()

SyscallReturn gem5::rmdirImpl	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		std::string	path
	)

Definition at line 955 of file syscall_emul.cc.

References gem5::Process::checkPathRedirect(), gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

Referenced by rmdirFunc(), and unlinkatFunc().

romMicroPC()

static MicroPC gem5::romMicroPC ( MicroPC  upc )

inlinestatic

Definition at line 154 of file types.hh.

References MicroPCRomBit.

Referenced by gem5::X86ISA::X86FaultBase::invoke(), gem5::X86ISA::InitInterrupt::invoke(), and TEST().

safe_cast()

template<class T , class U >

T gem5::safe_cast ( U &&  ref_or_ptr )

inline

Definition at line 74 of file cast.hh.

SafeRead() [1/2]

template<class T >

void gem5::SafeRead	(	std::ifstream &	stream,
		T &	data
	)

Definition at line 225 of file disk_image.cc.

References data, and SafeRead().

SafeRead() [2/2]

void gem5::SafeRead	(	std::ifstream &	stream,
		void *	data,
		int	count
	)

Definition at line 210 of file disk_image.cc.

References gem5::X86ISA::count, data, and panic.

Referenced by gem5::CowDiskImage::open(), SafeRead(), and SafeReadSwap().

SafeReadSwap()

template<class T >

void gem5::SafeReadSwap	(	std::ifstream &	stream,
		T &	data
	)

Definition at line 232 of file disk_image.cc.

References data, letoh(), and SafeRead().

Referenced by gem5::CowDiskImage::open().

SafeWrite() [1/2]

template<class T >

void gem5::SafeWrite	(	std::ofstream &	stream,
		const T &	data
	)

Definition at line 308 of file disk_image.cc.

References data, and SafeWrite().

SafeWrite() [2/2]

void gem5::SafeWrite	(	std::ofstream &	stream,
		const void *	data,
		int	count
	)

Definition at line 293 of file disk_image.cc.

References gem5::X86ISA::count, data, and panic.

Referenced by SafeWrite(), SafeWriteSwap(), and gem5::CowDiskImage::save().

SafeWriteSwap()

template<class T >

void gem5::SafeWriteSwap	(	std::ofstream &	stream,
		const T &	data
	)

Definition at line 315 of file disk_image.cc.

References data, letoh(), and SafeWrite().

Referenced by gem5::CowDiskImage::save().

schedBreak()

void gem5::schedBreak

(

Tick

when

)

Cause the simulator to execute a breakpoint.

Parameters

when	the tick to break

Definition at line 86 of file debug.cc.

References warn.

Referenced by pybind_init_debug(), and schedRelBreak().

schedGetaffinityFunc()

template<class OS >

SyscallReturn gem5::schedGetaffinityFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		pid_t	pid,
		typename OS::size_t	cpusetsize,
		VPtr<>	cpu_set_mask
	)

Target sched_getaffinity.

Definition at line 3012 of file syscall_emul.hh.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), gem5::BaseBufferArg::copyOut(), gem5::ThreadContext::getSystemPtr(), gem5::ArmISA::i, gem5::System::Threads::size(), gem5::System::threads, and warnUnsupportedOS().

schedRelBreak()

void gem5::schedRelBreak

(

Tick

delta

)

Cause the simulator to execute a breakpoint relative to the current tick.

Parameters

delta

the number of ticks to execute until breaking

Definition at line 93 of file debug.cc.

References curTick(), and schedBreak().

Referenced by gem5::RiscvISA::BreakpointFault::invokeSE().

segvHandler()

static void gem5::segvHandler ( int  sigtype )

static

Segmentation fault signal handler.

Definition at line 165 of file init_signals.cc.

References print_backtrace(), raiseFatalSignal(), and STATIC_ERR.

Referenced by initSignals().

selectFunc()

template<class OS >

SyscallReturn gem5::selectFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	nfds,
		VPtr< typename OS::fd_set >	readfds,
		VPtr< typename OS::fd_set >	writefds,
		VPtr< typename OS::fd_set >	errorfds,
		VPtr< typename OS::timeval >	timeout
	)

Host fields. Notice that these use the definitions from the system headers instead of the gem5 headers and libraries. If the host and target have different header file definitions, this will not work.

We need to translate the target file descriptor set into a host file descriptor set. This involves both our internal process fd array and the fd_set defined in Linux header files. The nfds field also needs to be updated as it will be only target specific after retrieving it from the target; the nfds value is expected to be the highest file descriptor that needs to be checked, so we need to extend it out for nfds_h when we do the update.

By this point, we know that we are looking at a valid file descriptor set on the target. We need to check if the target file descriptor value passed in as iter is part of the set.

We know that the target file descriptor belongs to the set, but we do not yet know if the file descriptor is valid or that we have a host mapping. Check that now.

Add the sim_fd to tgt_fd translation into trans_map for use later when we need to zero the target fd_set structures and then update them with hits returned from the host select call.

We know that the host file descriptor exists so now we check if we need to update the max count for nfds_h before passing the duplicated structure into the host.

Add the host file descriptor to the set that we are going to pass into the host.

It might be possible to decrement the timeval based on some derivation of wall clock determined from elapsed simulator ticks but that seems like overkill. Rather, we just set the timeval with zero timeout. (There is no reason to block during the simulation as it only decreases simulator performance.)

If the timeval pointer is null, setup a new timeval structure to pass into the host select call. Unfortunately, we will need to manually check the return value and throw a retry fault if the return value is zero. Allowing the system call to block will likely deadlock the event queue.

If blocking indefinitely, check the signal list to see if a signal would break the poll out of the retry cycle and try to return the signal interrupt instead.

We need to translate the host file descriptor set into a target file descriptor set. This involves both our internal process fd array and the fd_set defined in header files.

Definition at line 2614 of file syscall_emul.hh.

References gem5::ThreadContext::getProcessPtr(), gem5::ThreadContext::getSystemPtr(), gem5::ArmISA::i, gem5::MipsISA::p, gem5::SyscallReturn::retry(), and gem5::System::signalList.

sendmsgFunc()

SyscallReturn gem5::sendmsgFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr<>	msgPtr,
		int	flags
	)

Reserve buffer space.

Assuming msgHdr.msg_iovlen >= 1, then there is no point calling recvmsg without a buffer.

Cannot instantiate buffers till inside the loop. Create array to hold buffer addresses, to be used during copyIn of send data.

Iterate through the iovec structures: Get the base buffer addreses, reserve iov_len amount of space for each. Put the buf address into the bufferArray for later retrieval.

Free dynamically allocated memory.

Malloced above.

Definition at line 1257 of file syscall_emul.cc.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), flags, gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

sendtoFunc()

template<typename OS >

SyscallReturn gem5::sendtoFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr<>	buf_ptr,
		typename OS::size_t	buf_len,
		int	flags,
		VPtr<>	addr_ptr,
		socklen_t	addr_len
	)

Definition at line 3101 of file syscall_emul.hh.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), flags, gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and gem5::ArmISA::sa.

serialize()

void gem5::serialize	(	const ThreadContext &	tc,
		CheckpointOut &	cp
	)

Thread context serialization helpers.

These helper functions provide a way to the data in a ThreadContext. They are provided as separate helper function since implementing them as members of the ThreadContext interface would be confusing when the ThreadContext is exported via a proxy.

Definition at line 194 of file thread_context.cc.

References arrayParamOut, gem5::ThreadContext::getIsaPtr(), gem5::ThreadContext::getReg(), MiscRegClass, gem5::ThreadContext::pcState(), gem5::BaseISA::regClasses(), and gem5::PCStateBase::serialize().

Referenced by exitSimLoop(), gem5::o3::ThreadState::serialize(), gem5::SimpleThread::serialize(), and gem5::Iris::BaseCPU::serializeThread().

set_max_tick()

void gem5::set_max_tick

(

Tick

tick

)

Set the maximum tick.

This function will schedule, or reschedule, the maximum tick for the simulation.

This will setup the GlobalSimLoopExitEvent if it does not already exist.

Parameters

tick	The maximum tick.

Definition at line 253 of file simulate.cc.

References mainEventQueue, gem5::BaseGlobalEvent::reschedule(), and simulate_limit_event.

Referenced by pybind_init_event(), and simulate().

setClockFrequency()

void gem5::setClockFrequency

(

Tick

tps

)

Definition at line 115 of file core.cc.

References panic_if.

Referenced by pybind_init_core(), and sc_core::sc_set_time_resolution().

setContextSegment() [1/2]

void gem5::setContextSegment ( ThreadContext *  tc, const struct kvm_dtable &  kvm_dtable, const int  index  )

inline

Definition at line 1097 of file x86_cpu.cc.

References gem5::MipsISA::index, gem5::X86ISA::misc_reg::segBase(), gem5::X86ISA::misc_reg::segLimit(), and gem5::ThreadContext::setMiscReg().

setContextSegment() [2/2]

void gem5::setContextSegment ( ThreadContext *  tc, const struct kvm_segment &  kvm_seg, const int  index  )

inline

Definition at line 1072 of file x86_cpu.cc.

References gem5::ArmISA::attr, gem5::MipsISA::index, gem5::X86ISA::misc_reg::segAttr(), gem5::X86ISA::misc_reg::segBase(), gem5::X86ISA::misc_reg::segLimit(), gem5::X86ISA::misc_reg::segSel(), and gem5::ThreadContext::setMiscReg().

setDebugFlag()

void gem5::setDebugFlag

(

const char *

string

)

Definition at line 193 of file debug.cc.

References gem5::debug::changeFlag().

Referenced by gem5::trace::TarmacTracer::TarmacTracer(), and TEST().

setFpRound()

static void gem5::setFpRound ( RoundingMode  rm )

inline

Definition at line 42 of file fenv.cc.

References gem5::ArmISA::rm, and roundOps.

setKvmDTableReg()

static void gem5::setKvmDTableReg ( ThreadContext *  tc, struct kvm_dtable &  kvm_dtable, const int  index  )

inlinestatic

Definition at line 785 of file x86_cpu.cc.

References gem5::MipsISA::index, gem5::ThreadContext::readMiscRegNoEffect(), gem5::X86ISA::misc_reg::segBase(), and gem5::X86ISA::misc_reg::segLimit().

setKvmSegmentReg()

static void gem5::setKvmSegmentReg ( ThreadContext *  tc, struct kvm_segment &  kvm_seg, const int  index  )

inlinestatic

Definition at line 765 of file x86_cpu.cc.

References gem5::ArmISA::attr, gem5::MipsISA::index, gem5::ThreadContext::readMiscRegNoEffect(), gem5::X86ISA::misc_reg::segAttr(), gem5::X86ISA::misc_reg::segBase(), gem5::X86ISA::misc_reg::segLimit(), and gem5::X86ISA::misc_reg::segSel().

setOutputDir()

void gem5::setOutputDir

(

const std::string &

dir

)

Definition at line 124 of file core.cc.

References gem5::OutputDirectory::setDirectory(), and simout.

Referenced by pybind_init_core().

setpgidFunc()

SyscallReturn gem5::setpgidFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	pid,
		int	pgid
	)

Target setpgid() handler.

Definition at line 788 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), gem5::ThreadContext::getSystemPtr(), gem5::ThreadContext::Halted, gem5::Process::pgid(), gem5::Process::pid(), gem5::ThreadContext::status(), and gem5::System::threads.

setRegNoEffectWithMask()

template<typename xint >

static void gem5::setRegNoEffectWithMask ( ThreadContext *  context, RiscvType  type, PrivilegeModeSet  pms, CSRIndex  idx, xint  val  )

static

Definition at line 164 of file remote_gdb.cc.

References gem5::RiscvISA::CSRData, gem5::RiscvISA::CSRMasks, gem5::ArmISA::mask, gem5::ThreadContext::readMiscRegNoEffect(), gem5::ThreadContext::setMiscRegNoEffect(), gem5::X86ISA::type, and gem5::X86ISA::val.

Referenced by gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::setRegs(), and gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::setRegs().

setRegWithMask()

template<typename xint >

static void gem5::setRegWithMask ( ThreadContext *  context, RiscvType  type, PrivilegeModeSet  pms, CSRIndex  idx, xint  val  )

static

Definition at line 177 of file remote_gdb.cc.

References gem5::RiscvISA::CSRData, gem5::RiscvISA::CSRMasks, gem5::ArmISA::mask, gem5::ThreadContext::readMiscReg(), gem5::ThreadContext::setMiscReg(), gem5::X86ISA::type, and gem5::X86ISA::val.

Referenced by gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::setRegs(), and gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::setRegs().

setsockoptFunc()

SyscallReturn gem5::setsockoptFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		int	level,
		int	optname,
		VPtr<>	valPtr,
		socklen_t	len
	)

Definition at line 1436 of file syscall_emul.cc.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), gem5::ThreadContext::getProcessPtr(), gem5::ArmISA::len, gem5::X86ISA::level, gem5::MipsISA::p, and gem5::ArmISA::status.

setTidAddressFunc()

SyscallReturn gem5::setTidAddressFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	tidPtr
	)

Target set_tid_address() handler.

Definition at line 292 of file syscall_emul.cc.

References gem5::Process::childClearTID, and gem5::ThreadContext::getProcessPtr().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

setUintX()

bool gem5::setUintX	(	std::uint64_t	val,
		void *	buf,
		std::size_t	bytes,
		ByteOrder	endian
	)

Definition at line 59 of file bufval.cc.

References gem5::X86ISA::val.

Referenced by gem5::Packet::setUintX(), TEST(), TEST(), and TEST().

setupAltStack()

static bool gem5::setupAltStack ( )

static

Definition at line 69 of file init_signals.cc.

References gem5::X86ISA::stack.

Referenced by initSignals().

shutdownFunc()

SyscallReturn gem5::shutdownFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		int	how
	)

Target shutdown() handler.

Definition at line 1044 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

simulate()

GlobalSimLoopExitEvent * gem5::simulate

(

Tick

num_cycles

)

Definition at line 189 of file simulate.cc.

References gem5::GlobalSimLoopExitEvent::clean(), curTick(), doSimLoop(), fatal_if, global_exit_event, gem5::Event::globalEvent(), inform, initSigInt(), inParallelMode, mainEventQueue, MaxTick, numMainEventQueues, gem5::EventBase::Progress_Event_Pri, restoreSigInt(), set_max_tick(), simQuantum, simulate_limit_event, and simulatorThreads.

Referenced by gem5::ruby::RubySystem::memWriteback(), pybind_init_event(), and gem5::ruby::RubySystem::startup().

sleep()

void gem5::sleep

(

const Time &

time

)

Definition at line 142 of file time.cc.

References gem5::ArmISA::ts.

Referenced by gem5::Root::timeSync().

socketFunc()

template<class OS >

SyscallReturn gem5::socketFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	domain,
		int	type,
		int	prot
	)

Definition at line 2574 of file syscall_emul.hh.

References gem5::ArmISA::domain, gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, gem5::X86ISA::prot, and gem5::X86ISA::type.

socketpairFunc()

template<class OS >

SyscallReturn gem5::socketpairFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	domain,
		int	type,
		int	prot,
		VPtr<>	svPtr
	)

Definition at line 2591 of file syscall_emul.hh.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyOut(), gem5::ArmISA::domain, gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, gem5::X86ISA::prot, gem5::ArmISA::status, and gem5::X86ISA::type.

SPDSTS_POLARITY()

static int gem5::SPDSTS_POLARITY ( int  lnksts )

inlinestatic

Definition at line 421 of file ns_gige_reg.h.

References CFGR_DUPSTS, CFGR_LNKSTS, CFGR_SPDSTS0, CFGR_SPDSTS1, and CFGR_ZERO.

split_first()

bool gem5::split_first	(	const std::string &	s,
		std::string &	lhs,
		std::string &	rhs,
		char	c
	)

Definition at line 38 of file str.cc.

References gem5::ArmISA::c, gem5::ArmISA::offset, and gem5::ArmISA::s.

Referenced by TEST(), TEST(), and TEST().

split_last()

bool gem5::split_last	(	const std::string &	s,
		std::string &	lhs,
		std::string &	rhs,
		char	c
	)

Definition at line 53 of file str.cc.

References gem5::ArmISA::c, gem5::ArmISA::offset, and gem5::ArmISA::s.

Referenced by TEST(), TEST(), and TEST().

startswith() [1/3]

bool gem5::startswith ( const char *  s, const char *  prefix  )

inline

Return true if 's' starts with the prefix string 'prefix'.

Definition at line 230 of file str.hh.

References gem5::ArmISA::s.

Referenced by gem5::Process::absolutePath(), atSyscallPath(), chdirFunc(), gem5::Process::checkPathRedirect(), normalizePath(), openatFunc(), procInfo(), gem5::System::stripSystemName(), TEST(), TEST(), TEST(), TEST(), TEST(), and TEST().

startswith() [2/3]

bool gem5::startswith ( const std::string &  s, const char *  prefix  )

inline

Return true if 's' starts with the prefix string 'prefix'.

Definition at line 240 of file str.hh.

References gem5::ArmISA::s.

startswith() [3/3]

bool gem5::startswith ( const std::string &  s, const std::string &  prefix  )

inline

Return true if 's' starts with the prefix string 'prefix'.

Definition at line 250 of file str.hh.

References gem5::ArmISA::s.

stat64Func()

template<class OS >

SyscallReturn gem5::stat64Func	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		VPtr< typename OS::tgt_stat64 >	tgt_stat
	)

Target stat64() handler.

Definition at line 1557 of file syscall_emul.hh.

statfsFunc()

template<class OS >

SyscallReturn gem5::statfsFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		VPtr< typename OS::tgt_statfs >	tgt_stat
	)

Target statfs() handler.

Definition at line 1718 of file syscall_emul.hh.

References gem5::Process::checkPathRedirect(), gem5::ThreadContext::getProcessPtr(), and warnUnsupportedOS().

statFunc()

template<class OS >

SyscallReturn gem5::statFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		VPtr< typename OS::tgt_stat >	tgt_stat
	)

Target stat() handler.

Definition at line 1455 of file syscall_emul.hh.

References gem5::Process::checkPathRedirect(), and gem5::ThreadContext::getProcessPtr().

statxFunc()

template<class OS >

SyscallReturn gem5::statxFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	dirfd,
		VPtr<>	pathname,
		int	flags,
		unsigned int	mask,
		VPtr< typename OS::tgt_statx >	tgt_statx
	)

Target statx() handler.

Definition at line 1566 of file syscall_emul.hh.

References gem5::Process::checkPathRedirect(), flags, gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and warn_if.

swap_byte() [1/7]

template<typename T , size_t N>

std::array< T, N > gem5::swap_byte ( std::array< T, N >  a )

inline

Definition at line 156 of file byteswap.hh.

References gem5::ArmISA::a, swap_byte(), and gem5::ArmISA::v.

swap_byte() [2/7]

template<typename T >

std::enable_if_t< std::is_same_v< T, vring_used_elem >, T > gem5::swap_byte ( T  v )

inline

Definition at line 76 of file base.hh.

References swap_byte(), and gem5::ArmISA::v.

Referenced by betole(), htole(), letobe(), letoh(), gem5::auxv::swap_byte(), swap_byte(), swap_byte(), swap_byte(), and TEST().

swap_byte() [3/7]

template<typename T >

std::enable_if_t< std::is_same_v< T, vring_desc >, T > gem5::swap_byte ( T  v )

inline

Definition at line 85 of file base.hh.

References swap_byte(), and gem5::ArmISA::v.

swap_byte() [4/7]

template<typename T >

std::enable_if_t< sizeof(T)==8 &&std::is_convertible_v< T, uint64_t >, T > gem5::swap_byte ( T  x )

inline

Definition at line 116 of file byteswap.hh.

References swap_byte(), swap_byte64(), and gem5::RiscvISA::x.

swap_byte() [5/7]

template<typename T >

std::enable_if_t< sizeof(T)==4 &&std::is_convertible_v< T, uint32_t >, T > gem5::swap_byte ( T  x )

inline

Definition at line 124 of file byteswap.hh.

References swap_byte(), swap_byte32(), and gem5::RiscvISA::x.

swap_byte() [6/7]

template<typename T >

std::enable_if_t< sizeof(T)==2 &&std::is_convertible_v< T, uint16_t >, T > gem5::swap_byte ( T  x )

inline

Definition at line 132 of file byteswap.hh.

References swap_byte(), swap_byte16(), and gem5::RiscvISA::x.

swap_byte() [7/7]

template<typename T >

std::enable_if_t< sizeof(T)==1 &&std::is_convertible_v< T, uint8_t >, T > gem5::swap_byte ( T  x )

inline

Definition at line 140 of file byteswap.hh.

References swap_byte(), and gem5::RiscvISA::x.

swap_byte16()

uint16_t gem5::swap_byte16 ( uint16_t  x )

inline

Definition at line 101 of file byteswap.hh.

References gem5::RiscvISA::x.

Referenced by swap_byte(), and TEST().

swap_byte32()

uint32_t gem5::swap_byte32 ( uint32_t  x )

inline

Definition at line 87 of file byteswap.hh.

References gem5::RiscvISA::x.

Referenced by swap_byte(), and TEST().

swap_byte64()

uint64_t gem5::swap_byte64 ( uint64_t  x )

inline

Definition at line 68 of file byteswap.hh.

References gem5::RiscvISA::x.

Referenced by swap_byte(), and TEST().

symlinkFunc()

SyscallReturn gem5::symlinkFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		VPtr<>	new_pathname
	)

Target symlink() handler.

Definition at line 389 of file syscall_emul.cc.

References gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and gem5::PortProxy::tryReadString().

sysGettid()

static pid_t gem5::sysGettid ( )

static

Definition at line 65 of file timer.cc.

Referenced by gem5::PosixKvmTimer::PosixKvmTimer().

sysinfoFunc()

template<class OS >

SyscallReturn gem5::sysinfoFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr< typename OS::tgt_sysinfo >	sysinfo
	)

Target sysinfo() handler.

Definition at line 1224 of file syscall_emul.hh.

References gem5::ThreadContext::getProcessPtr(), and seconds_since_epoch.

takeCheckpoint()

void gem5::takeCheckpoint

(

Tick

when

)

Function to cause the simulator to take a checkpoint from the debugger.

Cause the simulator to return to python to create a checkpoint.

Parameters

when	the cycle to break

Definition at line 102 of file debug.cc.

References curTick(), and exitSimLoop().

takeOverFrom()

void gem5::takeOverFrom	(	ThreadContext &	new_tc,
		ThreadContext &	old_tc
	)

Copy state between thread contexts in preparation for CPU handover.

Note

This method modifies the old thread contexts as well as the new thread context. The old thread context will have its quiesce event descheduled if it is scheduled and its status set to halted.

Parameters

new_tc	Destination ThreadContext.
old_tc	Source ThreadContext.

Definition at line 252 of file thread_context.cc.

References gem5::ThreadContext::contextId(), gem5::ThreadContext::copyArchRegs(), FullSystem, gem5::ThreadContext::getProcessPtr(), gem5::ThreadContext::getSystemPtr(), gem5::ThreadContext::Halted, gem5::ThreadContext::setContextId(), gem5::ThreadContext::setStatus(), gem5::ThreadContext::setThreadId(), gem5::ThreadContext::status(), and gem5::ThreadContext::threadId().

Referenced by gem5::o3::ThreadContext::takeOverFrom(), and gem5::SimpleThread::takeOverFrom().

terminateEventQueueThreads()

void gem5::terminateEventQueueThreads

(

)

Terminate helper threads when running in parallel mode.

Precondition

Simulator must have returned from simulate() to service a GlobalExitEvent prior to calling this function.

Definition at line 277 of file simulate.cc.

References simulatorThreads.

Referenced by pybind_init_event().

tgkillFunc()

template<class OS >

SyscallReturn gem5::tgkillFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgid,
		int	tid,
		int	sig
	)

This system call is intended to allow killing a specific thread within an arbitrary thread group if sanctioned with permission checks. It's usually true that threads share the termination signal as pointed out by the pthread_kill man page and this seems to be the intended usage. Due to this being an emulated environment, assume the following: Threads are allowed to call tgkill because the EUID for all threads should be the same. There is no signal handling mechanism for kernel registration of signal handlers since signals are poorly supported in emulation mode. Since signal handlers cannot be registered, all threads within in a thread group must share the termination signal. We never exhaust PIDs so there's no chance of finding the wrong one due to PID rollover.

Definition at line 2530 of file syscall_emul.hh.

References exitGroupFunc(), gem5::ThreadContext::getProcessPtr(), gem5::ThreadContext::getSystemPtr(), gem5::Process::pid(), gem5::Process::tgid(), and gem5::System::threads.

timeFunc()

template<class OS >

SyscallReturn gem5::timeFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	taddr
	)

Target time() function.

Definition at line 2513 of file syscall_emul.hh.

References getElapsedTimeMicro(), htog(), gem5::MipsISA::p, seconds_since_epoch, and gem5::ArmISA::t.

timesFunc()

template<class OS >

SyscallReturn gem5::timesFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr< typename OS::tms >	bufp
	)

Target times() function.

Definition at line 2494 of file syscall_emul.hh.

References curTick(), htog(), and gem5::sim_clock::as_int::s.

to_bool()

bool gem5::to_bool ( const std::string &  value, bool &  retval  )

inline

Turn a string representation of a boolean into a boolean value.

Definition at line 192 of file str.hh.

References gem5::ArmISA::s, and to_lower().

Referenced by gem5::ParseParam< bool >::parse(), TEST(), TEST(), and TEST().

to_lower()

std::string gem5::to_lower ( const std::string &  s )

inline

Definition at line 75 of file str.hh.

References gem5::ArmISA::c, gem5::ArmISA::len, and gem5::ArmISA::s.

Referenced by TEST(), and to_bool().

to_number() [1/2]

bool gem5::to_number ( const std::string &  value, Pixel &  retval  )

inline

Definition at line 217 of file pixel.hh.

References gem5::PixelConverter::rgba8888_le, to_number(), and gem5::PixelConverter::toPixel().

Referenced by gem5::pseudo_inst::loadsymbol(), gem5::ParseParam< BitUnionType< T > >::parse(), gem5::ParseParam< T, decltype(to_number("", std::declval< T & >()), void())>::parse(), gem5::ListenSocketConfig::parseIni(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), and to_number().

to_number() [2/2]

template<class T >

std::enable_if_t<(std::is_integral_v< T >|| std::is_floating_point_v< T >|| std::is_enum_v< T >) && !std::is_same_v< bool, T >, bool > gem5::to_number ( const std::string &  value, T &  retval  )

inline

Turn a string representation of a number, either integral, floating point, or enum into an actual number.

Use to_bool for booleans.

Parameters

value	The string representing the number
retval	The resulting value

Returns

True if the parsing was successful

Definition at line 174 of file str.hh.

References panic.

tokenize()

void gem5::tokenize	(	std::vector< std::string > &	v,
		const std::string &	s,
		char	token,
		bool	ignore
	)

Definition at line 68 of file str.cc.

References ignore(), gem5::ArmISA::s, gem5::scmi::token, and gem5::ArmISA::v.

Referenced by arrayParamIn(), gem5::ObjectMatch::domatch(), gem5::CxxIniFile::getParamVector(), gem5::statistics::Info::less(), gem5::IniFile::Section::printUnreferenced(), gem5::ObjectMatch::setExpression(), gem5::ObjectMatch::setExpression(), TEST(), TEST(), TEST(), and gem5::statistics::validateStatName().

transferNeedsBurst()

bool gem5::transferNeedsBurst ( Addr  addr, unsigned int  size, unsigned int  block_size  )

inline

Returns true if the given memory access (address, size) needs to be fragmented across aligned fixed-size blocks.

Parameters

addr	Address of the memory access.
size	Size of the memory access.
block_size	Block size in bytes.

Returns

True if the memory access needs to be fragmented.

Definition at line 80 of file utils.hh.

References gem5::X86ISA::addr, and addrBlockOffset().

Referenced by gem5::o3::LSQ::pushRequest(), and gem5::minor::LSQ::pushRequest().

truncate64Func()

SyscallReturn gem5::truncate64Func	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		int64_t	length
	)

Target truncate64() handler.

Definition at line 461 of file syscall_emul.cc.

References gem5::Process::checkPathRedirect(), and gem5::ThreadContext::getProcessPtr().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

truncateFunc()

template<typename OS >

SyscallReturn gem5::truncateFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		typename OS::off_t	length
	)

Target truncate() handler.

Definition at line 3182 of file syscall_emul.hh.

References gem5::Process::checkPathRedirect(), gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

tryTranslate()

static bool gem5::tryTranslate ( ThreadContext *  tc, Addr  addr  )

static

Definition at line 186 of file remote_gdb.cc.

References gem5::X86ISA::addr, gem5::BaseMMU::Execute, gem5::ThreadContext::getMMUPtr(), NoFault, gem5::BaseMMU::Read, and gem5::BaseMMU::translateFunctional().

Referenced by gem5::ArmISA::RemoteGDB::acc().

umaskFunc()

SyscallReturn gem5::umaskFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc
	)

Target umask() handler.

Definition at line 501 of file syscall_emul.cc.

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32().

unbcdize()

static uint8_t gem5::unbcdize ( uint8_t  val )

static

Definition at line 55 of file mc146818.cc.

References gem5::X86ISA::val.

Referenced by gem5::MC146818::writeData().

unimplementedFunc()

SyscallReturn gem5::unimplementedFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc
	)

Handler for unimplemented syscalls that we haven't thought about.

Definition at line 77 of file syscall_emul.cc.

References fatal, gem5::SyscallDesc::name(), and gem5::SyscallDesc::num().

unlinkatFunc()

template<class OS >

SyscallReturn gem5::unlinkatFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	dirfd,
		VPtr<>	pathname,
		int	flags
	)

Target unlinkat() handler.

Definition at line 1024 of file syscall_emul.hh.

References flags, rmdirImpl(), and unlinkImpl().

unlinkFunc()

SyscallReturn gem5::unlinkFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname
	)

Target unlink() handler.

Definition at line 348 of file syscall_emul.cc.

References unlinkImpl().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32(), and gem5::ArmISA::SyscallTable64::SyscallTable64().

unlinkImpl()

SyscallReturn gem5::unlinkImpl	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		std::string	path
	)

Definition at line 358 of file syscall_emul.cc.

References gem5::Process::checkPathRedirect(), gem5::ThreadContext::getProcessPtr(), and gem5::MipsISA::p.

Referenced by unlinkatFunc(), and unlinkFunc().

unserialize()

void gem5::unserialize	(	ThreadContext &	tc,
		CheckpointIn &	cp
	)

Definition at line 222 of file thread_context.cc.

References arrayParamIn(), gem5::PCStateBase::clone(), gem5::ThreadContext::getIsaPtr(), MiscRegClass, gem5::ThreadContext::pcState(), gem5::BaseISA::regClasses(), and gem5::ThreadContext::setReg().

Referenced by gem5::o3::ThreadState::unserialize(), and gem5::SimpleThread::unserialize().

updateKvmStateFPUCommon()

template<typename T >

static void gem5::updateKvmStateFPUCommon ( ThreadContext *  tc, T &  fpu  )

static

Definition at line 874 of file x86_cpu.cc.

References bitsToFloat64(), gem5::X86ISA::convX87TagsToXTags(), DPRINTF, gem5::X86ISA::misc_reg::Fcw, gem5::X86ISA::misc_reg::Fop, gem5::X86ISA::float_reg::fpr(), gem5::X86ISA::misc_reg::Fsw, gem5::X86ISA::misc_reg::Ftw, gem5::ThreadContext::getReg(), gem5::ArmISA::i, gem5::X86ISA::misc_reg::Mxcsr, gem5::ThreadContext::readMiscReg(), gem5::ThreadContext::readMiscRegNoEffect(), gem5::X86ISA::storeFloat80(), gem5::X86ISA::float_reg::xmmHigh(), and gem5::X86ISA::float_reg::xmmLow().

Referenced by gem5::X86KvmCPU::updateKvmStateFPULegacy(), and gem5::X86KvmCPU::updateKvmStateFPUXSave().

updateThreadContextFPUCommon()

template<typename T >

static void gem5::updateThreadContextFPUCommon ( ThreadContext *  tc, const T &  fpu  )

static

Definition at line 1126 of file x86_cpu.cc.

References gem5::X86ISA::convX87XTagsToTags(), DPRINTF, gem5::X86ISA::misc_reg::Fcw, floatToBits64(), gem5::X86ISA::misc_reg::Fop, gem5::X86ISA::float_reg::fpr(), gem5::X86ISA::misc_reg::Fsw, gem5::X86ISA::misc_reg::Ftag, gem5::X86ISA::misc_reg::Ftw, gem5::ArmISA::i, gem5::X86ISA::loadFloat80(), gem5::X86ISA::misc_reg::Mxcsr, gem5::ThreadContext::setMiscRegNoEffect(), gem5::ThreadContext::setReg(), gem5::X86ISA::misc_reg::X87Top, gem5::X86ISA::float_reg::xmmHigh(), and gem5::X86ISA::float_reg::xmmLow().

Referenced by gem5::X86KvmCPU::updateThreadContextFPU(), and gem5::X86KvmCPU::updateThreadContextXSave().

utimesFunc()

template<class OS >

SyscallReturn gem5::utimesFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr<>	pathname,
		VPtr< typename OS::timeval[2]>	tp
	)

Target utimes() handler.

Definition at line 2339 of file syscall_emul.hh.

wait4Func()

template<class OS >

SyscallReturn gem5::wait4Func	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		pid_t	pid,
		VPtr<>	statPtr,
		int	options,
		VPtr<>	rusagePtr
	)

Currently, wait4 is only implemented so that it will wait for children exit conditions which are denoted by a SIGCHLD signals posted into the system signal list. We return no additional information via any of the parameters supplied to wait4. If nothing is found in the system signal list, we will wait indefinitely for SIGCHLD to post by retrying the call.

Definition at line 2860 of file syscall_emul.hh.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyOut(), DPRINTF_SYSCALL, gem5::ThreadContext::getProcessPtr(), gem5::ThreadContext::getSystemPtr(), gem5::MipsISA::p, gem5::SyscallReturn::retry(), and gem5::System::signalList.

warnUnsupportedOS()

void gem5::warnUnsupportedOS

(

std::string

syscall_name

)

Definition at line 71 of file syscall_emul.cc.

References warn.

Referenced by eventfdFunc(), fallocateFunc(), schedGetaffinityFunc(), and statfsFunc().

writeFunc()

template<class OS >

SyscallReturn gem5::writeFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr<>	buf_ptr,
		typename OS::size_t	nbytes
	)

We don't want to poll on /dev/random. The kernel will not enable the file descriptor for writing unless the entropy in the system falls below write_wakeup_threshold. This is not guaranteed to happen depending on host settings.

Definition at line 2821 of file syscall_emul.hh.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), gem5::ThreadContext::getProcessPtr(), gem5::MipsISA::p, and gem5::SyscallReturn::retry().

writeMemAtomic() [1/3]

template<ByteOrder Order, class XC , class MemT >

Fault gem5::writeMemAtomic	(	XC *	xc,
		trace::InstRecord *	traceData,
		const MemT &	mem,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res
	)

Definition at line 249 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, gtoh(), htog(), mem, gem5::Request::MEM_SWAP, gem5::Request::MEM_SWAP_COND, NoFault, gem5::trace::InstRecord::setData(), and writeMemAtomic().

writeMemAtomic() [2/3]

template<ByteOrder Order, class XC , class MemT >

Fault gem5::writeMemAtomic	(	XC *	xc,
		trace::InstRecord *	traceData,
		const MemT &	mem,
		Addr	addr,
		size_t	size,
		Request::Flags	flags,
		uint64_t *	res
	)

Definition at line 270 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, gtoh(), htog(), mem, gem5::Request::MEM_SWAP, gem5::Request::MEM_SWAP_COND, NoFault, gem5::trace::InstRecord::setData(), and writeMemAtomic().

writeMemAtomic() [3/3]

template<class XC >

Fault gem5::writeMemAtomic	(	XC *	xc,
		uint8_t *	mem,
		Addr	addr,
		std::size_t	size,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable
	)

Write to memory in atomic mode.

Definition at line 240 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, and mem.

Referenced by writeMemAtomic(), and writeMemAtomic().

writeMemAtomicBE()

template<class XC , class MemT >

Fault gem5::writeMemAtomicBE	(	XC *	xc,
		trace::InstRecord *	traceData,
		const MemT &	mem,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res
	)

Definition at line 309 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, and mem.

writeMemAtomicLE() [1/2]

template<class XC , class MemT >

Fault gem5::writeMemAtomicLE	(	XC *	xc,
		trace::InstRecord *	traceData,
		const MemT &	mem,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res
	)

Definition at line 291 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, and mem.

writeMemAtomicLE() [2/2]

template<class XC , class MemT >

Fault gem5::writeMemAtomicLE	(	XC *	xc,
		trace::InstRecord *	traceData,
		const MemT &	mem,
		size_t	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res
	)

Definition at line 300 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, and mem.

writeMemTiming() [1/3]

template<ByteOrder Order, class XC , class MemT >

Fault gem5::writeMemTiming	(	XC *	xc,
		trace::InstRecord *	traceData,
		MemT	mem,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res
	)

Definition at line 184 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, htog(), mem, gem5::trace::InstRecord::setData(), and writeMemTiming().

writeMemTiming() [2/3]

template<ByteOrder Order, class XC , class MemT >

Fault gem5::writeMemTiming	(	XC *	xc,
		trace::InstRecord *	traceData,
		MemT	mem,
		Addr	addr,
		size_t	size,
		Request::Flags	flags,
		uint64_t *	res
	)

Definition at line 198 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, htog(), mem, gem5::trace::InstRecord::setData(), and writeMemTiming().

writeMemTiming() [3/3]

template<class XC >

Fault gem5::writeMemTiming	(	XC *	xc,
		uint8_t *	mem,
		Addr	addr,
		std::size_t	size,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable
	)

Write to memory in timing mode.

Definition at line 175 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, and mem.

Referenced by writeMemTiming(), and writeMemTiming().

writeMemTimingBE()

template<class XC , class MemT >

Fault gem5::writeMemTimingBE	(	XC *	xc,
		trace::InstRecord *	traceData,
		MemT	mem,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res
	)

Definition at line 230 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, and mem.

writeMemTimingLE() [1/2]

template<class XC , class MemT >

Fault gem5::writeMemTimingLE	(	XC *	xc,
		trace::InstRecord *	traceData,
		MemT	mem,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res
	)

Definition at line 212 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, and mem.

writeMemTimingLE() [2/2]

template<class XC , class MemT >

Fault gem5::writeMemTimingLE	(	XC *	xc,
		trace::InstRecord *	traceData,
		MemT	mem,
		Addr	addr,
		size_t	size,
		Request::Flags	flags,
		uint64_t *	res
	)

Definition at line 221 of file memhelpers.hh.

References gem5::X86ISA::addr, flags, and mem.

writeOutField()

template<class T >

uint8_t gem5::writeOutField	(	PortProxy &	proxy,
		Addr	addr,
		T	val
	)

Definition at line 72 of file intelmp.cc.

References gem5::X86ISA::addr, htole(), gem5::X86ISA::val, and gem5::PortProxy::writeBlob().

Referenced by gem5::X86ISA::intelmp::FloatingPointer::writeOut(), gem5::X86ISA::intelmp::ConfigTable::writeOut(), gem5::X86ISA::intelmp::Processor::writeOut(), gem5::X86ISA::intelmp::Bus::writeOut(), gem5::X86ISA::intelmp::IOAPIC::writeOut(), gem5::X86ISA::intelmp::IntAssignment::writeOut(), gem5::X86ISA::intelmp::AddrSpaceMapping::writeOut(), gem5::X86ISA::intelmp::BusHierarchy::writeOut(), and gem5::X86ISA::intelmp::CompatAddrSpaceMod::writeOut().

writeOutString()

uint8_t gem5::writeOutString	(	PortProxy &	proxy,
		Addr	addr,
		std::string	str,
		int	length
	)

Definition at line 86 of file intelmp.cc.

References gem5::X86ISA::addr, gem5::ArmISA::i, warn, and gem5::PortProxy::writeBlob().

Referenced by gem5::X86ISA::intelmp::ConfigTable::writeOut(), and gem5::X86ISA::intelmp::Bus::writeOut().

writePng()

static void gem5::writePng ( png_structp  pngPtr, png_bytep  data, png_size_t  length  )

static

Write callback to use with libpng APIs.

Parameters

pngPtr	pointer to the png_struct structure
data	pointer to the data being written
length	number of bytes being written

Definition at line 67 of file pngwriter.cc.

References data.

Referenced by gem5::PngWriter::write().

writeVal()

template<class T >

void gem5::writeVal	(	T	val,
		PortProxy &	proxy,
		Addr &	addr
	)

Definition at line 49 of file e820.cc.

References gem5::X86ISA::addr, htole(), gem5::X86ISA::val, and gem5::PortProxy::writeBlob().

Referenced by gem5::X86ISA::E820Table::writeTo().

writevFunc()

template<class OS >

SyscallReturn gem5::writevFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	tgt_fd,
		VPtr<>	tiov_base,
		typename OS::size_t	count
	)

Target writev() handler.

Definition at line 1960 of file syscall_emul.hh.

References gem5::X86ISA::count, gem5::ThreadContext::getProcessPtr(), gtoh(), gem5::ArmISA::i, gem5::MipsISA::p, and gem5::PortProxy::readBlob().

Variable Documentation

_curEventQueue

__thread EventQueue * gem5::_curEventQueue = NULL

The current event queue for the running thread.

Access to this queue does not require any locking from the thread.

Definition at line 58 of file eventq.cc.

Referenced by curEventQueue().

_py_tracers

EmbeddedPyBind gem5::_py_tracers("trace", pybind_init_tracers) ( "trace"  , pybind_init_tracers    )

static

AmbaVendor

const uint64_t gem5::AmbaVendor = 0xb105f00d00000000ULL

Definition at line 52 of file amba_device.cc.

AMDGPU_VM_COUNT

constexpr int gem5::AMDGPU_VM_COUNT = 16

staticconstexpr

Definition at line 63 of file amdgpu_defines.hh.

Referenced by gem5::AMDGPUDevice::allocateVMID(), gem5::AMDGPUVM::AMDGPUVM(), gem5::AMDGPUVM::serialize(), and gem5::AMDGPUVM::unserialize().

amx

Bitfield<18, 17> gem5::amx

Definition at line 135 of file x86_cpu.cc.

asid16

Bitfield<12> gem5::asid16

Definition at line 119 of file smmu_v3_defs.hh.

async_event

volatile bool gem5::async_event = false

Some asynchronous event has happened.

Definition at line 32 of file async.cc.

Referenced by doSimLoop(), dumprstStatsHandler(), dumpStatsHandler(), exitNowHandler(), ioHandler(), and gem5::PollQueue::setupAsyncIO().

async_exception

volatile bool gem5::async_exception = false

Python exception.

Definition at line 37 of file async.cc.

Referenced by doSimLoop().

async_exit

volatile bool gem5::async_exit = false

Async request to exit simulator.

Definition at line 35 of file async.cc.

Referenced by doSimLoop(), and exitNowHandler().

async_io

volatile bool gem5::async_io = false

Async I/O request (SIGIO).

Definition at line 36 of file async.cc.

Referenced by doSimLoop(), ioHandler(), and gem5::PollQueue::setupAsyncIO().

async_statdump

volatile bool gem5::async_statdump = false

Async request to dump stats.

Definition at line 33 of file async.cc.

Referenced by doSimLoop(), dumprstStatsHandler(), and dumpStatsHandler().

async_statreset

volatile bool gem5::async_statreset = false

Async request to reset stats.

Definition at line 34 of file async.cc.

Referenced by doSimLoop(), and dumprstStatsHandler().

atos

Bitfield<15> gem5::atos

Definition at line 122 of file smmu_v3_defs.hh.

ats

Bitfield<10> gem5::ats

Definition at line 117 of file smmu_v3_defs.hh.

Referenced by gem5::SMMUTranslRequest::fromPacket().

atsRecErr

Bitfield<23> gem5::atsRecErr

Definition at line 129 of file smmu_v3_defs.hh.

avx

Bitfield<2> gem5::avx

Definition at line 124 of file x86_cpu.cc.

avx512

Bitfield<7, 5> gem5::avx512

Definition at line 126 of file x86_cpu.cc.

btm

Bitfield<5> gem5::btm

Definition at line 113 of file smmu_v3_defs.hh.

c2

gem5::c2 = 31

Definition at line 174 of file intmath.hh.

CACHE_LINE_BITS

const int gem5::CACHE_LINE_BITS = 6

Definition at line 51 of file Check.hh.

Referenced by gem5::Check::initiateAction(), gem5::Check::initiateCheck(), gem5::Check::initiateFlush(), gem5::Check::initiatePrefetch(), and gem5::Check::performCallback().

CCRegClassName

constexpr char gem5::CCRegClassName[] = "condition_code"

inlineconstexpr

Definition at line 81 of file reg_class.hh.

cd2l

Bitfield<19> gem5::cd2l

Definition at line 126 of file smmu_v3_defs.hh.

cet

Bitfield<12, 11> gem5::cet

Definition at line 130 of file x86_cpu.cc.

CHECK_SIZE

const int gem5::CHECK_SIZE = (1 << CHECK_SIZE_BITS)

Definition at line 50 of file Check.hh.

Referenced by gem5::CheckTable::addCheck(), gem5::CheckTable::CheckTable(), gem5::Check::initiateCheck(), gem5::Check::initiateFlush(), and gem5::Check::performCallback().

CHECK_SIZE_BITS

const int gem5::CHECK_SIZE_BITS = 2

Definition at line 49 of file Check.hh.

Referenced by gem5::CheckTable::addCheck().

ckptCount

int gem5::ckptCount = 0

Definition at line 59 of file serialize.cc.

ckptMaxCount

int gem5::ckptMaxCount = 0

Definition at line 58 of file serialize.cc.

ckptPrevCount

int gem5::ckptPrevCount = -1

Definition at line 60 of file serialize.cc.

cohacc

Bitfield<4> gem5::cohacc

Definition at line 112 of file smmu_v3_defs.hh.

DOORBELL_BAR

constexpr int gem5::DOORBELL_BAR = 2

constexpr

Definition at line 67 of file amdgpu_defines.hh.

Referenced by gem5::AMDGPUDevice::read(), gem5::AMDGPUDevice::readDoorbell(), and gem5::AMDGPUDevice::write().

dormhint

Bitfield<8> gem5::dormhint

Definition at line 115 of file smmu_v3_defs.hh.

dummyFault1

Fault gem5::dummyFault1 = std::make_shared<gem5::FaultBase>()

Definition at line 51 of file translation_gen.test.cc.

Referenced by operator<<(), TEST(), TEST(), TEST(), and TEST().

dummyFault2

Fault gem5::dummyFault2 = std::make_shared<gem5::FaultBase>()

Definition at line 52 of file translation_gen.test.cc.

Referenced by operator<<(), and TEST().

EEPROM_PMATCH0_ADDR

const uint8_t gem5::EEPROM_PMATCH0_ADDR = 0xC

Definition at line 59 of file ns_gige.hh.

Referenced by gem5::NSGigE::eepromKick().

EEPROM_PMATCH1_ADDR

const uint8_t gem5::EEPROM_PMATCH1_ADDR = 0xB

Definition at line 58 of file ns_gige.hh.

Referenced by gem5::NSGigE::eepromKick().

EEPROM_PMATCH2_ADDR

const uint8_t gem5::EEPROM_PMATCH2_ADDR = 0xA

Definition at line 57 of file ns_gige.hh.

Referenced by gem5::NSGigE::eepromKick().

EEPROM_READ

const uint8_t gem5::EEPROM_READ = 0x2

Definition at line 55 of file ns_gige.hh.

Referenced by gem5::NSGigE::eepromKick().

EEPROM_SIZE

const uint8_t gem5::EEPROM_SIZE = 64

Definition at line 56 of file ns_gige.hh.

eventqIrqEn

Bitfield<2> gem5::eventqIrqEn

Definition at line 138 of file smmu_v3_defs.hh.

FHASH_ADDR

const uint16_t gem5::FHASH_ADDR = 0x100

Definition at line 51 of file ns_gige.hh.

Referenced by gem5::NSGigE::read(), and gem5::NSGigE::write().

FHASH_SIZE

const uint16_t gem5::FHASH_SIZE = 0x100

Definition at line 52 of file ns_gige.hh.

Referenced by gem5::NSGigE::read(), gem5::NSGigE::serialize(), gem5::NSGigE::unserialize(), and gem5::NSGigE::write().

FloatAddOp

const OpClass gem5::FloatAddOp = enums::FloatAdd

static

Definition at line 59 of file op_class.hh.

FloatCmpOp

const OpClass gem5::FloatCmpOp = enums::FloatCmp

static

Definition at line 60 of file op_class.hh.

FloatCvtOp

const OpClass gem5::FloatCvtOp = enums::FloatCvt

static

Definition at line 61 of file op_class.hh.

FloatDivOp

const OpClass gem5::FloatDivOp = enums::FloatDiv

static

Definition at line 64 of file op_class.hh.

FloatMemReadOp

const OpClass gem5::FloatMemReadOp = enums::FloatMemRead

static

Definition at line 109 of file op_class.hh.

FloatMemWriteOp

const OpClass gem5::FloatMemWriteOp = enums::FloatMemWrite

static

Definition at line 110 of file op_class.hh.

FloatMiscOp

const OpClass gem5::FloatMiscOp = enums::FloatMisc

static

Definition at line 65 of file op_class.hh.

FloatMultAccOp

const OpClass gem5::FloatMultAccOp = enums::FloatMultAcc

static

Definition at line 63 of file op_class.hh.

FloatMultOp

const OpClass gem5::FloatMultOp = enums::FloatMult

static

Definition at line 62 of file op_class.hh.

FloatRegClassName

constexpr char gem5::FloatRegClassName[] = "floating_point"

inlineconstexpr

Definition at line 76 of file reg_class.hh.

FloatSqrtOp

const OpClass gem5::FloatSqrtOp = enums::FloatSqrt

static

Definition at line 66 of file op_class.hh.

FRAMEBUFFER_BAR

constexpr int gem5::FRAMEBUFFER_BAR = 0

constexpr

Definition at line 66 of file amdgpu_defines.hh.

Referenced by gem5::AMDGPUDevice::read(), and gem5::AMDGPUDevice::write().

FullSystem

bool gem5::FullSystem

The FullSystem variable can be used to determine the current mode of simulation.

Definition at line 220 of file root.cc.

Referenced by gem5::ArmISA::RemoteGDB::acc(), gem5::pseudo_inst::addsymbol(), gem5::BaseSimpleCPU::BaseSimpleCPU(), gem5::minor::Execute::checkInterrupts(), gem5::BaseCPU::checkInterrupts(), gem5::o3::Commit::commit(), gem5::GPUCommandProcessor::dispatchKernelObject(), gem5::X86ISA::TLB::finalizePhysical(), gem5::guest_abi::Argument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::get(), gem5::ArmSystem::getArmSystem(), gem5::ArmISA::ISA::getCurSmeVecLenInBits(), gem5::ArmISA::ISA::getCurSveVecLenInBits(), gem5::ArmSystem::has(), gem5::minor::Execute::hasInterrupt(), gem5::ArmSystem::haveSemihosting(), gem5::ArmISA::MiscRegLUTEntryInitializer::highest(), gem5::ArmSystem::highestEL(), gem5::ArmSystem::highestELIs64(), gem5::ruby::RubyPort::init(), gem5::X86ISA::TLB::insert(), gem5::o3::CPU::insertThread(), gem5::RiscvISA::RiscvFault::invoke(), gem5::MipsISA::MipsFaultBase::invoke(), gem5::MipsISA::ResetFault::invoke(), gem5::MipsISA::CoprocessorUnusableFault::invoke(), gem5::MipsISA::AddressFault< T >::invoke(), gem5::MipsISA::TlbFault< T >::invoke(), gem5::SparcISA::SparcFaultBase::invoke(), gem5::SparcISA::FastInstructionAccessMMUMiss::invoke(), gem5::SparcISA::FastDataAccessMMUMiss::invoke(), gem5::SparcISA::SpillNNormal::invoke(), gem5::SparcISA::FillNNormal::invoke(), gem5::SparcISA::TrapInstruction::invoke(), gem5::X86ISA::PageFault::invoke(), gem5::FaultBase::invoke(), gem5::ArmISA::Reset::invoke(), gem5::ArmISA::UndefinedInstruction::invoke(), gem5::ArmISA::SupervisorCall::invoke(), gem5::ArmISA::SecureMonitorCall::invoke(), gem5::ArmISA::ArmSev::invoke(), gem5::X86ISA::X86FaultBase::invoke(), gem5::X86ISA::InvalidOpcode::invoke(), gem5::GenericPageTableFault::invoke(), gem5::ArmISA::ArmFault::invoke32(), gem5::GPUComputeDriver::ioctl(), gem5::ArmISA::ISA::ISA(), gem5::MinorCPU::MinorCPU(), gem5::ArmISA::MMU::MMU(), gem5::NonCachingSimpleCPU::NonCachingSimpleCPU(), gem5::ArmSemihosting::portProxyImpl(), gem5::RiscvSemihosting::portProxyImpl(), gem5::BaseSimpleCPU::postExecute(), gem5::BaseCPU::postInterrupt(), gem5::ComputeUnit::DataPort::processMemRespEvent(), gem5::BaseRemoteGDB::readBlob(), gem5::pseudo_inst::readfile(), gem5::trace::TarmacParserRecord::readMemNoEffect(), gem5::ruby::RubyPort::PioRequestPort::recvRangeChange(), gem5::BaseCPU::registerThreadContexts(), gem5::X86ISA::Interrupts::requestInterrupt(), gem5::ArmISA::resetCPSR(), gem5::GPUCommandProcessor::sendCompletionSignal(), gem5::ComputeUnit::sendRequest(), gem5::Root::serialize(), gem5::GPUComputeDriver::setMtype(), gem5::CheckerCPU::setSystem(), gem5::o3::Decode::squash(), gem5::GPUCommandProcessor::submitDispatchPkt(), takeOverFrom(), gem5::o3::CPU::tick(), gem5::o3::Fetch::tick(), gem5::trace::ExeTracerRecord::traceInst(), gem5::HSAPacketProcessor::translate(), gem5::GPUCommandProcessor::translate(), gem5::RiscvISA::TLB::translate(), gem5::X86ISA::TLB::translate(), gem5::X86ISA::GpuTLB::translate(), gem5::ArmISA::MMU::translateAtomic(), gem5::ArmISA::MMU::translateComplete(), gem5::SparcISA::TLB::translateFunctional(), gem5::X86ISA::TLB::translateFunctional(), gem5::ArmISA::MMU::translateFunctional(), gem5::GPUCommandProcessor::updateHsaSignal(), gem5::Checker< DynInstPtr >::verify(), gem5::ComputeUnit::vramRequestorId(), gem5::BaseRemoteGDB::writeBlob(), and gem5::pseudo_inst::writefile().

FullSystemInt

unsigned int gem5::FullSystemInt

In addition to the boolean flag we make use of an unsigned int since the CPU instruction decoder makes use of the variable in switch statements.

A value of 0 signifies syscall emulation, and any other value full system.

Definition at line 221 of file root.cc.

GDBBadP

const char gem5::GDBBadP = '-'

static

Definition at line 169 of file remote_gdb.cc.

Referenced by gem5::BaseRemoteGDB::recv(), and gem5::BaseRemoteGDB::send().

GDBEnd

const char gem5::GDBEnd = '#'

static

Definition at line 167 of file remote_gdb.cc.

Referenced by gem5::BaseRemoteGDB::recv(), and gem5::BaseRemoteGDB::send().

GDBGoodP

const char gem5::GDBGoodP = '+'

static

Definition at line 168 of file remote_gdb.cc.

Referenced by gem5::BaseRemoteGDB::recv().

GDBStart

const char gem5::GDBStart = '$'

static

Definition at line 166 of file remote_gdb.cc.

Referenced by gem5::BaseRemoteGDB::recv(), and gem5::BaseRemoteGDB::send().

global_exit_event

GlobalSimLoopExitEvent* gem5::global_exit_event = nullptr

Simulate for num_cycles additional cycles.

If num_cycles is -1 (the default), we simulate to MAX_TICKS unless the max ticks has been set via the 'set_max_tick' function prior. This function is exported to Python.

Returns

The SimLoopExitEvent that caused the loop to exit.

Definition at line 187 of file simulate.cc.

Referenced by simulate().

gpuTypeMap

const std::map<enums::NoMaliGpuType, nomali_gpu_type_t> gem5::gpuTypeMap

static

Initial value:

{
    { enums::T60x, NOMALI_GPU_T60X },
    { enums::T62x, NOMALI_GPU_T62X },
    { enums::T760, NOMALI_GPU_T760 },
}

Definition at line 52 of file gpu_nomali.cc.

GRBM_OFFSET_SHIFT

constexpr uint32_t gem5::GRBM_OFFSET_SHIFT = 2

staticconstexpr

Definition at line 76 of file amdgpu_defines.hh.

Referenced by gem5::AMDGPUDevice::readMMIO(), and gem5::AMDGPUDevice::writeMMIO().

gtestLogOutput

thread_local GTestLogOutput gem5::gtestLogOutput

Definition at line 33 of file logging.cc.

Referenced by LoggingFixture::SetUp(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), and TEST_F().

hdc

Bitfield<13> gem5::hdc

Definition at line 131 of file x86_cpu.cc.

high

gem5::high = AB + c2

Definition at line 176 of file intmath.hh.

Referenced by gem5::BaseSemihosting::callElapsed32(), gem5::ArmISA::FpOp::dbl(), gem5::guest_abi::Argument< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer) > sizeof(uint32_t)) > >::get(), gem5::guest_abi::Argument< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer) > 8)> >::get(), gem5::guest_abi::Argument< ABI, Arg, typename std::enable_if_t< std::is_base_of_v< ArmISA::RegABI32, ABI > &&std::is_integral_v< Arg > &&ABI::template IsWideV< Arg > > >::get(), gem5::guest_abi::Argument< ABI, Arg, typename std::enable_if_t< std::is_base_of_v< RiscvISA::RegABI32, ABI > &&std::is_integral_v< Arg > &&ABI::template IsWideV< Arg > > >::get(), gem5::guest_abi::Argument< SparcISA::SEWorkload::SyscallABI32, Arg, typename std::enable_if_t< std::is_integral_v< Arg > &&SparcISA::SEWorkload::SyscallABI32::IsWideV< Arg > > >::get(), gem5::guest_abi::Argument< X86ISA::EmuLinux::SyscallABI32, Arg, typename std::enable_if_t< std::is_integral_v< Arg > &&X86ISA::EmuLinux::SyscallABI32::IsWideV< Arg > > >::get(), gem5::X86ISA::X86_64Process::initState(), gem5::ArmISA::makeDouble(), gem5::GenericSyscallABI32::mergeRegs(), mulSigned(), mulSignedManual(), mulUnsigned(), gem5::statistics::DistPrint::operator()(), gem5::KvmKernelGic::setIntState(), gem5::KvmVM::setIRQLine(), and gem5::X86ISA::Interrupts::setReg().

HostByteOrder

const ByteOrder gem5::HostByteOrder = ByteOrder::big

Definition at line 171 of file byteswap.hh.

Referenced by gem5::RegClassOps::valString().

hostname

const char* gem5::hostname = "m5.eecs.umich.edu"

Definition at line 335 of file syscall_emul.cc.

Referenced by gethostnameFunc().

hostSeconds

statistics::Value & gem5::hostSeconds = rootStats.hostSeconds

Definition at line 48 of file stats.cc.

Referenced by gem5::BaseCPU::GlobalStats::GlobalStats().

httu

Bitfield<7, 6> gem5::httu

Definition at line 114 of file smmu_v3_defs.hh.

hwp

Bitfield<16> gem5::hwp

Definition at line 134 of file x86_cpu.cc.

hyp

Bitfield<9> gem5::hyp

Definition at line 116 of file smmu_v3_defs.hh.

Referenced by gem5::ArmISA::MiscRegLUTEntryInitializer::highest(), and gem5::ArmISA::TableWalker::walk().

IH_OFFSET_SHIFT

constexpr uint32_t gem5::IH_OFFSET_SHIFT = 2

staticconstexpr

Definition at line 75 of file amdgpu_defines.hh.

Referenced by gem5::AMDGPUDevice::writeMMIO().

image_file

const uint8_t gem5::image_file[]

This image file contains the text "This is a test image.\n" 31 times.

Definition at line 40 of file small_image_file.test.hh.

Referenced by TEST(), and TEST().

image_file_gzipped

const uint8_t gem5::image_file_gzipped[]

Initial value:

= {
    0x1f, 0x8b, 0x08, 0x08, 0x48, 0x4b, 0xcb, 0x5d,
    0x00, 0x03, 0x62, 0x6c, 0x61, 0x2e, 0x69, 0x6d,
    0x67, 0x00, 0x0b, 0xc9, 0xc8, 0x2c, 0x56, 0x00,
    0xa2, 0x44, 0x85, 0x92, 0xd4, 0xe2, 0x12, 0x85,
    0xcc, 0xdc, 0xc4, 0xf4, 0x54, 0x3d, 0xae, 0x90,
    0x51, 0xd1, 0x51, 0xd1, 0x41, 0x26, 0x0a, 0x00,
    0xc9, 0x58, 0x6c, 0x4e, 0xaa, 0x02, 0x00, 0x00
}

This is "image_file" compressed using GZip.

Definition at line 132 of file small_image_file.test.hh.

Referenced by TEST().

inParallelMode

bool gem5::inParallelMode = false

Current mode of execution: parallel / serial.

Definition at line 59 of file eventq.cc.

Referenced by gem5::EventQueue::deschedule(), gem5::EventQueue::reschedule(), gem5::EventQueue::schedule(), and simulate().

InstPrefetchOp

const OpClass gem5::InstPrefetchOp = enums::InstPrefetch

static

Definition at line 128 of file op_class.hh.

IntAluOp

const OpClass gem5::IntAluOp = enums::IntAlu

static

Definition at line 56 of file op_class.hh.

IntCtlAddr

const Addr gem5::IntCtlAddr = 0x0400

Definition at line 47 of file iob.hh.

Referenced by gem5::Iob::readIob(), and gem5::Iob::writeIob().

IntCtlMask

const uint64_t gem5::IntCtlMask = 0x00006

Definition at line 66 of file iob.hh.

IntCtlSize

const Addr gem5::IntCtlSize = 0x0020

Definition at line 48 of file iob.hh.

Referenced by gem5::Iob::readIob(), and gem5::Iob::writeIob().

IntDivOp

const OpClass gem5::IntDivOp = enums::IntDiv

static

Definition at line 58 of file op_class.hh.

IntManAddr

const Addr gem5::IntManAddr = 0x0000

Definition at line 45 of file iob.hh.

Referenced by gem5::Iob::readIob(), and gem5::Iob::writeIob().

IntManMask

const uint64_t gem5::IntManMask = 0x01F3F

Definition at line 65 of file iob.hh.

IntManSize

const Addr gem5::IntManSize = 0x0020

Definition at line 46 of file iob.hh.

Referenced by gem5::Iob::readIob(), and gem5::Iob::writeIob().

IntMultOp

const OpClass gem5::IntMultOp = enums::IntMult

static

Definition at line 57 of file op_class.hh.

INTR_COOKIE_SIZE

constexpr uint32_t gem5::INTR_COOKIE_SIZE = 32

constexpr

MSI-style interrupts.

Send a "cookie" response to clear interrupts. From [1] we know the size of the struct is 8 dwords. Then we can look at the register shift offsets in [2] to guess the rest. Or we can also look at [3].

[1] https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/ drivers/gpu/drm/amd/amdkfd/kfd_device.c#L316 [2] https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/ drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h#L122 [3] https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h#L46

Definition at line 89 of file interrupt_handler.hh.

IntRegClassName

constexpr char gem5::IntRegClassName[] = "integer"

inlineconstexpr

Definition at line 75 of file reg_class.hh.

IntVecDis

const uint64_t gem5::IntVecDis = 0x31F3F

Definition at line 68 of file iob.hh.

IntVecDisAddr

const Addr gem5::IntVecDisAddr = 0x0800

Definition at line 50 of file iob.hh.

Referenced by gem5::Iob::writeIob().

IntVecDisSize

const Addr gem5::IntVecDisSize = 0x0100

Definition at line 51 of file iob.hh.

Referenced by gem5::Iob::writeIob().

InvalidContextID

const ContextID gem5::InvalidContextID = (ContextID)-1

Definition at line 240 of file types.hh.

Referenced by gem5::memory::AbstractMemory::checkLockedAddrList(), gem5::ruby::Sequencer::issueRequest(), and gem5::memory::LockedAddr::matchesContext().

InvalidPortID

const PortID gem5::InvalidPortID = (PortID)-1

Definition at line 246 of file types.hh.

Referenced by gem5::BaseXBar::findPort(), gem5::CoherentXBar::forwardAtomic(), gem5::CoherentXBar::forwardAtomic(), gem5::CoherentXBar::forwardFunctional(), gem5::CoherentXBar::forwardTiming(), gem5::fastmodel::CortexR52::getPort(), gem5::fastmodel::CortexR52Cluster::getPort(), gem5::ArmSigInterruptPinGen::getPort(), gem5::SimpleCache::getPort(), gem5::SimpleMemobj::getPort(), gem5::SnoopFilter::portToMask(), gem5::CoherentXBar::recvAtomicBackdoor(), gem5::CoherentXBar::recvAtomicSnoop(), gem5::CoherentXBar::recvFunctionalSnoop(), gem5::CoherentXBar::recvTimingReq(), gem5::CoherentXBar::recvTimingResp(), gem5::NoncoherentXBar::recvTimingResp(), gem5::CoherentXBar::recvTimingSnoopReq(), gem5::CoherentXBar::recvTimingSnoopResp(), and gem5::SnoopFilter::setCPUSidePorts().

InvalidThreadID

const ThreadID gem5::InvalidThreadID = (ThreadID)-1

Definition at line 236 of file types.hh.

Referenced by gem5::o3::Fetch::branchCount(), gem5::minor::Execute::checkInterrupts(), gem5::o3::Fetch::doSquash(), gem5::o3::Fetch::drainSanityCheck(), gem5::minor::Decode::evaluate(), gem5::minor::Execute::evaluate(), gem5::minor::Fetch1::evaluate(), gem5::minor::Fetch2::evaluate(), gem5::o3::Commit::executingHtmTransaction(), gem5::o3::Fetch::fetch(), gem5::o3::Fetch::finishTranslation(), gem5::minor::Execute::getCommittingThread(), gem5::o3::Commit::getCommittingThread(), gem5::o3::Fetch::getFetchingThread(), gem5::o3::CPU::getFreeTid(), gem5::minor::Execute::getIssuingThread(), gem5::o3::LSQ::getLatestHtmUid(), gem5::minor::Decode::getScheduledThread(), gem5::minor::Fetch1::getScheduledThread(), gem5::minor::Fetch2::getScheduledThread(), gem5::o3::Fetch::iqCount(), gem5::o3::Fetch::lsqCount(), gem5::o3::LSQ::numHtmStarts(), gem5::o3::LSQ::numHtmStops(), gem5::o3::Commit::oldestReady(), gem5::MipsISA::readRegOtherThread(), gem5::o3::Fetch::recvReqRetry(), gem5::o3::LSQ::resetHtmStartsStops(), gem5::o3::Commit::resetHtmStartsStops(), gem5::o3::Commit::roundRobin(), gem5::o3::Fetch::roundRobin(), gem5::o3::LSQ::setLastRetiredHtmUid(), and gem5::MipsISA::setRegOtherThread().

invariant_reg_vector

uint64_t gem5::invariant_reg_vector[]

static

Definition at line 243 of file arm_cpu.cc.

IprAccessOp

const OpClass gem5::IprAccessOp = enums::IprAccess

static

Definition at line 127 of file op_class.hh.

is_iterable_v

template<typename T >

constexpr bool gem5::is_iterable_v = is_iterable<T>::value

constexpr

Definition at line 106 of file type_traits.hh.

is_std_hash_enabled_v

template<typename T >

constexpr bool gem5::is_std_hash_enabled_v = is_std_hash_enabled<T>::value

constexpr

Definition at line 117 of file type_traits.hh.

JIntABusyAddr

const Addr gem5::JIntABusyAddr = 0x0B00

Definition at line 61 of file iob.hh.

Referenced by gem5::Iob::readJBus(), and gem5::Iob::writeJBus().

JIntBusyAddr

const Addr gem5::JIntBusyAddr = 0x0900

Definition at line 59 of file iob.hh.

Referenced by gem5::Iob::readJBus(), and gem5::Iob::writeJBus().

JIntBusyMask

const uint64_t gem5::JIntBusyMask = 0x0003F

Definition at line 69 of file iob.hh.

JIntBusySize

const Addr gem5::JIntBusySize = 0x0100

Definition at line 60 of file iob.hh.

Referenced by gem5::Iob::readJBus(), and gem5::Iob::writeJBus().

JIntData0Addr

const Addr gem5::JIntData0Addr = 0x0400

Definition at line 55 of file iob.hh.

Referenced by gem5::Iob::readJBus().

JIntData1Addr

const Addr gem5::JIntData1Addr = 0x0500

Definition at line 56 of file iob.hh.

Referenced by gem5::Iob::readJBus().

JIntDataA0Addr

const Addr gem5::JIntDataA0Addr = 0x0600

Definition at line 57 of file iob.hh.

Referenced by gem5::Iob::readJBus().

JIntDataA1Addr

const Addr gem5::JIntDataA1Addr = 0x0700

Definition at line 58 of file iob.hh.

Referenced by gem5::Iob::readJBus().

JIntVecAddr

const Addr gem5::JIntVecAddr = 0x0A00

Definition at line 49 of file iob.hh.

Referenced by gem5::Iob::readIob(), and gem5::Iob::writeIob().

JIntVecMask

const uint64_t gem5::JIntVecMask = 0x0003F

Definition at line 67 of file iob.hh.

lbr

Bitfield<15> gem5::lbr

Definition at line 133 of file x86_cpu.cc.

LDS_SIZE

const int gem5::LDS_SIZE = 65536

static

Definition at line 67 of file shader.hh.

mainEventQueue

std::vector< EventQueue * > gem5::mainEventQueue

Array for main event queues.

Definition at line 57 of file eventq.cc.

Referenced by gem5::LdsState::TickEvent::deschedule(), gem5::BaseGlobalEvent::deschedule(), gem5::trace::TarmacParserRecord::dump(), dumpMainQueue(), eventqDump(), getEventQueue(), gem5::BaseGlobalEvent::reschedule(), gem5::SimulatorThreads::runUntilLocalExit(), gem5::LdsState::TickEvent::schedule(), gem5::BaseGlobalEvent::schedule(), set_max_tick(), simulate(), and gem5::Root::unserialize().

MatRegClassName

constexpr char gem5::MatRegClassName[] = "matrix"

inlineconstexpr

Definition at line 80 of file reg_class.hh.

MatrixMovOp

const OpClass gem5::MatrixMovOp = enums::MatrixMov

static

Definition at line 105 of file op_class.hh.

MatrixOp

const OpClass gem5::MatrixOp = enums::Matrix

static

Definition at line 104 of file op_class.hh.

MatrixOPOp

const OpClass gem5::MatrixOPOp = enums::MatrixOP

static

Definition at line 106 of file op_class.hh.

MaxAddr

const Addr gem5::MaxAddr = (Addr)-1

Definition at line 171 of file types.hh.

Referenced by gem5::prefetch::SignaturePath::addPrefetch(), gem5::branch_prediction::BTBEntry::BTBEntry(), gem5::prefetch::AccessMapPatternMatching::calculatePrefetch(), gem5::AddrRange::getOffset(), gem5::KernelWorkload::initState(), gem5::SectorSubBlk::insert(), gem5::CacheEntry::invalidate(), gem5::branch_prediction::BTBEntry::invalidate(), gem5::TaggedEntry::invalidate(), gem5::TempCacheBlk::invalidate(), gem5::KernelWorkload::KernelWorkload(), gem5::loader::MemoryImage::minAddr(), gem5::prefetch::STeMS::reconstructSequence(), TEST(), and TEST().

MaxMatRegRowLenInBytes

constexpr unsigned gem5::MaxMatRegRowLenInBytes = 256

constexpr

Definition at line 124 of file matrix.hh.

Referenced by TEST().

MaxMatRegRows

constexpr unsigned gem5::MaxMatRegRows = 256

constexpr

Definition at line 125 of file matrix.hh.

Referenced by TEST().

MaxNiagaraProcs

const int gem5::MaxNiagaraProcs = 32

Definition at line 43 of file iob.hh.

Referenced by gem5::Iob::Iob(), gem5::Iob::serialize(), and gem5::Iob::unserialize().

maxThreadsPerCPU

int gem5::maxThreadsPerCPU = 1

The maximum number of active threads across all cpus.

Used to initialize per-thread statistics in the cache.

NB: Be careful to only use it once all the CPUs that you care about have been initialized

Definition at line 86 of file base.cc.

MaxTick

const Tick gem5::MaxTick = 0xffffffffffffffffULL

Definition at line 60 of file types.hh.

Referenced by gem5::o3::ElasticTrace::addCommittedInst(), gem5::o3::ElasticTrace::addSquashedInst(), gem5::memory::MemCtrl::addToReadQueue(), gem5::memory::MemCtrl::addToWriteQueue(), gem5::memory::MemCtrl::chooseNextFRFCFS(), gem5::memory::HeteroMemCtrl::chooseNextFRFCFS(), gem5::memory::DRAMInterface::chooseNextFRFCFS(), gem5::memory::NVMInterface::chooseNextFRFCFS(), gem5::memory::NVMInterface::chooseRead(), gem5::PacketQueue::deferredPacketReadyTime(), gem5::BaseTrafficGen::drain(), get_max_tick(), gem5::CacheBlk::getWhenReady(), gem5::TraceCPU::FixedRetryGen::init(), gem5::CacheBlk::invalidate(), gem5::trace::OstreamLogger::logMessage(), gem5::memory::DRAMInterface::minBankPrep(), gem5::ExitGen::nextPacketTick(), gem5::HybridGen::nextPacketTick(), gem5::IdleGen::nextPacketTick(), gem5::LinearGen::nextPacketTick(), gem5::RandomGen::nextPacketTick(), gem5::StridedGen::nextPacketTick(), gem5::TraceGen::nextPacketTick(), gem5::prefetch::Multi::nextPrefetchReadyTime(), gem5::prefetch::Queued::nextPrefetchReadyTime(), gem5::Queue< Entry >::nextReadyTime(), sc_gem5::Scheduler::oneCycle(), gem5::ruby::PerfectSwitch::operateVnet(), gem5::memory::NVMInterface::processReadReadyEvent(), pybind_init_core(), pybind_init_event(), gem5::ruby::MessageBuffer::readyTime(), gem5::BaseCache::recvTimingReq(), gem5::BaseCache::recvTimingResp(), gem5::BaseTrafficGen::retryReq(), sc_core::sc_max_time(), sc_core::sc_start(), sc_core::sc_start(), gem5::PacketQueue::schedSendEvent(), gem5::SpatterGen::scheduleNextGenEvent(), gem5::ruby::RubyPrefetcherProxy::scheduleNextPrefetch(), gem5::SpatterGen::scheduleNextSendEvent(), gem5::BaseTrafficGen::scheduleUpdate(), gem5::BaseCache::CacheReqPacketQueue::sendDeferredPacket(), simulate(), gem5::Sp805::stopCounter(), TEST(), gem5::BaseKvmCPU::tick(), gem5::Sp805::timeoutExpired(), sc_gem5::Scheduler::timeToPending(), and gem5::BaseTrafficGen::transition().

MaxVecRegLenInBytes

constexpr unsigned gem5::MaxVecRegLenInBytes = 1ULL << 16

constexpr

Definition at line 115 of file vec_reg.hh.

Referenced by TEST().

MemReadOp

const OpClass gem5::MemReadOp = enums::MemRead

static

Definition at line 107 of file op_class.hh.

Referenced by gem5::ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemSV(), and gem5::ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemVI().

MemWriteOp

const OpClass gem5::MemWriteOp = enums::MemWrite

static

Definition at line 108 of file op_class.hh.

MicroPCRomBit

const MicroPC gem5::MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1)

static

Definition at line 151 of file types.hh.

Referenced by isRomMicroPC(), romMicroPC(), TEST(), TEST(), TEST(), and TEST().

MIN_HOST_CYCLES

const uint64_t gem5::MIN_HOST_CYCLES = 1000

static

Minimum number of cycles that a host can spend in a KVM call (used to calculate the resolution of some timers).

The value of this constant is a bit arbitrary, but in practice, we can't really do anything useful in less than ~1000 cycles.

Definition at line 77 of file timer.cc.

Referenced by gem5::PerfKvmTimer::calcResolution(), and gem5::PosixKvmTimer::calcResolution().

MiscRegClassName

constexpr char gem5::MiscRegClassName[] = "miscellaneous"

inlineconstexpr

Definition at line 82 of file reg_class.hh.

MMHUB_OFFSET_SHIFT

constexpr uint32_t gem5::MMHUB_OFFSET_SHIFT = 2

staticconstexpr

Definition at line 77 of file amdgpu_defines.hh.

Referenced by gem5::AMDGPUDevice::readMMIO().

MMIO_BAR

constexpr int gem5::MMIO_BAR = 5

constexpr

Definition at line 68 of file amdgpu_defines.hh.

Referenced by gem5::AMDGPUDevice::read(), gem5::AMDGPUDevice::readMMIO(), and gem5::AMDGPUDevice::write().

mpx

Bitfield<4, 3> gem5::mpx

Definition at line 125 of file x86_cpu.cc.

msi

Bitfield<13> gem5::msi

Definition at line 120 of file smmu_v3_defs.hh.

NoFault

constexpr decltype(nullptr) gem5::NoFault = nullptr

constexpr

Definition at line 253 of file types.hh.

Referenced by gem5::ArmISA::AArch64AArch32SystemAccessTrap(), gem5::o3::ElasticTrace::addCommittedInst(), gem5::ArmISA::addPACDA(), gem5::ArmISA::addPACDB(), gem5::ArmISA::addPACGA(), gem5::ArmISA::addPACIA(), gem5::ArmISA::addPACIB(), gem5::ArmISA::ISA::addressTranslation(), gem5::AtOp64::addressTranslation64(), gem5::o3::ElasticTrace::addSquashedInst(), gem5::TimingSimpleCPU::advanceInst(), gem5::Checker< DynInstPtr >::advancePC(), gem5::BaseSimpleCPU::advancePC(), gem5::AtomicSimpleCPU::amoMem(), amoMemAtomic(), gem5::ArmISA::authDA(), gem5::ArmISA::authDB(), gem5::ArmISA::authIA(), gem5::ArmISA::authIB(), gem5::o3::LSQ::SplitDataRequest::buildPackets(), gem5::RiscvISA::PMAChecker::check(), gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), gem5::PowerISA::TLB::checkCacheability(), gem5::BaseSimpleCPU::checkForInterrupts(), gem5::ArmISA::ArmStaticInst::checkForWFxTrap32(), gem5::ArmISA::ArmStaticInst::checkForWFxTrap64(), gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64(), gem5::RiscvISA::PMAChecker::checkPAddrAlignment(), gem5::RiscvISA::TLB::checkPermissions(), gem5::ArmISA::MMU::checkPermissions(), gem5::ArmISA::MMU::checkPermissions64(), gem5::ArmISA::ArmStaticInst::checkSETENDEnabled(), gem5::ArmISA::ArmStaticInst::checkSmeAccess(), gem5::ArmISA::ArmStaticInst::checkSmeEnabled(), gem5::ArmISA::ArmStaticInst::checkSveEnabled(), gem5::RiscvISA::PMAChecker::checkVAddrAlignment(), gem5::o3::LSQUnit::checkViolations(), gem5::o3::Commit::Commit(), gem5::minor::Execute::commit(), gem5::o3::Commit::commitHead(), gem5::minor::Execute::commitInst(), gem5::o3::Commit::commitInsts(), gem5::ArmISAInst::MicroTfence64::completeAcc(), gem5::TimingSimpleCPU::completeDataAccess(), gem5::TimingSimpleCPU::completeIfetch(), gem5::ArmISA::MiscRegLUTEntry::defaultFault(), gem5::ArmISA::defaultFaultE2H_EL2(), gem5::ArmISA::defaultFaultE2H_EL3(), gem5::ArmISA::TableWalker::doL1Descriptor(), gem5::ArmISA::TableWalker::doL1DescriptorWrapper(), gem5::ArmISA::TableWalker::doL2Descriptor(), gem5::ArmISA::TableWalker::doL2DescriptorWrapper(), gem5::ArmISA::TableWalker::doLongDescriptor(), gem5::ArmISA::TableWalker::doLongDescriptorWrapper(), gem5::BaseKvmCPU::doMMIOAccess(), gem5::o3::InstructionQueue::doSquash(), gem5::RiscvISA::TLB::doTranslate(), gem5::minor::Decode::evaluate(), gem5::ArmISAInst::Tstart64::execute(), gem5::ArmISAInst::Tcancel64::execute(), gem5::ArmISAInst::MicroTfence64::execute(), gem5::ArmISAInst::MicroTcommit64::execute(), gem5::ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::execute(), gem5::ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::execute(), gem5::ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::execute(), gem5::ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::execute(), gem5::ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::execute(), gem5::ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::execute(), gem5::RiscvISA::MemFenceMicro::execute(), gem5::RiscvISA::VMaskMergeMicroInst::execute(), gem5::RiscvISA::VxsatMicroInst::execute(), gem5::RiscvISA::VlFFTrimVlMicroOp::execute(), gem5::RiscvISA::VlSegDeIntrlvMicroInst::execute(), gem5::RiscvISA::VsSegIntrlvMicroInst::execute(), gem5::RiscvISA::VCpyVsMicroInst::execute(), gem5::RiscvISA::VPinVdMicroInst::execute(), gem5::X86ISA::MicroHalt::execute(), gem5::McrMrcImplDefined::execute(), gem5::WarnUnimplemented::execute(), gem5::RiscvISA::VectorNopMicroInst::execute(), gem5::SparcISA::Nop::execute(), gem5::SparcISA::WarnUnimplemented::execute(), gem5::RiscvISA::SystemOp::executeEBreakOrSemihosting(), gem5::o3::IEW::executeInsts(), gem5::o3::LSQUnit::executeLoad(), gem5::o3::LSQUnit::executeLoad(), gem5::minor::Execute::executeMemRefInst(), gem5::o3::LSQUnit::executeStore(), gem5::o3::Fetch::fetchCacheLine(), gem5::ArmISA::TableWalker::fetchDescriptor(), gem5::Iris::TLB::finalizePhysical(), gem5::SparcISA::TLB::finalizePhysical(), gem5::X86ISA::TLB::finalizePhysical(), gem5::ArmISA::MMU::finalizePhysical(), gem5::o3::LSQ::SingleDataRequest::finish(), gem5::o3::LSQ::SplitDataRequest::finish(), gem5::ArmISA::Stage2LookUp::finish(), gem5::ArmISA::TableWalker::Stage2Walk::finish(), gem5::DataTranslation< ExecContextPtr >::finish(), gem5::prefetch::Queued::DeferredPacket::finish(), gem5::WholeTranslationState::finish(), gem5::minor::LSQ::SingleDataRequest::finish(), gem5::minor::LSQ::SplitDataRequest::finish(), gem5::o3::Fetch::finishTranslation(), gem5::TimingSimpleCPU::finishTranslation(), gem5::WholeTranslationState::getFault(), gem5::Iris::Interrupts::getInterrupt(), gem5::RiscvISA::Interrupts::getInterrupt(), gem5::SparcISA::Interrupts::getInterrupt(), gem5::X86ISA::Interrupts::getInterrupt(), gem5::ArmISA::MMU::getResultTe(), gem5::ArmISA::Stage2LookUp::getTe(), gem5::ArmISA::MMU::getTE(), gem5::o3::Commit::handleInterrupt(), gem5::minor::Execute::handleMemResponse(), gem5::minor::Fetch1::handleTLBResponse(), gem5::ArmISAInst::MicroTfence64::initiateAcc(), gem5::TimingSimpleCPU::initiateMemAMO(), gem5::CheckerCPU::initiateMemMgmtCmd(), gem5::minor::ExecContext::initiateMemMgmtCmd(), gem5::TimingSimpleCPU::initiateMemMgmtCmd(), gem5::TimingSimpleCPU::initiateMemRead(), gem5::o3::LSQ::UnsquashableDirectRequest::initiateTranslation(), gem5::o3::Commit::isDrained(), gem5::minor::MinorDynInst::isFault(), gem5::minor::ForwardLineData::isFault(), gem5::minor::LSQ::LSQRequest::makePacket(), gem5::ArmISA::Stage2LookUp::mergeTe(), gem5::minor::Fetch1::minorTraceResponseLine(), gem5::BaseCPU::mwaitAtomic(), gem5::TranslationGenConstIterator::operator++(), gem5::minor::operator<<(), gem5::AtOp64::performAt(), gem5::RiscvISA::PMP::pmpCheck(), gem5::o3::CPU::processInterrupts(), gem5::minor::Fetch1::processResponse(), gem5::ArmISA::TableWalker::processWalkWrapper(), gem5::o3::Commit::propagateInterrupt(), gem5::o3::LSQ::pushRequest(), gem5::minor::LSQ::pushRequest(), gem5::o3::LSQUnit::read(), gem5::ArmISA::TableWalker::readDataUntimed(), gem5::CheckerCPU::readMem(), gem5::AtomicSimpleCPU::readMem(), gem5::X86ISA::readMemAtomic(), gem5::X86ISA::readMemAtomic(), readMemAtomic(), readMemAtomic(), gem5::trace::TarmacParserRecord::readMemNoEffect(), gem5::X86ISA::readPackedMemAtomic(), gem5::VegaISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::RiscvISA::Walker::WalkerState::recvPacket(), gem5::X86ISA::Walker::WalkerState::recvPacket(), gem5::minor::MinorDynInst::reportData(), gem5::minor::ForwardLineData::reportData(), gem5::minor::LSQ::SplitDataRequest::retireResponse(), gem5::TimingSimpleCPU::sendFetch(), gem5::WholeTranslationState::setNoFault(), gem5::RiscvISA::Walker::start(), gem5::X86ISA::Walker::start(), gem5::RiscvISA::Walker::WalkerState::startFunctional(), gem5::X86ISA::Walker::WalkerState::startFunctional(), gem5::VegaISA::Walker::WalkerState::startFunctional(), gem5::VegaISA::Walker::WalkerState::startWalk(), gem5::RiscvISA::Walker::WalkerState::startWalk(), gem5::X86ISA::Walker::WalkerState::startWalk(), gem5::RiscvISA::Walker::startWalkWrapper(), gem5::VegaISA::Walker::WalkerState::stepWalk(), gem5::RiscvISA::Walker::WalkerState::stepWalk(), gem5::X86ISA::Walker::WalkerState::stepWalk(), gem5::minor::Execute::takeInterrupt(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), gem5::ArmISA::MMU::testAndFinalize(), gem5::ArmISA::SelfDebug::testBreakPoints(), gem5::ArmISA::SelfDebug::testDebug(), gem5::ArmISA::MMU::testTranslation(), gem5::ArmISA::TableWalker::testWalk(), gem5::ArmISA::SelfDebug::testWatchPoints(), gem5::AtomicSimpleCPU::tick(), gem5::EmulationPageTable::translate(), gem5::RiscvISA::TLB::translate(), gem5::X86ISA::TLB::translate(), gem5::X86ISA::GpuTLB::translate(), gem5::BaseMMU::MMUTranslationGen::translate(), gem5::AMDGPUVM::UserTranslationGen::translate(), gem5::ArmISA::MMU::translateComplete(), gem5::ArmISA::MMU::translateFs(), gem5::Iris::TLB::translateFunctional(), gem5::SparcISA::TLB::translateFunctional(), gem5::X86ISA::GpuTLB::translateInt(), gem5::X86ISA::TLB::translateInt(), gem5::ArmISA::MMU::translateMmuOn(), gem5::TimingSimpleCPU::translationFault(), gem5::ArmISA::trapPACUse(), gem5::ArmISA::ArmStaticInst::trapWFx(), gem5::minor::Execute::tryToBranch(), gem5::minor::Fetch1::tryToSendToTransfers(), gem5::minor::LSQ::tryToSendToTransfers(), gem5::minor::LSQ::LSQRequest::tryToSuppressFault(), tryTranslate(), gem5::ArmISA::ArmStaticInst::undefinedFault64(), gem5::Checker< DynInstPtr >::validateState(), gem5::Checker< DynInstPtr >::verify(), gem5::ArmISA::TableWalker::walk(), gem5::WholeTranslationState::WholeTranslationState(), gem5::WholeTranslationState::WholeTranslationState(), gem5::o3::LSQUnit::write(), gem5::o3::LSQUnit::writeback(), gem5::o3::IEW::writebackInsts(), gem5::CheckerCPU::writeMem(), gem5::AtomicSimpleCPU::writeMem(), gem5::TimingSimpleCPU::writeMem(), gem5::X86ISA::writeMemAtomic(), gem5::X86ISA::writeMemAtomic(), writeMemAtomic(), writeMemAtomic(), and gem5::o3::DynInst::~DynInst().

nopStaticInstPtr

StaticInstPtr gem5::nopStaticInstPtr = new NopStaticInst

Pointer to a statically allocated generic "nop" instruction object.

Definition at line 67 of file nop_static_inst.cc.

Referenced by gem5::o3::Fetch::finishTranslation().

ns1ats

Bitfield<11> gem5::ns1ats

Definition at line 118 of file smmu_v3_defs.hh.

NsDmaState

const char* gem5::NsDmaState[]

Initial value:

=
{
    "dmaIdle",
    "dmaReading",
    "dmaWriting",
    "dmaReadWaiting",
    "dmaWriteWaiting"
}

Definition at line 82 of file ns_gige.cc.

NsRxStateStrings

const char* gem5::NsRxStateStrings[]

Initial value:

=
{
    "rxIdle",
    "rxDescRefr",
    "rxDescRead",
    "rxFifoBlock",
    "rxFragWrite",
    "rxDescWrite",
    "rxAdvance"
}

Definition at line 60 of file ns_gige.cc.

Referenced by gem5::NSGigE::rxKick().

NsTxStateStrings

const char* gem5::NsTxStateStrings[]

Initial value:

=
{
    "txIdle",
    "txDescRefr",
    "txDescRead",
    "txFifoBlock",
    "txFragRead",
    "txDescWrite",
    "txAdvance"
}

Definition at line 71 of file ns_gige.cc.

Referenced by gem5::NSGigE::txKick().

nullStaticInstPtr

const StaticInstPtr gem5::nullStaticInstPtr

Statically allocated null StaticInstPtr.

Definition at line 36 of file null_static_inst.cc.

Referenced by gem5::Checker< DynInstPtr >::advancePC(), gem5::BaseSimpleCPU::advancePC(), gem5::o3::Commit::commitHead(), gem5::minor::Fetch2::evaluate(), gem5::Checker< DynInstPtr >::handlePendingInt(), and gem5::Checker< DynInstPtr >::verify().

NUM_BANKS

const int gem5::NUM_BANKS = 4

static

Definition at line 84 of file inst_util.hh.

Referenced by gem5::VegaISA::processDPP().

Num_OpClasses

const OpClass gem5::Num_OpClasses = enums::Num_OpClass

static

Definition at line 135 of file op_class.hh.

Referenced by gem5::BaseCPU::CommitCPUStats::CommitCPUStats(), gem5::o3::InstructionQueue::dumpLists(), gem5::minor::Execute::Execute(), gem5::FuncUnit::FuncUnit(), gem5::o3::InstructionQueue::hasReadyInsts(), gem5::o3::InstructionQueue::IQStats::IQStats(), and gem5::o3::InstructionQueue::resetState().

NUM_QREGS

constexpr unsigned gem5::NUM_QREGS = NumVecV8ArchRegs

staticconstexpr

Definition at line 60 of file armv8_cpu.cc.

Referenced by gem5::ArmV8KvmCPU::dump(), gem5::ArmV8KvmCPU::updateKvmState(), and gem5::ArmV8KvmCPU::updateThreadContext().

NUM_XREGS

constexpr unsigned gem5::NUM_XREGS = int_reg::NumArchRegs - 1

staticconstexpr

Definition at line 55 of file armv8_cpu.cc.

Referenced by gem5::ArmV8KvmCPU::dump(), gem5::ArmV8KvmCPU::updateKvmState(), and gem5::ArmV8KvmCPU::updateThreadContext().

numMainEventQueues

uint32_t gem5::numMainEventQueues = 0

Current number of allocated main event queues.

Definition at line 56 of file eventq.cc.

Referenced by gem5::BaseGlobalEventTemplate< Derived >::BaseGlobalEventTemplate(), gem5::BaseGlobalEvent::deschedule(), dumpMainQueue(), eventqDump(), getEventQueue(), gem5::BaseGlobalEvent::reschedule(), gem5::BaseGlobalEvent::schedule(), gem5::BaseGlobalEvent::scheduled(), simulate(), gem5::Root::unserialize(), gem5::BaseGlobalEvent::when(), and gem5::BaseGlobalEvent::~BaseGlobalEvent().

NumOutputBits

const uint8_t gem5::NumOutputBits = 14

Definition at line 47 of file i8042.cc.

Referenced by gem5::X86ISA::I8042::write().

old_int_sa

struct sigaction gem5::old_int_sa

Definition at line 219 of file init_signals.cc.

Referenced by initSigInt(), and restoreSigInt().

p9_msg_info

const P9MsgInfoMap gem5::p9_msg_info

static

Definition at line 82 of file fs9p.cc.

Referenced by gem5::VirtIO9PBase::dumpMsg().

pasid

Bitfield<10> gem5::pasid

Definition at line 129 of file x86_cpu.cc.

Referenced by gem5::AMDGPUDevice::allocateVMID(), gem5::AMDGPUDevice::deallocatePasid(), and gem5::PM4PacketProcessor::mapProcess().

pkru

Bitfield<9> gem5::pkru

Definition at line 128 of file x86_cpu.cc.

pri

Bitfield<16> gem5::pri

Definition at line 123 of file smmu_v3_defs.hh.

priqIrqEn

Bitfield<1> gem5::priqIrqEn

Definition at line 137 of file smmu_v3_defs.hh.

pt

Bitfield<8> gem5::pt

Definition at line 127 of file x86_cpu.cc.

Referenced by gem5::ArmISA::svePredTypeToStr(), and gem5::branch_prediction::TAGEBase::updateGHist().

pybindSimObjectResolver

PybindSimObjectResolver gem5::pybindSimObjectResolver

Definition at line 74 of file core.cc.

Referenced by pybind_init_core().

RamSize

const uint8_t gem5::RamSize = 32

Definition at line 46 of file i8042.cc.

Referenced by gem5::X86ISA::I8042::write().

reserved

Bitfield<63, 19> gem5::reserved

Definition at line 136 of file x86_cpu.cc.

Referenced by gem5::X86ISA::intelmp::ConfigTable::writeOut(), gem5::X86ISA::intelmp::Processor::writeOut(), and gem5::X86ISA::intelmp::BusHierarchy::writeOut().

reverseBitsLookUpTable

const uint8_t gem5::reverseBitsLookUpTable

Initial value:

=
{
    0x00, 0x80, 0x40, 0xC0, 0x20, 0xA0, 0x60, 0xE0, 0x10, 0x90, 0x50, 0xD0,
    0x30, 0xB0, 0x70, 0xF0, 0x08, 0x88, 0x48, 0xC8, 0x28, 0xA8, 0x68, 0xE8,
    0x18, 0x98, 0x58, 0xD8, 0x38, 0xB8, 0x78, 0xF8, 0x04, 0x84, 0x44, 0xC4,
    0x24, 0xA4, 0x64, 0xE4, 0x14, 0x94, 0x54, 0xD4, 0x34, 0xB4, 0x74, 0xF4,
    0x0C, 0x8C, 0x4C, 0xCC, 0x2C, 0xAC, 0x6C, 0xEC, 0x1C, 0x9C, 0x5C, 0xDC,
    0x3C, 0xBC, 0x7C, 0xFC, 0x02, 0x82, 0x42, 0xC2, 0x22, 0xA2, 0x62, 0xE2,
    0x12, 0x92, 0x52, 0xD2, 0x32, 0xB2, 0x72, 0xF2, 0x0A, 0x8A, 0x4A, 0xCA,
    0x2A, 0xAA, 0x6A, 0xEA, 0x1A, 0x9A, 0x5A, 0xDA, 0x3A, 0xBA, 0x7A, 0xFA,
    0x06, 0x86, 0x46, 0xC6, 0x26, 0xA6, 0x66, 0xE6, 0x16, 0x96, 0x56, 0xD6,
    0x36, 0xB6, 0x76, 0xF6, 0x0E, 0x8E, 0x4E, 0xCE, 0x2E, 0xAE, 0x6E, 0xEE,
    0x1E, 0x9E, 0x5E, 0xDE, 0x3E, 0xBE, 0x7E, 0xFE, 0x01, 0x81, 0x41, 0xC1,
    0x21, 0xA1, 0x61, 0xE1, 0x11, 0x91, 0x51, 0xD1, 0x31, 0xB1, 0x71, 0xF1,
    0x09, 0x89, 0x49, 0xC9, 0x29, 0xA9, 0x69, 0xE9, 0x19, 0x99, 0x59, 0xD9,
    0x39, 0xB9, 0x79, 0xF9, 0x05, 0x85, 0x45, 0xC5, 0x25, 0xA5, 0x65, 0xE5,
    0x15, 0x95, 0x55, 0xD5, 0x35, 0xB5, 0x75, 0xF5, 0x0D, 0x8D, 0x4D, 0xCD,
    0x2D, 0xAD, 0x6D, 0xED, 0x1D, 0x9D, 0x5D, 0xDD, 0x3D, 0xBD, 0x7D, 0xFD,
    0x03, 0x83, 0x43, 0xC3, 0x23, 0xA3, 0x63, 0xE3, 0x13, 0x93, 0x53, 0xD3,
    0x33, 0xB3, 0x73, 0xF3, 0x0B, 0x8B, 0x4B, 0xCB, 0x2B, 0xAB, 0x6B, 0xEB,
    0x1B, 0x9B, 0x5B, 0xDB, 0x3B, 0xBB, 0x7B, 0xFB, 0x07, 0x87, 0x47, 0xC7,
    0x27, 0xA7, 0x67, 0xE7, 0x17, 0x97, 0x57, 0xD7, 0x37, 0xB7, 0x77, 0xF7,
    0x0F, 0x8F, 0x4F, 0xCF, 0x2F, 0xAF, 0x6F, 0xEF, 0x1F, 0x9F, 0x5F, 0xDF,
    0x3F, 0xBF, 0x7F, 0xFF
}

Lookup table used for High Speed bit reversing.

Definition at line 44 of file bitfield.cc.

Referenced by reverseBits().

ROM_SIZE

constexpr uint32_t gem5::ROM_SIZE = 0x20000

constexpr

Definition at line 72 of file amdgpu_defines.hh.

Referenced by gem5::AMDGPUDevice::AMDGPUDevice(), and gem5::AMDGPUDevice::readROM().

rootStats

Root::RootStats & gem5::rootStats = Root::RootStats::instance

Global simulator statistics that are not associated with a specific SimObject.

Definition at line 57 of file root.cc.

roundOps

const int gem5::roundOps[]

static

Initial value:

=
    { FE_DOWNWARD, FE_TONEAREST, FE_TOWARDZERO, FE_UPWARD }

Definition at line 39 of file fenv.cc.

Referenced by getFpRound(), and setFpRound().

ROW_SIZE

const int gem5::ROW_SIZE = 16

static

Definition at line 83 of file inst_util.hh.

Referenced by gem5::VegaISA::dppInstImpl(), and gem5::VegaISA::processDPP().

RX_INT

const int gem5::RX_INT = 0x1

Definition at line 46 of file uart.hh.

Referenced by gem5::Uart8250::dataAvailable(), gem5::Uart8250::readIir(), gem5::Uart8250::readRbr(), and gem5::Uart8250::writeIer().

s1p

Bitfield<1> gem5::s1p

Definition at line 110 of file smmu_v3_defs.hh.

SDMA_ATOMIC_ADD64

constexpr unsigned int gem5::SDMA_ATOMIC_ADD64 = 47

constexpr

Definition at line 312 of file sdma_packets.hh.

Referenced by gem5::SDMAEngine::atomicData().

seconds_since_epoch

const unsigned gem5::seconds_since_epoch = 1000 * 1000 * 1000

Approximate seconds since the epoch (1/1/1970).

About a billion, by my reckoning. We want to keep this a constant (not use the real-world time) to keep simulations repeatable.

Definition at line 514 of file syscall_emul.hh.

Referenced by clock_gettimeFunc(), gettimeofdayFunc(), sysinfoFunc(), and timeFunc().

sev

Bitfield<14> gem5::sev

Definition at line 121 of file smmu_v3_defs.hh.

Referenced by gem5::PosixKvmTimer::PosixKvmTimer().

SimdAddAccOp

const OpClass gem5::SimdAddAccOp = enums::SimdAddAcc

static

Definition at line 68 of file op_class.hh.

SimdAddOp

const OpClass gem5::SimdAddOp = enums::SimdAdd

static

Definition at line 67 of file op_class.hh.

SimdAesMixOp

const OpClass gem5::SimdAesMixOp = enums::SimdAesMix

static

Definition at line 96 of file op_class.hh.

SimdAesOp

const OpClass gem5::SimdAesOp = enums::SimdAes

static

Definition at line 95 of file op_class.hh.

SimdAluOp

const OpClass gem5::SimdAluOp = enums::SimdAlu

static

Definition at line 69 of file op_class.hh.

SimdCmpOp

const OpClass gem5::SimdCmpOp = enums::SimdCmp

static

Definition at line 70 of file op_class.hh.

SimdConfigOp

const OpClass gem5::SimdConfigOp = enums::SimdConfig

static

Definition at line 134 of file op_class.hh.

SimdCvtOp

const OpClass gem5::SimdCvtOp = enums::SimdCvt

static

Definition at line 71 of file op_class.hh.

SimdDivOp

const OpClass gem5::SimdDivOp = enums::SimdDiv

static

Definition at line 78 of file op_class.hh.

SimdExtOp

const OpClass gem5::SimdExtOp = enums::SimdExt

static

Definition at line 132 of file op_class.hh.

SimdFloatAddOp

const OpClass gem5::SimdFloatAddOp = enums::SimdFloatAdd

static

Definition at line 83 of file op_class.hh.

SimdFloatAluOp

const OpClass gem5::SimdFloatAluOp = enums::SimdFloatAlu

static

Definition at line 84 of file op_class.hh.

SimdFloatCmpOp

const OpClass gem5::SimdFloatCmpOp = enums::SimdFloatCmp

static

Definition at line 85 of file op_class.hh.

SimdFloatCvtOp

const OpClass gem5::SimdFloatCvtOp = enums::SimdFloatCvt

static

Definition at line 86 of file op_class.hh.

SimdFloatDivOp

const OpClass gem5::SimdFloatDivOp = enums::SimdFloatDiv

static

Definition at line 87 of file op_class.hh.

SimdFloatExtOp

const OpClass gem5::SimdFloatExtOp = enums::SimdFloatExt

static

Definition at line 133 of file op_class.hh.

SimdFloatMatMultAccOp

const OpClass gem5::SimdFloatMatMultAccOp = enums::SimdFloatMatMultAcc

static

Definition at line 91 of file op_class.hh.

SimdFloatMiscOp

const OpClass gem5::SimdFloatMiscOp = enums::SimdFloatMisc

static

Definition at line 88 of file op_class.hh.

SimdFloatMultAccOp

const OpClass gem5::SimdFloatMultAccOp = enums::SimdFloatMultAcc

static

Definition at line 90 of file op_class.hh.

SimdFloatMultOp

const OpClass gem5::SimdFloatMultOp = enums::SimdFloatMult

static

Definition at line 89 of file op_class.hh.

SimdFloatReduceAddOp

const OpClass gem5::SimdFloatReduceAddOp = enums::SimdFloatReduceAdd

static

Definition at line 94 of file op_class.hh.

SimdFloatReduceCmpOp

const OpClass gem5::SimdFloatReduceCmpOp = enums::SimdFloatReduceCmp

static

Definition at line 93 of file op_class.hh.

SimdFloatSqrtOp

const OpClass gem5::SimdFloatSqrtOp = enums::SimdFloatSqrt

static

Definition at line 92 of file op_class.hh.

SimdIndexedLoadOp

const OpClass gem5::SimdIndexedLoadOp = enums::SimdIndexedLoad

static

Definition at line 119 of file op_class.hh.

SimdIndexedStoreOp

const OpClass gem5::SimdIndexedStoreOp = enums::SimdIndexedStore

static

Definition at line 120 of file op_class.hh.

SimdMatMultAccOp

const OpClass gem5::SimdMatMultAccOp = enums::SimdMatMultAcc

static

Definition at line 75 of file op_class.hh.

SimdMiscOp

const OpClass gem5::SimdMiscOp = enums::SimdMisc

static

Definition at line 72 of file op_class.hh.

SimdMultAccOp

const OpClass gem5::SimdMultAccOp = enums::SimdMultAcc

static

Definition at line 74 of file op_class.hh.

SimdMultOp

const OpClass gem5::SimdMultOp = enums::SimdMult

static

Definition at line 73 of file op_class.hh.

SimdPredAluOp

const OpClass gem5::SimdPredAluOp = enums::SimdPredAlu

static

Definition at line 103 of file op_class.hh.

SimdReduceAddOp

const OpClass gem5::SimdReduceAddOp = enums::SimdReduceAdd

static

Definition at line 80 of file op_class.hh.

SimdReduceAluOp

const OpClass gem5::SimdReduceAluOp = enums::SimdReduceAlu

static

Definition at line 81 of file op_class.hh.

SimdReduceCmpOp

const OpClass gem5::SimdReduceCmpOp = enums::SimdReduceCmp

static

Definition at line 82 of file op_class.hh.

SimdSha1Hash2Op

const OpClass gem5::SimdSha1Hash2Op = enums::SimdSha1Hash2

static

Definition at line 98 of file op_class.hh.

SimdSha1HashOp

const OpClass gem5::SimdSha1HashOp = enums::SimdSha1Hash

static

Definition at line 97 of file op_class.hh.

SimdSha256Hash2Op

const OpClass gem5::SimdSha256Hash2Op = enums::SimdSha256Hash2

static

Definition at line 100 of file op_class.hh.

SimdSha256HashOp

const OpClass gem5::SimdSha256HashOp = enums::SimdSha256Hash

static

Definition at line 99 of file op_class.hh.

SimdShaSigma2Op

const OpClass gem5::SimdShaSigma2Op = enums::SimdShaSigma2

static

Definition at line 101 of file op_class.hh.

SimdShaSigma3Op

const OpClass gem5::SimdShaSigma3Op = enums::SimdShaSigma3

static

Definition at line 102 of file op_class.hh.

SimdShiftAccOp

const OpClass gem5::SimdShiftAccOp = enums::SimdShiftAcc

static

Definition at line 77 of file op_class.hh.

SimdShiftOp

const OpClass gem5::SimdShiftOp = enums::SimdShift

static

Definition at line 76 of file op_class.hh.

SimdSqrtOp

const OpClass gem5::SimdSqrtOp = enums::SimdSqrt

static

Definition at line 79 of file op_class.hh.

SimdStridedLoadOp

const OpClass gem5::SimdStridedLoadOp = enums::SimdStridedLoad

static

Definition at line 117 of file op_class.hh.

SimdStridedStoreOp

const OpClass gem5::SimdStridedStoreOp = enums::SimdStridedStore

static

Definition at line 118 of file op_class.hh.

SimdUnitStrideFaultOnlyFirstLoadOp

const OpClass gem5::SimdUnitStrideFaultOnlyFirstLoadOp = enums::SimdUnitStrideFaultOnlyFirstLoad

static

Definition at line 121 of file op_class.hh.

SimdUnitStrideLoadOp

const OpClass gem5::SimdUnitStrideLoadOp = enums::SimdUnitStrideLoad

static

Definition at line 111 of file op_class.hh.

SimdUnitStrideMaskLoadOp

const OpClass gem5::SimdUnitStrideMaskLoadOp = enums::SimdUnitStrideMaskLoad

static

Definition at line 113 of file op_class.hh.

SimdUnitStrideMaskStoreOp

const OpClass gem5::SimdUnitStrideMaskStoreOp = enums::SimdUnitStrideMaskStore

static

Definition at line 115 of file op_class.hh.

SimdUnitStrideSegmentedLoadOp

const OpClass gem5::SimdUnitStrideSegmentedLoadOp = enums::SimdUnitStrideSegmentedLoad

static

Definition at line 129 of file op_class.hh.

SimdUnitStrideSegmentedStoreOp

const OpClass gem5::SimdUnitStrideSegmentedStoreOp = enums::SimdUnitStrideSegmentedStore

static

Definition at line 130 of file op_class.hh.

SimdUnitStrideStoreOp

const OpClass gem5::SimdUnitStrideStoreOp = enums::SimdUnitStrideStore

static

Definition at line 112 of file op_class.hh.

SimdWholeRegisterLoadOp

const OpClass gem5::SimdWholeRegisterLoadOp = enums::SimdWholeRegisterLoad

static

Definition at line 123 of file op_class.hh.

SimdWholeRegisterStoreOp

const OpClass gem5::SimdWholeRegisterStoreOp = enums::SimdWholeRegisterStore

static

Definition at line 125 of file op_class.hh.

simFreq

statistics::Value & gem5::simFreq = rootStats.simFreq

Definition at line 47 of file stats.cc.

simout

OutputDirectory gem5::simout

Definition at line 62 of file output.cc.

Referenced by gem5::BaseSemihosting::callTmpNam(), gem5::trace::InstPBTrace::createTraceFile(), gem5::Pl111::dmaDone(), gem5::X86ISA::GpuTLB::exitCallback(), gem5::ComputeUnit::exitCallback(), gem5::statistics::initHDF5(), gem5::statistics::initText(), gem5::ListenSocketUnixFile::listen(), gem5::MemTraceProbe::MemTraceProbe(), gem5::FDArray::openOutputFile(), output(), gem5::linux::PanicOrOopsEvent::process(), gem5::ProtocolTester::ProtocolTester(), gem5::HDLcd::pxlFrameDone(), setOutputDir(), gem5::SimPoint::SimPoint(), gem5::VirtIO9PDiod::startDiod(), gem5::ArmISA::FsLinux::startup(), gem5::Terminal::terminalDump(), gem5::VncInput::VncInput(), gem5::pseudo_inst::writefile(), gem5::ProtocolTester::~ProtocolTester(), gem5::SimPoint::~SimPoint(), and sc_gem5::TraceFile::~TraceFile().

simQuantum

Tick gem5::simQuantum = 0

Simulation Quantum for multiple eventq simulation.

The quantum value is the period length after which the queues synchronize themselves with each other. This means that any event to scheduled on Queue A which is generated by an event on Queue B should be at least simQuantum ticks away in future.

Definition at line 48 of file eventq.cc.

Referenced by exitSimLoop(), gem5::statistics::schedStatEvent(), and simulate().

simSeconds

statistics::Formula & gem5::simSeconds = rootStats.simSeconds

Definition at line 45 of file stats.cc.

Referenced by gem5::GUPSGen::GUPSGenStat::regStats(), gem5::memory::AbstractMemory::MemStats::regStats(), gem5::memory::DRAMInterface::DRAMStats::regStats(), gem5::memory::MemCtrl::CtrlStats::regStats(), gem5::memory::NVMInterface::NVMStats::regStats(), gem5::SMMUv3BaseCache::SMMUv3BaseCacheStats::SMMUv3BaseCacheStats(), gem5::ruby::Throttle::ThrottleStats::ThrottleStats(), and gem5::WalkCache::WalkCacheStats::WalkCacheStats().

simTicks

statistics::Value & gem5::simTicks = rootStats.simTicks

Definition at line 46 of file stats.cc.

Referenced by gem5::CommMonitor::samplePeriodic(), and gem5::ruby::Throttle::ThrottleStats::ThrottleStats().

simulate_limit_event

GlobalSimLoopExitEvent * gem5::simulate_limit_event = nullptr

Definition at line 64 of file simulate.cc.

Referenced by get_max_tick(), set_max_tick(), simulate(), and gem5::ruby::RubySystem::startup().

simulatorThreads

std::unique_ptr<SimulatorThreads> gem5::simulatorThreads

static

Definition at line 168 of file simulate.cc.

Referenced by simulate(), and terminateEventQueueThreads().

sse

Bitfield<1> gem5::sse

Definition at line 123 of file x86_cpu.cc.

stallModel

Bitfield<25, 24> gem5::stallModel

Definition at line 130 of file smmu_v3_defs.hh.

stLevel

Bitfield<28, 27> gem5::stLevel

Definition at line 132 of file smmu_v3_defs.hh.

termModel

Bitfield<26> gem5::termModel

Definition at line 131 of file smmu_v3_defs.hh.

TESTER_ALLOCATOR

unsigned int gem5::TESTER_ALLOCATOR = 0

static

Definition at line 54 of file memtest.cc.

TESTER_NETWORK

int gem5::TESTER_NETWORK =0

Definition at line 50 of file GarnetSyntheticTraffic.cc.

ttEndian

Bitfield<22, 21> gem5::ttEndian

Definition at line 128 of file smmu_v3_defs.hh.

ttf

Bitfield<3, 2> gem5::ttf

Definition at line 111 of file smmu_v3_defs.hh.

TX_INT

const int gem5::TX_INT = 0x2

Definition at line 47 of file uart.hh.

Referenced by gem5::Uart8250::readIir(), gem5::Uart8250::Uart8250(), gem5::Uart8250::writeIer(), and gem5::Uart8250::writeThr().

UART_MCR_LOOP

const uint8_t gem5::UART_MCR_LOOP = 0x10

Definition at line 46 of file uart8250.hh.

Referenced by gem5::Uart8250::Registers::Registers().

uintr

Bitfield<14> gem5::uintr

Definition at line 132 of file x86_cpu.cc.

vatos

Bitfield<20> gem5::vatos

Definition at line 127 of file smmu_v3_defs.hh.

VecElemClassName

constexpr char gem5::VecElemClassName[] = "vector_element"

inlineconstexpr

Definition at line 78 of file reg_class.hh.

VecPredRegClassName

constexpr char gem5::VecPredRegClassName[] = "vector_predicate"

inlineconstexpr

Definition at line 79 of file reg_class.hh.

VecRegClassName

constexpr char gem5::VecRegClassName[] = "vector"

inlineconstexpr

Definition at line 77 of file reg_class.hh.

version_tags

std::set< std::string > gem5::version_tags

The version tags for this build of the simulator, to be stored in the Globals section during serialization and compared upon unserialization.

Definition at line 42 of file globals.test.cc.

Referenced by gem5::Globals::serialize(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), and gem5::Globals::unserialize().

VGA_ROM_DEFAULT

constexpr uint32_t gem5::VGA_ROM_DEFAULT = 0xc0000

constexpr

Definition at line 71 of file amdgpu_defines.hh.

Referenced by gem5::AMDGPUDevice::AMDGPUDevice().

vmid16

Bitfield<18> gem5::vmid16

Definition at line 125 of file smmu_v3_defs.hh.

vmw

Bitfield<17> gem5::vmw

Definition at line 124 of file smmu_v3_defs.hh.