gem5  v21.1.0.2
Namespaces | Classes | Typedefs | Enumerations | Functions | Variables
gem5 Namespace Reference

Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223. More...

Namespaces

 AMBA
 
 ArmISA
 
 ArmISAInst
 
 auxv
 
 bitfield_backend
 
 bloom_filter
 
 branch_prediction
 
 compression
 
 context_switch_task_id
 
 copy_engine_reg
 
 cp
 
 debug
 
 decode_cache
 
 fastmodel
 
 free_bsd
 
 Gcn3ISA
 classes that represnt vector/scalar operands in GCN3 ISA.
 
 Gem5Internal
 
 GenericISA
 
 guest_abi
 
 igbreg
 
 Iris
 
 linux
 
 loader
 
 memory
 
 minor
 
 MipsISA
 
 networking
 
 NullISA
 
 o3
 
 PowerISA
 
 prefetch
 
 probing
 
 ps2
 
 pseudo_inst
 
 QARMA
 
 replacement_policy
 
 RiscvISA
 
 ruby
 
 scmi
 
 sim_clock
 
 sinic
 
 SparcISA
 
 statistics
 
 stl_helpers
 
 TheISA
 
 Trace
 
 VegaISA
 classes that represnt vector/scalar operands in VEGA ISA.
 
 X86ISA
 This is exposed globally, independent of the ISA.
 
 X86ISAInst
 

Classes

class  __SchedulingPolicy
 Intermediate class that derives from the i-face class, and implements its API. More...
 
struct  _amd_queue_t
 
struct  _hsa_agent_dispatch_packet_t
 
struct  _hsa_barrier_and_packet_t
 
struct  _hsa_barrier_or_packet_t
 
struct  _hsa_dispatch_packet_t
 
struct  _hsa_queue_t
 
struct  _hsa_signal_t
 
class  A9SCU
 
struct  Aapcs32
 
struct  Aapcs32Vfp
 
struct  Aapcs64
 
class  AbstractNVM
 This is an interface between the disk interface (which will handle the disk data transactions) and the timing model. More...
 
class  ActivityRecorder
 ActivityRecorder helper class that informs the CPU if it can switch over to being idle or not. More...
 
class  AddressManager
 
struct  AddressMonitor
 
class  AddrMapper
 An address mapper changes the packet addresses in going from the response port side of the mapper to the request port side. More...
 
class  AddrRange
 The AddrRange class encapsulates an address range, and supports a number of tests to check if two ranges intersect, if a range contains a specific address etc. More...
 
class  AddrRangeMap
 The AddrRangeMap uses an STL map to implement an interval tree for address decoding. More...
 
class  AmbaDevice
 
class  AmbaDmaDevice
 
class  AmbaFake
 
class  AmbaIntDevice
 
class  AmbaPioDevice
 
struct  amd_signal_s
 
class  AMDGPUDevice
 Device model for an AMD GPU. More...
 
struct  AMDKernelCode
 
class  AMDMMIOReader
 Helper class to read Linux kernel MMIO trace from amdgpu modprobes. More...
 
class  Ap2ScpDoorbell
 
struct  ApertureRegister
 
class  AQLRingBuffer
 Internal ring buffer which is used to prefetch/store copies of the in-memory HSA ring buffer. More...
 
class  ArchTimer
 Per-CPU architected timer. More...
 
class  ArchTimerKvm
 
class  ARMArchTLB
 
class  ArmFreebsd
 
class  ArmFreebsd32
 
class  ArmFreebsd64
 
class  ArmInterruptPin
 Generic representation of an Arm interrupt pin. More...
 
class  ArmInterruptPinGen
 This SimObject is instantiated in the python world and serves as an ArmInterruptPin generator. More...
 
class  ArmKvmCPU
 ARM implementation of a KVM-based hardware virtualized CPU. More...
 
class  ArmLinux
 
class  ArmLinux32
 
class  ArmLinux64
 
class  ArmLinuxProcess32
 A process with emulated Arm/Linux syscalls. More...
 
class  ArmLinuxProcess64
 A process with emulated Arm/Linux syscalls. More...
 
class  ArmPPI
 
class  ArmPPIGen
 Private Peripheral Interrupt Generator Since PPIs are banked in the GIC, this class is capable of generating more than one interrupt (one per ContextID). More...
 
class  ArmProcess
 
class  ArmProcess32
 
class  ArmProcess64
 
class  ArmSemihosting
 Semihosting for AArch32 and AArch64. More...
 
class  ArmSigInterruptPin
 
class  ArmSigInterruptPinGen
 
class  ArmSPI
 
class  ArmSPIGen
 Shared Peripheral Interrupt Generator It is capable of generating one interrupt only: it maintains a pointer to it and returns it every time it is asked for it (via the get metod) More...
 
class  ArmSystem
 
class  ArmV8KvmCPU
 This is an implementation of a KVM-based ARMv8-compatible CPU. More...
 
class  AssociativeSet
 Associative container based on the previosuly defined Entry type Each element is indexed by a key of type Addr, an additional bool value is used as an additional tag data of the entry. More...
 
class  AtagCmdline
 
class  AtagCore
 
class  AtagHeader
 
class  AtagMem
 
class  AtagNone
 
class  AtagRev
 
class  AtagSerial
 
class  AtomicGeneric2Op
 
class  AtomicGeneric3Op
 
class  AtomicGenericPair3Op
 
class  AtomicOpAdd
 
class  AtomicOpAnd
 
class  AtomicOpCAS
 
class  AtomicOpDec
 
class  AtomicOpExch
 
struct  AtomicOpFunctor
 
class  AtomicOpInc
 
class  AtomicOpMax
 
class  AtomicOpMin
 
class  AtomicOpOr
 
class  AtomicOpSub
 
class  AtomicOpXor
 
class  AtomicRequestProtocol
 
class  AtomicResponseProtocol
 
class  AtomicSimpleCPU
 
class  BadDevice
 BadDevice This device just panics when accessed. More...
 
class  Barrier
 
class  BaseArmKvmCPU
 
class  BaseBufferArg
 Base class for BufferArg and TypedBufferArg, Not intended to be used directly. More...
 
class  BaseCache
 A basic cache interface. More...
 
class  BaseCPU
 
class  BaseGdbRegCache
 Concrete subclasses of this abstract class represent how the register values are transmitted on the wire. More...
 
class  BaseGen
 Base class for all generators, with the shared functionality and virtual functions for entering, executing and leaving the generator. More...
 
class  BaseGic
 
class  BaseGicRegisters
 
class  BaseGlobalEvent
 Common base class for GlobalEvent and GlobalSyncEvent. More...
 
class  BaseGlobalEventTemplate
 Funky intermediate class to support CRTP so that we can have a common constructor to create the local events, even though the types of the local events are defined in the derived classes. More...
 
class  BaseHTMCheckpoint
 Transactional Memory checkpoint. More...
 
class  BaseIndexingPolicy
 A common base class for indexing table locations. More...
 
class  BaseInterrupts
 
class  BaseISA
 
class  BaseKvmCPU
 Base class for KVM based CPU models. More...
 
class  BaseKvmTimer
 Timer functions to interrupt VM execution after a number of simulation ticks. More...
 
class  BaseMemProbe
 Base class for memory system probes accepting Packet instances. More...
 
class  BaseMMU
 
class  BasePixelPump
 Timing generator for a pixel-based display. More...
 
class  BaseRemoteGDB
 
class  BaseSetAssoc
 A basic cache tag store. More...
 
class  BaseSimpleCPU
 
class  BaseStackTrace
 
class  BaseTags
 A common base class of Cache tagstore objects. More...
 
class  BaseTLB
 
class  BaseTrafficGen
 The traffic generator is a module that generates stimuli for the memory system, based on a collection of simple generator behaviours that are either probabilistic or based on traces. More...
 
class  BaseXBar
 The base crossbar contains the common elements of the non-coherent and coherent crossbar. More...
 
class  BasicPioDevice
 
class  BasicSignal
 
class  BitfieldROType
 
class  BitfieldType
 
class  BitfieldTypeImpl
 
class  BitfieldWOType
 
class  BmpWriter
 
class  BreakPCEvent
 
class  Bridge
 A bridge is used to interface two different crossbars (or in general a memory-mapped requestor and responder), with buffering for requests and responses. More...
 
class  BufferArg
 BufferArg represents an untyped buffer in target user space that is passed by reference to an (emulated) system call. More...
 
class  Cache
 A coherent cache that can be arranged in flexible topologies. More...
 
class  CacheBlk
 A Basic Cache block. More...
 
class  CacheBlkPrintWrapper
 Simple class to provide virtual print() method on cache blocks without allocating a vtable pointer for every single cache block. More...
 
class  CallbackQueue
 
class  ChannelAddr
 Class holding a guest address in a contiguous channel-local address space. More...
 
class  ChannelAddrRange
 The ChanneelAddrRange class describes a contiguous range of addresses in a contiguous channel-local address space. More...
 
class  Check
 
class  Checker
 Templated Checker class. More...
 
class  CheckerCPU
 CheckerCPU class. More...
 
class  CheckerThreadContext
 Derived ThreadContext class for use with the Checker. More...
 
class  CheckpointIn
 
class  CheckTable
 
class  ChunkGenerator
 This class takes an arbitrary memory region (address/length pair) and generates a series of appropriately (e.g. More...
 
class  CircleBuf
 Circular buffer backed by a vector. More...
 
class  CircularQueue
 Circular queue. More...
 
class  Clint
 NOTE: This implementation of CLINT is based on the SiFive U54MC datasheet: https://sifive.cdn.prismic.io/sifive/fab000f6- 0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_ full_20G1.03.00_manual.pdf. More...
 
class  ClockDomain
 The ClockDomain provides clock to group of clocked objects bundled under the same clock domain. More...
 
class  Clocked
 Helper class for objects that need to be clocked. More...
 
class  ClockedObject
 The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to the cycles of the object. More...
 
class  ClockRateControlBwIf
 
struct  ClockRateControlDummyProtocolType
 
class  ClockRateControlFwIf
 
class  ClockRateControlInitiatorSocket
 
class  ClockRateControlSlaveBase
 
class  ClockRateControlTargetSocket
 
class  CoherentXBar
 A coherent crossbar connects a number of (potentially) snooping requestors and responders, and routes the request and response packets based on the address, and also forwards all requests to the snoopers and deals with the snoop responses. More...
 
struct  CommandReg_t
 
class  CommMonitor
 The communication monitor is a SimObject which can monitor statistics of the communication happening between two ports in the memory system. More...
 
class  CompressedTags
 A CompressedTags cache tag store. More...
 
class  CompressionBlk
 A superblock is composed of sub-blocks, and each sub-block has information regarding its superblock and a pointer to its superblock tag. More...
 
class  ComputeUnit
 
class  ConfigCache
 
class  ConstProxyPtr
 
struct  ContextDescriptor
 
class  CopyEngine
 
class  Coroutine
 This template defines a Coroutine wrapper type with a Boost-like interface. More...
 
class  CountedExitEvent
 
class  CowDiskImage
 Specialization for accessing a copy-on-write disk image layer. More...
 
class  CpuLocalTimer
 
class  CPUProgressEvent
 
class  CpuThread
 
class  CustomNoMaliGpu
 
class  CxxConfigDirectoryEntry
 Config details entry for a SimObject. More...
 
class  CxxConfigFileBase
 Config file wrapper providing a common interface to CxxConfigManager. More...
 
class  CxxConfigManager
 This class allows a config file to be read into gem5 (generating the appropriate SimObjects) from C++. More...
 
class  CxxConfigParams
 Base for peer classes of SimObjectParams derived classes with parameter modifying member functions. More...
 
class  CxxIniFile
 CxxConfigManager interface for using .ini files. More...
 
class  Cycles
 Cycles is a wrapper class for representing cycle counts, i.e. More...
 
class  DataTranslation
 This class represents part of a data address translation. More...
 
struct  DebugBreakEvent
 
class  DebugStep
 
class  DecoderFaultInst
 
class  DerivedClockDomain
 The derived clock domains provides the notion of a clock domain that is connected to a parent clock domain that can either be a source clock domain or a derived clock domain. More...
 
class  DeviceFDEntry
 Holds file descriptors needed to simulate devices opened with pseudo files (commonly with calls to ioctls). More...
 
class  DirectedGenerator
 
class  DiskImage
 Basic interface for accessing a disk image. More...
 
class  Display
 
struct  DisplayTimings
 
class  DistEtherLink
 Model for a fixed bandwidth full duplex ethernet link. More...
 
class  DistHeaderPkt
 
class  DistIface
 The interface class to talk to peer gem5 processes. More...
 
class  DmaCallback
 DMA callback class. More...
 
class  DmaDevice
 
class  DmaPort
 
class  DmaReadFifo
 Buffered DMA engine helper class. More...
 
class  DmaThread
 
class  DmaVirtDevice
 
struct  DmesgEntry
 
class  Doorbell
 Generic doorbell interface. More...
 
struct  dp_regs
 Ethernet device registers. More...
 
struct  dp_rom
 
class  Drainable
 Interface for objects that might require draining before checkpointing. More...
 
class  DrainManager
 
class  DramGen
 DRAM specific generator is for issuing request with variable page hit length and bank utilization. More...
 
class  DRAMPower
 DRAMPower is a standalone tool which calculates the power consumed by a DRAM in the system. More...
 
class  DramRotGen
 
class  Dueler
 A dueler is an entry that may or may not be accounted for sampling. More...
 
class  DuelingMonitor
 Duel between two sampled options to determine which is the winner. More...
 
class  DumbTOD
 DumbTOD simply returns some idea of time when read. More...
 
class  DummyChecker
 Specific non-templated derived class used for SimObject configuration. More...
 
class  DVFSHandler
 DVFS Handler class, maintains a list of all the domains it can handle. More...
 
class  DynPoolManager
 
class  EmbeddedPyBind
 
struct  EmbeddedPython
 
class  EmulatedDriver
 EmulatedDriver is an abstract base class for fake SE-mode device drivers. More...
 
class  EmulationPageTable
 
class  EnergyCtrl
 
class  Episode
 
class  EtherBus
 
class  EtherDevBase
 Dummy class to keep the Python class hierarchy in sync with the C++ object hierarchy. More...
 
class  EtherDevice
 
class  EtherDump
 
class  EtherInt
 
class  EtherLink
 
class  EtherSwitch
 
class  EtherTapBase
 
class  EtherTapInt
 
class  EtherTapStub
 
class  EthPacketData
 
class  Event
 
class  EventBase
 Common base class for Event and GlobalEvent, so they can share flag and priority definitions and accessor functions. More...
 
class  EventFunctionWrapper
 
class  EventManager
 
class  EventQueue
 Queue of events sorted in time order. More...
 
class  EventWrapper
 
class  ExecContext
 The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate the state of the CPU model. More...
 
class  ExecStage
 
class  ExitGen
 The exit generator exits from the simulation once entered. More...
 
class  ExternalMaster
 
class  ExternalSlave
 
class  FailUnimplemented
 Static instruction class for unimplemented instructions that cause simulator termination. More...
 
class  FALRU
 A fully associative LRU cache. More...
 
class  FALRUBlk
 A fully associative cache block. More...
 
class  FaultBase
 
class  FDArray
 
class  FDEntry
 Holds a single file descriptor mapping and that mapping's data for processes running in syscall emulation mode. More...
 
class  FetchStage
 
class  FetchUnit
 
class  Fiber
 This class represents a fiber, which is a light weight sort of thread which is cooperatively scheduled and runs sequentially with other fibers, swapping in and out of a single actual thread of execution. More...
 
class  Fifo
 Simple FIFO implementation backed by a circular buffer. More...
 
class  FileFDEntry
 Holds file descriptors for host-backed files; host-backed files are files which were opened on the physical machine where the simulation is running (probably the thing on/under your desk). More...
 
class  FixedStreamGen
 
class  Flags
 Wrapper that groups a few flag bits under the same undelying container. More...
 
class  FlashDevice
 Flash Device model The Flash Device model is a timing model for a NAND flash device. More...
 
class  Float16
 
class  FrameBuffer
 Internal gem5 representation of a frame buffer. More...
 
class  FreeBSD
 This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Alpha FreeBSD syscall interface. More...
 
class  FUDesc
 
class  FunctionalRequestProtocol
 
class  FunctionalResponseProtocol
 
class  FunctionProfile
 
class  FuncUnit
 
class  FutexKey
 FutexKey class defines an unique identifier for a particular futex in the system. More...
 
class  FutexMap
 FutexMap class holds a map of all futexes used in the system. More...
 
class  FVPBasePwrCtrl
 
struct  FXSave
 
class  GarnetSyntheticTraffic
 
class  GenericAlignmentFault
 
class  GenericArmPciHost
 
class  GenericHtmFailureFault
 
class  GenericPageTableFault
 
class  GenericPciHost
 Configurable generic PCI host interface. More...
 
class  GenericSatCounter
 Implements an n bit saturating counter and provides methods to increment, decrement, and read it. More...
 
struct  GenericSyscallABI
 
struct  GenericSyscallABI32
 
struct  GenericSyscallABI64
 
class  GenericTimer
 
class  GenericTimerFrame
 
class  GenericTimerISA
 
class  GenericTimerMem
 
class  GenericWatchdog
 
class  GicV2
 
class  Gicv2m
 
class  Gicv2mFrame
 Ultimately this class should be embedded in the Gicv2m class, but this confuses Python as 'Gicv2m::Frame' gets interpreted as 'Frame' in namespace Gicv2m. More...
 
class  Gicv3
 
class  Gicv3CPUInterface
 
class  Gicv3Distributor
 
class  Gicv3Its
 GICv3 ITS module. More...
 
class  Gicv3Redistributor
 
class  GlobalEvent
 The main global event class. More...
 
class  GlobalMemPipeline
 
class  Globals
 Container for serializing global variables (not associated with any serialized object). More...
 
class  GlobalSimLoopExitEvent
 
class  GlobalSyncEvent
 A special global event that synchronizes all threads and forces them to process asynchronously enqueued events. More...
 
class  GoodbyeObject
 
class  GPUCommandProcessor
 
class  GPUComputeDriver
 
class  GPUDispatcher
 
class  GPUDynInst
 
class  GPUExecContext
 
class  GPURenderDriver
 
class  GPUStaticInst
 
class  GpuWavefront
 
class  GTestLogOutput
 
class  GTestTickHandler
 
class  HardBreakpoint
 
class  HBFDEntry
 Extends the base class to include a host-backed file descriptor field that records the integer used to represent the file descriptor on the host and the file's flags. More...
 
class  HDLcd
 
class  HelloObject
 
class  HiFive
 
class  HMCController
 HMC Controller, in general, is responsible for translating the host protocol (AXI for example) to serial links protocol. More...
 
struct  hsa_packet_header_bitfield_t
 
class  HSAPacketProcessor
 
class  HSAQueueDescriptor
 
class  HSAQueueEntry
 
class  HWScheduler
 
class  HybridGen
 Hybrid NVM + DRAM specific generator is for issuing request with variable buffer hit length and bank utilization. More...
 
class  I2CBus
 
class  I2CDevice
 
class  IdeController
 Device model for an Intel PIIX4 IDE controller. More...
 
class  IdeDisk
 IDE Disk device model. More...
 
class  IdleGen
 The idle generator does nothing. More...
 
class  IdleStartEvent
 
class  IGbE
 
class  IGbEInt
 
class  IllegalExecInst
 This class is modelling instructions which are not going to be executed since they are flagged as Illegal Execution Instructions (PSTATE.IL = 1 or CPSR.IL = 1). More...
 
class  ImgWriter
 
class  ImmOp
 
class  ImmOp64
 
class  IniFile
 This class represents the contents of a ".ini" file. More...
 
class  InstDecoder
 
class  InstResult
 
class  Intel8254Timer
 Programmable Interval Timer (Intel 8254) More...
 
class  IntSinkPin
 
class  IntSinkPinBase
 
class  IntSourcePin
 
class  IntSourcePinBase
 
class  InvalidateGenerator
 
class  Iob
 
class  IPACache
 
class  IsaFake
 IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and rites. More...
 
struct  ItsAction
 
class  ItsCommand
 An ItsCommand is created whenever there is a new command in the command queue. More...
 
class  ItsProcess
 ItsProcess is a base coroutine wrapper which is spawned by the Gicv3Its module when the latter needs to perform different actions, like translating a peripheral's MSI into an LPI (See derived ItsTranslation) or processing a Command from the ITS queue (ItsCommand). More...
 
class  ItsTranslation
 An ItsTranslation is created whenever a peripheral writes a message in GITS_TRANSLATER (MSI). More...
 
class  KernelLaunchStaticInst
 
class  KernelWorkload
 
struct  kfd_event_data
 
struct  kfd_hsa_hw_exception_data
 
struct  kfd_hsa_memory_exception_data
 
struct  kfd_ioctl_acquire_vm_args
 
struct  kfd_ioctl_alloc_memory_of_gpu_args
 
struct  kfd_ioctl_alloc_queue_gws_args
 
struct  kfd_ioctl_create_event_args
 
struct  kfd_ioctl_create_queue_args
 
struct  kfd_ioctl_dbg_address_watch_args
 
struct  kfd_ioctl_dbg_register_args
 
struct  kfd_ioctl_dbg_unregister_args
 
struct  kfd_ioctl_dbg_wave_control_args
 
struct  kfd_ioctl_destroy_event_args
 
struct  kfd_ioctl_destroy_queue_args
 
struct  kfd_ioctl_free_memory_of_gpu_args
 
struct  kfd_ioctl_get_clock_counters_args
 
struct  kfd_ioctl_get_dmabuf_info_args
 
struct  kfd_ioctl_get_process_apertures_args
 
struct  kfd_ioctl_get_process_apertures_new_args
 
struct  kfd_ioctl_get_queue_wave_state_args
 
struct  kfd_ioctl_get_tile_config_args
 
struct  kfd_ioctl_get_version_args
 
struct  kfd_ioctl_import_dmabuf_args
 
struct  kfd_ioctl_map_memory_to_gpu_args
 
struct  kfd_ioctl_reset_event_args
 
struct  kfd_ioctl_set_cu_mask_args
 
struct  kfd_ioctl_set_event_args
 
struct  kfd_ioctl_set_memory_policy_args
 
struct  kfd_ioctl_set_scratch_backing_va_args
 
struct  kfd_ioctl_set_trap_handler_args
 
struct  kfd_ioctl_smi_events_args
 
struct  kfd_ioctl_unmap_memory_from_gpu_args
 
struct  kfd_ioctl_update_queue_args
 
struct  kfd_ioctl_wait_events_args
 
struct  kfd_memory_exception_failure
 
struct  kfd_process_device_apertures
 
class  Kvm
 KVM parent interface. More...
 
class  KvmDevice
 KVM device wrapper. More...
 
union  KvmFPReg
 
class  KvmKernelGicV2
 KVM in-kernel GIC abstraction. More...
 
class  KvmVM
 KVM VM container. More...
 
class  LdsChunk
 this represents a slice of the overall LDS, intended to be associated with an individual workgroup More...
 
class  LdsState
 
class  LinearEquation
 This class describes a linear equation with constant coefficients. More...
 
class  LinearGen
 The linear generator generates sequential requests from a start to an end address, with a fixed block size. More...
 
class  LinearSystem
 
class  Linux
 This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Alpha Linux syscall interface. More...
 
class  ListenSocket
 
class  LocalMemPipeline
 
class  LocalSimLoopExitEvent
 
class  Logger
 
class  Malta
 Top level class for Malta Chipset emulation. More...
 
class  MaltaCChip
 Malta CChip CSR Emulation. More...
 
class  MaltaIO
 Malta I/O device is a catch all for all the south bridge stuff we care to implement. More...
 
class  MasterPort
 
class  MathExpr
 
class  MathExprPowerModel
 A Equation power model. More...
 
class  MC146818
 Real-Time Clock (MC146818) More...
 
class  McrMrcImplDefined
 This class is also used for IMPLEMENTATION DEFINED registers, whose mcr/mrc behaviour is trappable even for unimplemented registers. More...
 
class  McrMrcMiscInst
 Certain mrc/mcr instructions act as nops or flush the pipe based on what register the instruction is trying to access. More...
 
class  McrrOp
 
class  MemBackdoor
 
class  MemChecker
 MemChecker. More...
 
class  MemCheckerMonitor
 Implements a MemChecker monitor, to be inserted between two ports. More...
 
class  MemCmd
 
class  MemDelay
 This abstract component provides a mechanism to delay packets. More...
 
class  MemFootprintProbe
 Probe to track footprint of accessed memory Two granularity of footprint measurement i.e. More...
 
class  MemPool
 Class for handling allocation of physical pages in SE mode. More...
 
class  MemState
 This class holds the memory state for the Process class and all of its derived, architecture-specific children. More...
 
class  MemTest
 The MemTest class tests a cache coherent memory system by generating false sharing and verifying the read data against a reference updated on the completion of writes. More...
 
class  MemTraceProbe
 
class  MHU
 Message Handling Unit. More...
 
class  MhuDoorbell
 
class  MinorCPU
 MinorCPU is an in-order CPU model with four fixed pipeline stages: More...
 
class  MinorFU
 A functional unit that can execute any of opClasses operations with a single op(eration)Lat(ency) and issueLat(ency) associated with the unit rather than each operation (as in src/FuncUnit). More...
 
class  MinorFUPool
 A collection of MinorFUs. More...
 
class  MinorFUTiming
 Extra timing capability to allow individual ops to have their source register dependency latencies tweaked based on the ExtMachInst of the source instruction. More...
 
class  MinorOpClass
 Boxing for MinorOpClass to get around a build problem with C++11 but also allow for future additions to op class checking. More...
 
class  MinorOpClassSet
 Wrapper for a matchable set of op classes. More...
 
class  MipsLinux
 
class  MipsProcess
 
class  MiscRegImmOp64
 
class  MiscRegImplDefined64
 
class  MiscRegOp64
 This class is implementing the Base class for a generic AArch64 instruction which is making use of system registers (MiscReg), like MSR,MRS,SYS. More...
 
class  MiscRegRegImmOp
 
class  MiscRegRegImmOp64
 
class  MmDisk
 
class  MmioVirtIO
 
class  MrrcOp
 
class  MrsOp
 
class  MSHR
 Miss Status and handling Register. More...
 
class  MSHRQueue
 A Class for maintaining a list of pending and allocated memory requests. More...
 
class  MsrBase
 
class  MsrImmOp
 
class  MsrRegOp
 
class  MultiLevelPageTable
 
class  MuxingKvmGic
 
class  Named
 Interface for things with names. More...
 
class  NoMaliGpu
 
class  NonCachingSimpleCPU
 The NonCachingSimpleCPU is an AtomicSimpleCPU using the 'atomic_noncaching' memory mode instead of just 'atomic'. More...
 
class  NoncoherentCache
 A non-coherent cache. More...
 
class  NoncoherentXBar
 A non-coherent crossbar connects a number of non-snooping memory-side ports and cpu_sides, and routes the request and response packets based on the address. More...
 
struct  ns_desc32
 
struct  ns_desc64
 
class  NSGigE
 NS DP83820 Ethernet device model. More...
 
class  NSGigEInt
 
class  NvmGen
 NVM specific generator is for issuing request with variable buffer hit length and bank utilization. More...
 
class  ObjectMatch
 ObjectMatch contains a vector of expressions. More...
 
class  OFSchedulingPolicy
 
class  OpDesc
 
class  OpenFlagTable
 
class  OperandInfo
 
class  OperatingSystem
 This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to an operating system syscall interface. More...
 
class  OutputDirectory
 Interface for creating files in a gem5 output directory. More...
 
class  OutputFile
 
class  OutputStream
 
struct  P9MsgHeader
 
struct  P9MsgInfo
 
class  Packet
 A Packet is used to encapsulate a transfer between two objects in the memory system (e.g., the L1 and L2 cache). More...
 
class  PacketFifo
 
struct  PacketFifoEntry
 
class  PacketQueue
 A packet queue is a class that holds deferred packets and later sends them using the associated CPU-side port or memory-side port. More...
 
struct  PageTableOps
 
class  PanicPCEvent
 
struct  ParseParam
 
struct  ParseParam< BitUnionType< T > >
 
struct  ParseParam< bool >
 
struct  ParseParam< std::string >
 
struct  ParseParam< T, decltype(to_number("", std::declval< T & >()), void())>
 
struct  ParseParam< T, std::enable_if_t< std::is_base_of< typename RegisterBankBase::RegisterBaseBase, T >::value > >
 
struct  ParseParam< VecPredRegContainer< NumBits, Packed > >
 
struct  ParseParam< VecRegContainer< Sz > >
 Calls required for serialization/deserialization. More...
 
class  Pc
 
struct  pcap_file_header
 
struct  pcap_pkthdr
 
class  PCEvent
 
class  PCEventQueue
 
class  PCEventScope
 
class  PciBar
 
class  PciBarNone
 
struct  PciBusAddr
 
class  PciDevice
 PCI device, base implementation is only config space. More...
 
class  PciHost
 The PCI host describes the interface between PCI devices and a simulated system. More...
 
class  PciIoBar
 
class  PciLegacyIoBar
 
class  PciMemBar
 
class  PciMemUpperBar
 
class  PciVirtIO
 
class  PerfKvmCounter
 An instance of a performance counter. More...
 
class  PerfKvmCounterConfig
 PerfEvent counter configuration. More...
 
class  PerfKvmTimer
 PerfEvent based timer using the host's CPU cycle counter. More...
 
class  PhysRegId
 Physical register ID. More...
 
class  PioDevice
 This device is the base class which all devices senstive to an address range inherit from. More...
 
class  PioPort
 The PioPort class is a programmed i/o port that all devices that are sensitive to an address range use. More...
 
class  PipeFDEntry
 Holds the metadata needed to maintain the mappings for file descriptors allocated with the pipe() system calls and its variants. More...
 
class  PipeStageIFace
 
struct  Pixel
 Internal gem5 representation of a Pixel. More...
 
class  PixelConverter
 Configurable RGB pixel converter. More...
 
class  Pl011
 
class  PL031
 
class  Pl050
 
class  Pl111
 
class  Platform
 
class  Plic
 
class  PlicIntDevice
 
struct  PlicOutput
 NOTE: This implementation of CLINT is based on the SiFive U54MC datasheet: https://sifive.cdn.prismic.io/sifive/fab000f6- 0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_ full_20G1.03.00_manual.pdf. More...
 
class  PMAChecker
 Based on the RISC-V ISA privileged specifications V1.11, there is no implementation guidelines on the Physical Memory Attributes. More...
 
class  PMP
 This class helps to implement RISCV's physical memory protection (pmp) primitive. More...
 
class  PngWriter
 Image writer implementing support for PNG. More...
 
class  PollEvent
 
class  PollQueue
 
class  PoolManager
 
class  Port
 Ports are used to interface objects to each other. More...
 
class  PortProxy
 This object is a proxy for a port or other object which implements the functional response protocol, to be used for debug accesses. More...
 
class  PosixKvmTimer
 Timer based on standard POSIX timers. More...
 
class  PowerDomain
 The PowerDomain groups PowerState objects together to regulate their power states. More...
 
class  PowerLinux
 
class  PowerModel
 
class  PowerModelState
 A PowerModelState is an abstract class used as interface to get power figures out of SimObjects. More...
 
class  PowerProcess
 
class  PowerState
 Helper class for objects that have power states. More...
 
struct  PrdEntry_t
 
class  PrdTableEntry
 
class  Printable
 Abstract base class for objects which support being printed to a stream for debugging. More...
 
class  ProbeListener
 ProbeListener base class; here to simplify things like containers containing multiple types of ProbeListener. More...
 
class  ProbeListenerArg
 ProbeListenerArg generates a listener for the class of Arg and the class type T which is the class containing the function that notify will call. More...
 
class  ProbeListenerArgBase
 ProbeListenerArgBase is used to define the base interface to a ProbeListenerArg (i.e the notify method on specific type). More...
 
class  ProbeListenerObject
 This class is a minimal wrapper around SimObject. More...
 
class  ProbeManager
 ProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners with probe points. More...
 
class  ProbePoint
 ProbeListener base class; again used to simplify use of ProbePoints in containers and used as to define interface for adding removing listeners to the ProbePoint. More...
 
class  ProbePointArg
 ProbePointArg generates a point for the class of Arg. More...
 
class  Process
 
class  ProfileNode
 
class  ProtocolTester
 
class  ProxyPtr
 
class  ProxyPtr< void, Proxy >
 
class  ProxyPtrBuffer
 
class  PybindSimObjectResolver
 Resolve a SimObject name using the Pybind configuration. More...
 
class  PyEvent
 PyBind wrapper for Events. More...
 
class  PyTrafficGen
 
struct  QCntxt
 
class  Queue
 A high-level queue interface, to be used by both the MSHR queue and the write buffer. More...
 
class  QueuedRequestPort
 The QueuedRequestPort combines two queues, a request queue and a snoop response queue, that both share the same port. More...
 
class  QueuedResponsePort
 A queued port is a port that has an infinite queue for outgoing packets and thus decouples the module that wants to send request/responses from the flow control (retry mechanism) of the port. More...
 
class  QueueEntry
 A queue entry base class, to be used by both the MSHRs and write-queue entries. More...
 
class  Random
 
class  RandomGen
 The random generator is similar to the linear one, but does not generate sequential addresses. More...
 
class  RandomStreamGen
 
class  RangeAddrMapper
 Range address mapper that maps a set of original ranges to a set of remapped ranges, where a specific range is of the same size (original and remapped), only with an offset. More...
 
class  RawDiskImage
 Specialization for accessing a raw disk image. More...
 
class  RealView
 
class  RealViewCtrl
 
class  RealViewOsc
 This is an implementation of a programmable oscillator on the that can be configured through the RealView/Versatile Express configuration interface. More...
 
class  RealViewTemperatureSensor
 This device implements the temperature sensor used in the RealView/Versatile Express platform. More...
 
class  RedirectPath
 RedirectPath stores a mapping from one 'appPath' to a vector of 'hostPath'. More...
 
class  ReExec
 
class  RefCounted
 Derive from RefCounted if you want to enable reference counting of this class. More...
 
class  RefCountingPtr
 If you want a reference counting pointer to a mutable object, create it like this: More...
 
class  RegClassInfo
 
class  RegId
 Register ID: describe an architectural register with its class and index. More...
 
class  RegImmImmOp
 
class  RegImmOp
 
class  RegImmRegOp
 
class  RegImmRegShiftOp
 
class  RegisterBank
 
class  RegisterBankBase
 
class  RegisterFile
 
class  RegisterManager
 
class  RegisterManagerPolicy
 Register Manager Policy abstract class. More...
 
class  RegisterOperandInfo
 
class  RegMiscRegImmOp
 
class  RegMiscRegImmOp64
 
class  RegNone
 
class  RegOp
 
class  RegRegImmImmOp
 
class  RegRegImmImmOp64
 
class  RegRegImmOp
 
class  RegRegOp
 
class  RegRegRegImmOp
 
class  RegRegRegImmOp64
 
class  RegRegRegOp
 
class  RegRegRegRegOp
 
class  ReplaceableEntry
 A replaceable entry is a basic entry in a 2d table-like structure that needs to have replacement functionality. More...
 
class  ReqPacketQueue
 
class  Request
 
struct  RequestorInfo
 The RequestorInfo class contains data about a specific requestor. More...
 
class  RequestPort
 A RequestPort is a specialisation of a Port, which implements the default protocol for the three different level of transport functions. More...
 
class  ResponsePort
 A ResponsePort is a specialization of a port. More...
 
class  RespPacketQueue
 
class  RiscvLinux
 
class  RiscvLinux32
 
class  RiscvLinux64
 
class  RiscvProcess
 
class  RiscvProcess32
 
class  RiscvProcess64
 
class  RiscvRTC
 NOTE: This is a generic wrapper around the MC146818 RTC. More...
 
class  Root
 
class  RRSchedulingPolicy
 
class  RubyDirectedTester
 
class  RubyTester
 
class  ScalarMemPipeline
 
class  ScalarRegisterFile
 
class  Scheduler
 
class  ScheduleStage
 
class  ScheduleToExecute
 Communication interface between Schedule and Execute stages. More...
 
class  SchedulingPolicy
 Interface class for the wave scheduling policy. More...
 
class  ScoreboardCheckStage
 
class  ScoreboardCheckToSchedule
 Communication interface between ScoreboardCheck and Schedule stages. More...
 
class  Scp
 
class  Scp2ApDoorbell
 
class  SectorBlk
 A Basic Sector block. More...
 
class  SectorSubBlk
 A sector is composed of sub-blocks, and each sub-block has information regarding its sector and a pointer to its sector tag. More...
 
class  SectorTags
 A SectorTags cache tag store. More...
 
struct  SemiPseudoAbi32
 
struct  SemiPseudoAbi64
 
class  SerialDevice
 Base class for serial devices such as terminals. More...
 
class  Serializable
 Basic support for object serialization. More...
 
class  SerialLink
 SerialLink is a simple variation of the Bridge class, with the ability to account for the latency of packet serialization. More...
 
class  SerialNullDevice
 Dummy serial device that discards all data sent to it. More...
 
class  SeriesRequestGenerator
 
class  SESyscallFault
 
class  SetAssociative
 A set associative indexing policy. More...
 
class  SETranslatingPortProxy
 
class  SEWorkload
 
class  Shader
 
struct  ShowParam
 
struct  ShowParam< BitUnionType< T > >
 
struct  ShowParam< bool >
 
struct  ShowParam< T, std::enable_if_t< std::is_base_of< typename RegisterBankBase::RegisterBaseBase, T >::value > >
 
struct  ShowParam< T, std::enable_if_t< std::is_same< char, T >::value||std::is_same< unsigned char, T >::value||std::is_same< signed char, T >::value > >
 
struct  ShowParam< VecPredRegContainer< NumBits, Packed > >
 
struct  ShowParam< VecRegContainer< Sz > >
 
class  SignalInterruptBwIf
 
struct  SignalInterruptDummyProtocolType
 
class  SignalInterruptFwIf
 
class  SignalInterruptInitiatorSocket
 
class  SignalInterruptSlaveBase
 
class  SignalInterruptTargetSocket
 
class  SimObject
 Abstract superclass for simulation objects. More...
 
class  SimObjectResolver
 Base class to wrap object resolving functionality. More...
 
class  SimpleCache
 A very simple cache object. More...
 
class  SimpleDisk
 
class  SimpleExecContext
 
class  SimpleMemDelay
 Delay packets by a constant time. More...
 
class  SimpleMemobj
 A very simple memory object. More...
 
class  SimpleObject
 
class  SimplePoolManager
 
class  SimpleThread
 The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interface. More...
 
class  SimpleTimingPort
 The simple timing port uses a queued port to implement recvFunctional and recvTimingReq through recvAtomic. More...
 
class  SimpleUart
 
class  SimPoint
 
class  SkewedAssociative
 A skewed associative indexing policy. More...
 
class  SkipFuncBase
 
class  SlavePort
 
struct  SMMUAction
 
class  SMMUATSDevicePort
 
class  SMMUATSMemoryPort
 
struct  SMMUCommand
 
class  SMMUCommandExecProcess
 
class  SMMUControlPort
 
class  SMMUDevicePort
 
class  SMMUDeviceRetryEvent
 
struct  SMMUEvent
 
class  SMMUProcess
 
union  SMMURegs
 
class  SMMURequestPort
 
struct  SMMUSemaphore
 
struct  SMMUSignal
 
class  SMMUTableWalkPort
 
class  SMMUTLB
 
class  SMMUTranslationProcess
 
struct  SMMUTranslRequest
 
class  SMMUv3
 
class  SMMUv3BaseCache
 
class  SMMUv3DeviceInterface
 
struct  SNHash
 
class  SnoopFilter
 This snoop filter keeps track of which connected port has a particular line of data. More...
 
class  SnoopRespPacketQueue
 
class  SocketFDEntry
 
class  Solaris
 This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Solaris syscall interface. More...
 
class  SouthBridge
 
class  Sp804
 
class  Sp805
 
class  Sparc32Linux
 
class  Sparc32Process
 
class  Sparc64Process
 
class  SparcLinux
 
class  SparcProcess
 
struct  SparcPseudoInstABI
 
class  SparcSolaris
 
class  SrcClockDomain
 The source clock domains provides the notion of a clock domain that is connected to a tunable clock source. More...
 
class  StackDistCalc
 The stack distance calculator is a passive object that merely observes the addresses pass to it. More...
 
class  StackDistProbe
 
class  StaticInst
 Base, ISA-independent static instruction class. More...
 
class  StaticRegisterManagerPolicy
 
class  StochasticGen
 
class  StreamGen
 
struct  StreamTableEntry
 
class  StridedGen
 The strided generator generates sequential requests from a start to an end address, with a fixed block size. More...
 
struct  StringWrap
 
class  StubSlavePort
 Implement a ‘stub’ port which just responds to requests by printing a message. More...
 
class  StubSlavePortHandler
 
class  SubSystem
 The SubSystem simobject does nothing, it is just a container for other simobjects used by the configuration system. More...
 
class  SuperBlk
 A basic compression superblock. More...
 
class  SyscallDesc
 This class provides the wrapper interface for the system call implementations which are defined in the sim/syscall_emul files and bound to the ISAs in the architecture specific code (i.e. More...
 
class  SyscallDescABI
 
class  SyscallDescTable
 
class  SyscallRetryFault
 
class  SyscallReturn
 This class represents the return value from an emulated system call, including any errno setting. More...
 
class  System
 
class  SystemCounter
 Global system counter. More...
 
class  SystemCounterListener
 Abstract class for elements whose events depend on the counting speed of the System Counter. More...
 
class  T1000
 
class  TaggedEntry
 A tagged entry is an entry containing a tag. More...
 
class  TapEvent
 
class  TapListener
 
class  TCPIface
 
class  TempCacheBlk
 Special instance of CacheBlk for use with tempBlk that deals with its block address regeneration. More...
 
class  Temperature
 The class stores temperatures in Kelvin and provides helper methods to convert to/from Celsius. More...
 
class  Terminal
 
class  TesterDma
 
class  TesterThread
 
class  ThermalCapacitor
 A ThermalCapacitor is used to model a thermal capacitance between two thermal domains. More...
 
class  ThermalDomain
 A ThermalDomain is used to group objects under that operate under the same temperature. More...
 
class  ThermalEntity
 An abstract class that represents any thermal entity which is used in the circuital thermal equivalent model. More...
 
class  ThermalModel
 
class  ThermalNode
 A ThermalNode is used to connect thermal entities, such as resistors, capacitors, references and domains. More...
 
class  ThermalReference
 A ThermalReference is a thermal domain with fixed temperature. More...
 
class  ThermalResistor
 A ThermalResistor is used to model a thermal resistance between two thermal domains. More...
 
class  ThreadContext
 ThreadContext is the external interface to all thread state for anything outside of the CPU. More...
 
struct  ThreadState
 Struct for holding general thread state that is needed across CPU models. More...
 
class  Ticked
 Ticked attaches gem5's event queue/scheduler to evaluate calls and provides a start/stop interface to ticking. More...
 
class  TickedObject
 TickedObject attaches Ticked to ClockedObject and can be used as a base class where ticked operation. More...
 
class  Time
 
class  TimeBuffer
 
class  TimingExpr
 
class  TimingExprBin
 
class  TimingExprEvalContext
 Object to gather the visible context for evaluation. More...
 
class  TimingExprIf
 
class  TimingExprLet
 
class  TimingExprLiteral
 
class  TimingExprReadIntReg
 
class  TimingExprRef
 
class  TimingExprSrcReg
 
class  TimingExprUn
 
class  TimingRequestProtocol
 
class  TimingResponseProtocol
 
class  TimingSimpleCPU
 
class  TLBCoalescer
 The TLBCoalescer is a ClockedObject sitting on the front side (CPUSide) of each TLB. More...
 
class  TokenManager
 
class  TokenRequestPort
 
class  TokenResponsePort
 
class  TraceCPU
 The trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model. More...
 
class  TraceGen
 The trace replay generator reads a trace file and plays back the transactions. More...
 
class  TrafficGen
 The traffic generator is a module that generates stimuli for the memory system, based on a collection of simple behaviours that are either probabilistic or based on traces. More...
 
class  TranslatingPortProxy
 This proxy attempts to translate virtual addresses using the TLBs. More...
 
class  Trie
 A trie is a tree-based data structure used for data retrieval. More...
 
struct  TypedAtomicOpFunctor
 
class  TypedBufferArg
 TypedBufferArg is a class template; instances of this template represent typed buffers in target user space that are passed by reference to an (emulated) system call. More...
 
class  Uart
 
class  Uart8250
 
class  UFSHostDevice
 Host controller layer: This is your Host controller This layer handles the UFS functionality. More...
 
class  UncontendedMutex
 
class  UnimpFault
 
class  UnknownOp
 
class  UnknownOp64
 
struct  V7LPageTableOps
 
struct  V8PageTableOps16k
 
struct  V8PageTableOps4k
 
struct  V8PageTableOps64k
 
class  VecPredRegContainer
 Generic predicate register container. More...
 
class  VecPredRegT
 Predicate register view. More...
 
class  VecRegContainer
 Vector Register Abstraction This generic class is the model in a particularization of MVC, to vector registers. More...
 
class  VectorRegisterFile
 
class  VGic
 
class  VirtDescriptor
 VirtIO descriptor (chain) wrapper. More...
 
class  VirtIO9PBase
 This class implements a VirtIO transport layer for the 9p network file system. More...
 
class  VirtIO9PDiod
 VirtIO 9p proxy that communicates with the diod 9p server using pipes. More...
 
class  VirtIO9PProxy
 VirtIO 9p proxy base class. More...
 
class  VirtIO9PSocket
 VirtIO 9p proxy that communicates with a 9p server over tcp sockets. More...
 
class  VirtIOBlock
 VirtIO block device. More...
 
class  VirtIOConsole
 VirtIO console. More...
 
class  VirtIODeviceBase
 Base class for all VirtIO-based devices. More...
 
class  VirtIODummyDevice
 
class  VirtQueue
 Base wrapper around a virtqueue. More...
 
class  VMA
 
class  VncInput
 
class  VncKeyboard
 A device that expects to receive input from the vnc server should derrive (through mulitple inheritence if necessary from VncKeyboard or VncMouse and call setKeyboard() or setMouse() respectively on the vnc server. More...
 
class  VncMouse
 
class  VncServer
 
class  VoltageDomain
 A VoltageDomain is used to group clock domains that operate under the same voltage. More...
 
class  WaitClass
 
class  WaiterState
 WaiterState defines internal state of a waiter thread. More...
 
class  WalkCache
 
class  WarnUnimplemented
 Base class for unimplemented instructions that cause a warning to be printed (but do not terminate simulation). More...
 
class  Wavefront
 
class  WFBarrier
 WF barrier slots. More...
 
class  WholeTranslationState
 This class captures the state of an address translation. More...
 
class  Workload
 
class  WriteAllocator
 The write allocator inspects write packets and detects streaming patterns. More...
 
class  WriteQueue
 A write queue for all eviction packets, i.e. More...
 
class  WriteQueueEntry
 Write queue entry. More...
 
class  X86KvmCPU
 x86 implementation of a KVM-based hardware virtualized CPU. More...
 
class  X86Linux
 
class  X86Linux32
 
class  X86Linux64
 
struct  X86PseudoInstABI
 

Typedefs

typedef std::unique_ptr< BaseHTMCheckpointBaseHTMCheckpointPtr
 
typedef Trie< Addr, X86ISA::TlbEntryTlbEntryTrie
 
typedef MultiLevelPageTable< LongModePTE< 47, 39 >, LongModePTE< 38, 30 >, LongModePTE< 29, 21 >, LongModePTE< 20, 12 > > ArchPageTable
 
typedef std::list< AddrRangeAddrRangeList
 Convenience typedef for a collection of address ranges. More...
 
typedef std::unique_ptr< AtomicOpFunctorAtomicOpFunctorPtr
 
template<typename T >
using BitUnionType = bitfield_backend::BitUnionOperators< T >
 
template<typename T >
using BitUnionBaseType = typename bitfield_backend::BitUnionBaseType< T >::Type
 
typedef SatCounter8 SatCounter
 
typedef int64_t Counter
 Statistics counter type. More...
 
typedef uint64_t Tick
 Tick count type. More...
 
typedef uint64_t Addr
 Address type This will probably be moved somewhere else in the near future. More...
 
typedef uint16_t MicroPC
 
using RegVal = uint64_t
 
using RegIndex = uint16_t
 
using ElemIndex = uint16_t
 Logical vector register elem index type. More...
 
typedef int16_t ThreadID
 Thread index/ID type. More...
 
typedef int ContextID
 Globally unique thread context ID. More...
 
typedef int16_t PortID
 Port index/ID type, and a symbolic name for an invalid port id. More...
 
typedef std::shared_ptr< FaultBaseFault
 
typedef std::vector< OpDesc * >::const_iterator OPDDiterator
 
typedef std::vector< FUDesc * >::const_iterator FUDDiterator
 
typedef uint64_t InstSeqNum
 
typedef unsigned int InstTag
 
using PhysRegIdPtr = PhysRegId *
 
typedef std::pair< Addr, AddrBasicBlockRange
 Probe for SimPoints BBV generation. More...
 
typedef RefCountingPtr< StaticInstStaticInstPtr
 
typedef RubyTester::SenderState SenderState
 
using PacketPtr = Packet *
 
typedef uint32_t _amd_queue_properties32_t
 
typedef int64_t amd_signal_kind64_t
 
typedef struct gem5::amd_signal_s amd_signal_t
 
typedef std::shared_ptr< EthPacketDataEthPacketPtr
 
using RegisterBankLE = RegisterBank< ByteOrder::little >
 
using RegisterBankBE = RegisterBank< ByteOrder::big >
 
typedef std::map< P9MsgType, P9MsgInfoP9MsgInfoMap
 
typedef uint8_t P9MsgType
 
typedef uint16_t P9Tag
 
typedef std::bitset< std::numeric_limits< unsigned long long >::digits > VectorMask
 
typedef std::shared_ptr< GPUDynInstGPUDynInstPtr
 
typedef MemBackdoorMemBackdoorPtr
 
typedef std::vector< ReplaceableEntry * > ReplacementCandidates
 Replacement candidates as chosen by the indexing policy. More...
 
typedef uint32_t CachesMask
 
typedef uint8_t * PacketDataPtr
 
typedef std::list< PacketPtrPacketList
 
typedef uint64_t PacketId
 
typedef std::shared_ptr< RequestRequestPtr
 
typedef uint16_t RequestorID
 
using namespace = gem5::auxv::AuxVector< IntType >
 
typedef statistics::Scalar FaultStat
 
typedef std::list< WaiterStateWaiterList
 
template<typename T >
using ConstVPtr = ConstProxyPtr< T, SETranslatingPortProxy >
 
template<typename T = void>
using VPtr = ProxyPtr< T, SETranslatingPortProxy >
 
typedef std::ostream CheckpointOut
 
typedef struct statfs hst_statfs
 
typedef struct stat hst_stat
 
typedef struct stat64 hst_stat64
 

Enumerations

enum  SDWASelVals : int {
  SDWA_BYTE_0 = 0, SDWA_BYTE_1 = 1, SDWA_BYTE_2 = 2, SDWA_BYTE_3 = 3,
  SDWA_WORD_0 = 4, SDWA_WORD_1 = 5, SDWA_DWORD = 6, SDWA_BYTE_0 = 0,
  SDWA_BYTE_1 = 1, SDWA_BYTE_2 = 2, SDWA_BYTE_3 = 3, SDWA_WORD_0 = 4,
  SDWA_WORD_1 = 5, SDWA_DWORD = 6
}
 
enum  SDWADstVals : int {
  SDWA_UNUSED_PAD = 0, SDWA_UNUSED_SEXT = 1, SDWA_UNUSED_PRESERVE = 2, SDWA_UNUSED_PAD = 0,
  SDWA_UNUSED_SEXT = 1, SDWA_UNUSED_PRESERVE = 2
}
 
enum  SqDPPVals : int {
  SQ_DPP_QUAD_PERM_MAX = 0xFF, SQ_DPP_RESERVED = 0x100, SQ_DPP_ROW_SL1 = 0x101, SQ_DPP_ROW_SL15 = 0x10F,
  SQ_DPP_ROW_SR1 = 0x111, SQ_DPP_ROW_SR15 = 0x11F, SQ_DPP_ROW_RR1 = 0x121, SQ_DPP_ROW_RR15 = 0x12F,
  SQ_DPP_WF_SL1 = 0x130, SQ_DPP_WF_RL1 = 0x134, SQ_DPP_WF_SR1 = 0x138, SQ_DPP_WF_RR1 = 0x13C,
  SQ_DPP_ROW_MIRROR = 0x140, SQ_DPP_ROW_HALF_MIRROR = 0x141, SQ_DPP_ROW_BCAST15 = 0x142, SQ_DPP_ROW_BCAST31 = 0x143,
  SQ_DPP_QUAD_PERM_MAX = 0xFF, SQ_DPP_RESERVED = 0x100, SQ_DPP_ROW_SL1 = 0x101, SQ_DPP_ROW_SL15 = 0x10F,
  SQ_DPP_ROW_SR1 = 0x111, SQ_DPP_ROW_SR15 = 0x11F, SQ_DPP_ROW_RR1 = 0x121, SQ_DPP_ROW_RR15 = 0x12F,
  SQ_DPP_WF_SL1 = 0x130, SQ_DPP_WF_RL1 = 0x134, SQ_DPP_WF_SR1 = 0x138, SQ_DPP_WF_RR1 = 0x13C,
  SQ_DPP_ROW_MIRROR = 0x140, SQ_DPP_ROW_HALF_MIRROR = 0x141, SQ_DPP_ROW_BCAST15 = 0x142, SQ_DPP_ROW_BCAST31 = 0x143
}
 
enum  SDWASelVals : int {
  SDWA_BYTE_0 = 0, SDWA_BYTE_1 = 1, SDWA_BYTE_2 = 2, SDWA_BYTE_3 = 3,
  SDWA_WORD_0 = 4, SDWA_WORD_1 = 5, SDWA_DWORD = 6, SDWA_BYTE_0 = 0,
  SDWA_BYTE_1 = 1, SDWA_BYTE_2 = 2, SDWA_BYTE_3 = 3, SDWA_WORD_0 = 4,
  SDWA_WORD_1 = 5, SDWA_DWORD = 6
}
 
enum  SDWADstVals : int {
  SDWA_UNUSED_PAD = 0, SDWA_UNUSED_SEXT = 1, SDWA_UNUSED_PRESERVE = 2, SDWA_UNUSED_PAD = 0,
  SDWA_UNUSED_SEXT = 1, SDWA_UNUSED_PRESERVE = 2
}
 
enum  SqDPPVals : int {
  SQ_DPP_QUAD_PERM_MAX = 0xFF, SQ_DPP_RESERVED = 0x100, SQ_DPP_ROW_SL1 = 0x101, SQ_DPP_ROW_SL15 = 0x10F,
  SQ_DPP_ROW_SR1 = 0x111, SQ_DPP_ROW_SR15 = 0x11F, SQ_DPP_ROW_RR1 = 0x121, SQ_DPP_ROW_RR15 = 0x12F,
  SQ_DPP_WF_SL1 = 0x130, SQ_DPP_WF_RL1 = 0x134, SQ_DPP_WF_SR1 = 0x138, SQ_DPP_WF_RR1 = 0x13C,
  SQ_DPP_ROW_MIRROR = 0x140, SQ_DPP_ROW_HALF_MIRROR = 0x141, SQ_DPP_ROW_BCAST15 = 0x142, SQ_DPP_ROW_BCAST31 = 0x143,
  SQ_DPP_QUAD_PERM_MAX = 0xFF, SQ_DPP_RESERVED = 0x100, SQ_DPP_ROW_SL1 = 0x101, SQ_DPP_ROW_SL15 = 0x10F,
  SQ_DPP_ROW_SR1 = 0x111, SQ_DPP_ROW_SR15 = 0x11F, SQ_DPP_ROW_RR1 = 0x121, SQ_DPP_ROW_RR15 = 0x12F,
  SQ_DPP_WF_SL1 = 0x130, SQ_DPP_WF_RL1 = 0x134, SQ_DPP_WF_SR1 = 0x138, SQ_DPP_WF_RR1 = 0x13C,
  SQ_DPP_ROW_MIRROR = 0x140, SQ_DPP_ROW_HALF_MIRROR = 0x141, SQ_DPP_ROW_BCAST15 = 0x142, SQ_DPP_ROW_BCAST31 = 0x143
}
 
enum  {
  CoreTag = 0x54410001, MemTag = 0x54410002, RevTag = 0x54410007, SerialTag = 0x54410006,
  CmdTag = 0x54410009, NoneTag = 0x00000000
}
 
enum  RoundingMode { RoundingMode::Downward = 0, RoundingMode::ToNearest = 1, RoundingMode::TowardZero = 2, RoundingMode::Upward = 3 }
 
enum  RegClass {
  IntRegClass, FloatRegClass, VecRegClass, VecElemClass,
  VecPredRegClass, CCRegClass, MiscRegClass
}
 Enumerate the classes of registers. More...
 
enum  TrafficType {
  BIT_COMPLEMENT_ = 0, BIT_REVERSE_ = 1, BIT_ROTATION_ = 2, NEIGHBOR_ = 3,
  SHUFFLE_ = 4, TORNADO_ = 5, TRANSPOSE_ = 6, UNIFORM_RANDOM_ = 7,
  NUM_TRAFFIC_PATTERNS_
}
 
enum  ItsActionType { ItsActionType::INITIAL_NOP, ItsActionType::SEND_REQ, ItsActionType::TERMINATE }
 
enum  { SMMU_CACHE_REPL_ROUND_ROBIN, SMMU_CACHE_REPL_RANDOM, SMMU_CACHE_REPL_LRU }
 
enum  { SMMU_SECURE_SZ = 0x184, SMMU_PAGE_ZERO_SZ = 0x10000, SMMU_PAGE_ONE_SZ = 0x10000, SMMU_REG_SIZE = SMMU_PAGE_ONE_SZ + SMMU_PAGE_ZERO_SZ }
 
enum  {
  STE_CONFIG_ABORT = 0x0, STE_CONFIG_BYPASS = 0x4, STE_CONFIG_STAGE1_ONLY = 0x5, STE_CONFIG_STAGE2_ONLY = 0x6,
  STE_CONFIG_STAGE1_AND_2 = 0x7
}
 
enum  { STAGE1_CFG_1L = 0x0, STAGE1_CFG_2L_4K = 0x1, STAGE1_CFG_2L_64K = 0x2 }
 
enum  { ST_CFG_SPLIT_SHIFT = 6, ST_CD_ADDR_SHIFT = 6, CD_TTB_SHIFT = 4, STE_S2TTB_SHIFT = 4 }
 
enum  { TRANS_GRANULE_4K = 0x0, TRANS_GRANULE_64K = 0x1, TRANS_GRANULE_16K = 0x2, TRANS_GRANULE_INVALID = 0x3 }
 
enum  {
  ST_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL, ST_CFG_SIZE_MASK = 0x000000000000003fULL, ST_CFG_SPLIT_MASK = 0x00000000000007c0ULL, ST_CFG_FMT_MASK = 0x0000000000030000ULL,
  ST_CFG_FMT_LINEAR = 0x0000000000000000ULL, ST_CFG_FMT_2LEVEL = 0x0000000000010000ULL, ST_L2_SPAN_MASK = 0x000000000000001fULL, ST_L2_ADDR_MASK = 0x0000ffffffffffe0ULL,
  VMT_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL, VMT_BASE_SIZE_MASK = 0x000000000000001fULL, Q_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL, Q_BASE_SIZE_MASK = 0x000000000000001fULL,
  E_BASE_ENABLE_MASK = 0x8000000000000000ULL, E_BASE_ADDR_MASK = 0x0000fffffffffffcULL
}
 
enum  {
  CR0_SMMUEN_MASK = 0x1, CR0_PRIQEN_MASK = 0x2, CR0_EVENTQEN_MASK = 0x4, CR0_CMDQEN_MASK = 0x8,
  CR0_ATSCHK_MASK = 0x10, CR0_VMW_MASK = 0x1C0
}
 
enum  SMMUCommandType {
  CMD_PRF_CONFIG = 0x01, CMD_PRF_ADDR = 0x02, CMD_CFGI_STE = 0x03, CMD_CFGI_STE_RANGE = 0x04,
  CMD_CFGI_CD = 0x05, CMD_CFGI_CD_ALL = 0x06, CMD_TLBI_NH_ALL = 0x10, CMD_TLBI_NH_ASID = 0x11,
  CMD_TLBI_NH_VAA = 0x13, CMD_TLBI_NH_VA = 0x12, CMD_TLBI_EL3_ALL = 0x18, CMD_TLBI_EL3_VA = 0x1A,
  CMD_TLBI_EL2_ALL = 0x20, CMD_TLBI_EL2_ASID = 0x21, CMD_TLBI_EL2_VA = 0x22, CMD_TLBI_EL2_VAA = 0x23,
  CMD_TLBI_S2_IPA = 0x2a, CMD_TLBI_S12_VMALL = 0x28, CMD_TLBI_NSNH_ALL = 0x30, CMD_ATC_INV = 0x40,
  CMD_PRI_RESP = 0x41, CMD_RESUME = 0x44, CMD_STALL_TERM = 0x45, CMD_SYNC = 0x46
}
 
enum  SMMUEventTypes { EVT_FAULT = 0x0001 }
 
enum  SMMUEventFlags { EVF_WRITE = 0x0001 }
 
enum  { SMMU_MAX_TRANS_ID = 64 }
 
enum  SMMUActionType {
  ACTION_INITIAL_NOP, ACTION_SEND_REQ, ACTION_SEND_REQ_FINAL, ACTION_SEND_RESP,
  ACTION_SEND_RESP_ATS, ACTION_DELAY, ACTION_SLEEP, ACTION_TERMINATE
}
 
enum  Q_STATE { UNBLOCKED = 0, BLOCKED_BBIT, BLOCKED_BPKT }
 
enum  _hsa_queue_type_t { _HSA_QUEUE_TYPE_MULTI = 0, _HSA_QUEUE_TYPE_SINGLE = 1 }
 
enum  amd_signal_kind_t { AMD_SIGNAL_KIND_INVALID = 0, AMD_SIGNAL_KIND_USER = 1, AMD_SIGNAL_KIND_DOORBELL = -1, AMD_SIGNAL_KIND_LEGACY_DOORBELL = -2 }
 
enum  kfd_smi_event {
  KFD_SMI_EVENT_NONE = 0, KFD_SMI_EVENT_VMFAULT = 1, KFD_SMI_EVENT_THERMAL_THROTTLE = 2, KFD_SMI_EVENT_GPU_PRE_RESET = 3,
  KFD_SMI_EVENT_GPU_POST_RESET = 4
}
 
enum  kfd_mmio_remap { KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0, KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4 }
 
enum  DeviceRegisterAddress {
  CR = 0x00, CFGR = 0x04, MEAR = 0x08, PTSCR = 0x0c,
  ISR = 0x10, IMR = 0x14, IER = 0x18, IHR = 0x1c,
  TXDP = 0x20, TXDP_HI = 0x24, TX_CFG = 0x28, GPIOR = 0x2c,
  RXDP = 0x30, RXDP_HI = 0x34, RX_CFG = 0x38, PQCR = 0x3c,
  WCSR = 0x40, PCR = 0x44, RFCR = 0x48, RFDR = 0x4c,
  BRAR = 0x50, BRDR = 0x54, SRR = 0x58, MIBC = 0x5c,
  MIB_START = 0x60, MIB_END = 0x88, VRCR = 0xbc, VTCR = 0xc0,
  VDR = 0xc4, CCSR = 0xcc, TBICR = 0xe0, TBISR = 0xe4,
  TANAR = 0xe8, TANLPAR = 0xec, TANER = 0xf0, TESR = 0xf4,
  M5REG = 0xf8, LAST = 0xf8, RESERVED = 0xfc
}
 
enum  ChipCommandRegister {
  CR_TXE = 0x00000001, CR_TXD = 0x00000002, CR_RXE = 0x00000004, CR_RXD = 0x00000008,
  CR_TXR = 0x00000010, CR_RXR = 0x00000020, CR_SWI = 0x00000080, CR_RST = 0x00000100
}
 
enum  ConfigurationRegisters {
  CFGR_ZERO = 0x00000000, CFGR_LNKSTS = 0x80000000, CFGR_SPDSTS = 0x60000000, CFGR_SPDSTS1 = 0x40000000,
  CFGR_SPDSTS0 = 0x20000000, CFGR_DUPSTS = 0x10000000, CFGR_TBI_EN = 0x01000000, CFGR_RESERVED = 0x0e000000,
  CFGR_MODE_1000 = 0x00400000, CFGR_AUTO_1000 = 0x00200000, CFGR_PINT_CTL = 0x001c0000, CFGR_PINT_DUPSTS = 0x00100000,
  CFGR_PINT_LNKSTS = 0x00080000, CFGR_PINT_SPDSTS = 0x00040000, CFGR_TMRTEST = 0x00020000, CFGR_MRM_DIS = 0x00010000,
  CFGR_MWI_DIS = 0x00008000, CFGR_T64ADDR = 0x00004000, CFGR_PCI64_DET = 0x00002000, CFGR_DATA64_EN = 0x00001000,
  CFGR_M64ADDR = 0x00000800, CFGR_PHY_RST = 0x00000400, CFGR_PHY_DIS = 0x00000200, CFGR_EXTSTS_EN = 0x00000100,
  CFGR_REQALG = 0x00000080, CFGR_SB = 0x00000040, CFGR_POW = 0x00000020, CFGR_EXD = 0x00000010,
  CFGR_PESEL = 0x00000008, CFGR_BROM_DIS = 0x00000004, CFGR_EXT_125 = 0x00000002, CFGR_BEM = 0x00000001
}
 
enum  EEPROMAccessRegister {
  MEAR_EEDI = 0x00000001, MEAR_EEDO = 0x00000002, MEAR_EECLK = 0x00000004, MEAR_EESEL = 0x00000008,
  MEAR_MDIO = 0x00000010, MEAR_MDDIR = 0x00000020, MEAR_MDC = 0x00000040
}
 
enum  PCITestControlRegister {
  PTSCR_EEBIST_FAIL = 0x00000001, PTSCR_EEBIST_EN = 0x00000002, PTSCR_EELOAD_EN = 0x00000004, PTSCR_RBIST_FAIL = 0x000001b8,
  PTSCR_RBIST_DONE = 0x00000200, PTSCR_RBIST_EN = 0x00000400, PTSCR_RBIST_RST = 0x00002000, PTSCR_RBIST_RDONLY = 0x000003f9
}
 
enum  InterruptStatusRegister {
  ISR_RESERVE = 0x80000000, ISR_TXDESC3 = 0x40000000, ISR_TXDESC2 = 0x20000000, ISR_TXDESC1 = 0x10000000,
  ISR_TXDESC0 = 0x08000000, ISR_RXDESC3 = 0x04000000, ISR_RXDESC2 = 0x02000000, ISR_RXDESC1 = 0x01000000,
  ISR_RXDESC0 = 0x00800000, ISR_TXRCMP = 0x00400000, ISR_RXRCMP = 0x00200000, ISR_DPERR = 0x00100000,
  ISR_SSERR = 0x00080000, ISR_RMABT = 0x00040000, ISR_RTAB = 0x00020000, ISR_RXSOVR = 0x00010000,
  ISR_HIBINT = 0x00008000, ISR_PHY = 0x00004000, ISR_PME = 0x00002000, ISR_SWI = 0x00001000,
  ISR_MIB = 0x00000800, ISR_TXURN = 0x00000400, ISR_TXIDLE = 0x00000200, ISR_TXERR = 0x00000100,
  ISR_TXDESC = 0x00000080, ISR_TXOK = 0x00000040, ISR_RXORN = 0x00000020, ISR_RXIDLE = 0x00000010,
  ISR_RXEARLY = 0x00000008, ISR_RXERR = 0x00000004, ISR_RXDESC = 0x00000002, ISR_RXOK = 0x00000001,
  ISR_ALL = 0x7FFFFFFF, ISR_DELAY, ISR_NODELAY = (ISR_ALL & ~ISR_DELAY), ISR_IMPL,
  ISR_NOIMPL = (ISR_ALL & ~ISR_IMPL)
}
 
enum  TransmitConfigurationRegister {
  TX_CFG_CSI = 0x80000000, TX_CFG_HBI = 0x40000000, TX_CFG_MLB = 0x20000000, TX_CFG_ATP = 0x10000000,
  TX_CFG_ECRETRY = 0x00800000, TX_CFG_BRST_DIS = 0x00080000, TX_CFG_MXDMA1024 = 0x00000000, TX_CFG_MXDMA512 = 0x00700000,
  TX_CFG_MXDMA256 = 0x00600000, TX_CFG_MXDMA128 = 0x00500000, TX_CFG_MXDMA64 = 0x00400000, TX_CFG_MXDMA32 = 0x00300000,
  TX_CFG_MXDMA16 = 0x00200000, TX_CFG_MXDMA8 = 0x00100000, TX_CFG_MXDMA = 0x00700000, TX_CFG_FLTH_MASK = 0x0000ff00,
  TX_CFG_DRTH_MASK = 0x000000ff
}
 
enum  GeneralPurposeIOControlRegister {
  GPIOR_UNUSED = 0xffff8000, GPIOR_GP5_IN = 0x00004000, GPIOR_GP4_IN = 0x00002000, GPIOR_GP3_IN = 0x00001000,
  GPIOR_GP2_IN = 0x00000800, GPIOR_GP1_IN = 0x00000400, GPIOR_GP5_OE = 0x00000200, GPIOR_GP4_OE = 0x00000100,
  GPIOR_GP3_OE = 0x00000080, GPIOR_GP2_OE = 0x00000040, GPIOR_GP1_OE = 0x00000020, GPIOR_GP5_OUT = 0x00000010,
  GPIOR_GP4_OUT = 0x00000008, GPIOR_GP3_OUT = 0x00000004, GPIOR_GP2_OUT = 0x00000002, GPIOR_GP1_OUT = 0x00000001
}
 
enum  ReceiveConfigurationRegister {
  RX_CFG_AEP = 0x80000000, RX_CFG_ARP = 0x40000000, RX_CFG_STRIPCRC = 0x20000000, RX_CFG_RX_FD = 0x10000000,
  RX_CFG_ALP = 0x08000000, RX_CFG_AIRL = 0x04000000, RX_CFG_MXDMA512 = 0x00700000, RX_CFG_MXDMA = 0x00700000,
  RX_CFG_DRTH = 0x0000003e, RX_CFG_DRTH0 = 0x00000002
}
 
enum  PauseControlStatusRegister {
  PCR_PSEN = (1 << 31), PCR_PS_MCAST = (1 << 30), PCR_PS_DA = (1 << 29), PCR_STHI_8 = (3 << 23),
  PCR_STLO_4 = (1 << 23), PCR_FFHI_8K = (3 << 21), PCR_FFLO_4K = (1 << 21), PCR_PAUSE_CNT = 0xFFFE
}
 
enum  ReceiveFilterMatchControlRegister {
  RFCR_RFEN = 0x80000000, RFCR_AAB = 0x40000000, RFCR_AAM = 0x20000000, RFCR_AAU = 0x10000000,
  RFCR_APM = 0x08000000, RFCR_APAT = 0x07800000, RFCR_APAT3 = 0x04000000, RFCR_APAT2 = 0x02000000,
  RFCR_APAT1 = 0x01000000, RFCR_APAT0 = 0x00800000, RFCR_AARP = 0x00400000, RFCR_MHEN = 0x00200000,
  RFCR_UHEN = 0x00100000, RFCR_ULM = 0x00080000, RFCR_RFADDR = 0x000003ff
}
 
enum  ReceiveFilterMatchDataRegister { RFDR_BMASK = 0x00030000, RFDR_RFDATA0 = 0x000000ff, RFDR_RFDATA1 = 0x0000ff00 }
 
enum  ManagementInformationBaseControlRegister { MIBC_MIBS = 0x00000008, MIBC_ACLR = 0x00000004, MIBC_FRZ = 0x00000002, MIBC_WRN = 0x00000001 }
 
enum  VLANIPReceiveControlRegister {
  VRCR_RUDPE = 0x00000080, VRCR_RTCPE = 0x00000040, VRCR_RIPE = 0x00000020, VRCR_IPEN = 0x00000010,
  VRCR_DUTF = 0x00000008, VRCR_DVTF = 0x00000004, VRCR_VTREN = 0x00000002, VRCR_VTDEN = 0x00000001
}
 
enum  VLANIPTransmitControlRegister { VTCR_PPCHK = 0x00000008, VTCR_GCHK = 0x00000004, VTCR_VPPTI = 0x00000002, VTCR_VGTI = 0x00000001 }
 
enum  ClockrunControlStatusRegister { CCSR_CLKRUN_EN = 0x00000001 }
 
enum  TBIControlRegister { TBICR_MR_LOOPBACK = 0x00004000, TBICR_MR_AN_ENABLE = 0x00001000, TBICR_MR_RESTART_AN = 0x00000200 }
 
enum  TBIStatusRegister { TBISR_MR_LINK_STATUS = 0x00000020, TBISR_MR_AN_COMPLETE = 0x00000004 }
 
enum  TBIAutoNegotiationAdvertisementRegister {
  TANAR_NP = 0x00008000, TANAR_RF2 = 0x00002000, TANAR_RF1 = 0x00001000, TANAR_PS2 = 0x00000100,
  TANAR_PS1 = 0x00000080, TANAR_HALF_DUP = 0x00000040, TANAR_FULL_DUP = 0x00000020, TANAR_UNUSED = 0x00000E1F
}
 
enum  M5ControlRegister { M5REG_RESERVED = 0xfffffffc, M5REG_RSS = 0x00000004, M5REG_RX_THREAD = 0x00000002, M5REG_TX_THREAD = 0x00000001 }
 
enum  CMDSTSFlatsForDescriptors {
  CMDSTS_OWN = 0x80000000, CMDSTS_MORE = 0x40000000, CMDSTS_INTR = 0x20000000, CMDSTS_ERR = 0x10000000,
  CMDSTS_OK = 0x08000000, CMDSTS_LEN_MASK = 0x0000ffff, CMDSTS_DEST_MASK = 0x01800000, CMDSTS_DEST_SELF = 0x00800000,
  CMDSTS_DEST_MULTI = 0x01000000
}
 
enum  ExtendedFlagsForDescriptors {
  EXTSTS_UDPERR = 0x00400000, EXTSTS_UDPPKT = 0x00200000, EXTSTS_TCPERR = 0x00100000, EXTSTS_TCPPKT = 0x00080000,
  EXTSTS_IPERR = 0x00040000, EXTSTS_IPPKT = 0x00020000
}
 
enum  PciIntPin : uint8_t {
  PciIntPin::NO_INT =0, PciIntPin::INTA, PciIntPin::INTB, PciIntPin::INTC,
  PciIntPin::INTD
}
 
enum  BMIRegOffset { BMICommand = 0x0, BMIStatus = 0x2, BMIDescTablePtr = 0x4 }
 
enum  Events_t {
  None = 0, Transfer, ReadWait, WriteWait,
  PrdRead, DmaRead, DmaWrite
}
 
enum  DevAction_t {
  ACT_NONE = 0, ACT_CMD_WRITE, ACT_CMD_COMPLETE, ACT_CMD_ERROR,
  ACT_SELECT_WRITE, ACT_STAT_READ, ACT_DATA_READY, ACT_DATA_READ_BYTE,
  ACT_DATA_READ_SHORT, ACT_DATA_WRITE_BYTE, ACT_DATA_WRITE_SHORT, ACT_DMA_READY,
  ACT_DMA_DONE, ACT_SRST_SET, ACT_SRST_CLEAR
}
 
enum  DevState_t {
  Device_Idle_S = 0, Device_Idle_SI, Device_Idle_NS, Device_Srst,
  Command_Execution, Prepare_Data_In, Data_Ready_INTRQ_In, Transfer_Data_In,
  Prepare_Data_Out, Data_Ready_INTRQ_Out, Transfer_Data_Out, Prepare_Data_Dma,
  Transfer_Data_Dma, Device_Dma_Abort
}
 
enum  DmaState_t { Dma_Idle = 0, Dma_Start, Dma_Transfer }
 
enum  EXEC_POLICY { OLDEST = 0, RR }
 
enum  TLB_CACHE { TLB_MISS_CACHE_MISS = 0, TLB_MISS_CACHE_HIT, TLB_HIT_CACHE_MISS, TLB_HIT_CACHE_HIT }
 
enum  STAT_STATUS { IdleExec, BusyExec, PostExec }
 
enum  DISPATCH_STATUS { EMPTY = 0, EXREADY, SKIP }
 
enum  ScalarRegInitFields : int {
  PrivateSegBuf = 0, DispatchPtr = 1, QueuePtr = 2, KernargSegPtr = 3,
  DispatchId = 4, FlatScratchInit = 5, PrivateSegSize = 6, GridWorkgroupCountX = 7,
  GridWorkgroupCountY = 8, GridWorkgroupCountZ = 9, WorkgroupIdX = 10, WorkgroupIdY = 11,
  WorkgroupIdZ = 12, WorkgroupInfo = 13, PrivSegWaveByteOffset = 14, NumScalarInitFields = 15
}
 these enums represent the indices into the initialRegState bitfields in HsaKernelInfo. More...
 
enum  VectorRegInitFields : int { WorkitemIdX = 0, WorkitemIdY = 1, WorkitemIdZ = 2, NumVectorInitFields = 3 }
 
enum  InstMemoryHop : int {
  Initiate = 0, CoalsrSend = 1, CoalsrRecv = 2, GMEnqueue = 3,
  Complete = 4, InstMemoryHopMax = 5
}
 
enum  BlockMemoryHop : int { BlockSend = 0, BlockRecv = 1 }
 
enum  HtmFailureFaultCause : int {
  HtmFailureFaultCause::INVALID = -1, HtmFailureFaultCause::EXPLICIT, HtmFailureFaultCause::NEST, HtmFailureFaultCause::SIZE,
  HtmFailureFaultCause::EXCEPTION, HtmFailureFaultCause::MEMORY, HtmFailureFaultCause::OTHER, HtmFailureFaultCause::NUM_CAUSES
}
 
enum  HtmCacheFailure { HtmCacheFailure::NO_FAIL, HtmCacheFailure::FAIL_SELF, HtmCacheFailure::FAIL_REMOTE, HtmCacheFailure::FAIL_OTHER }
 
enum  AuxiliaryVectorType {
  GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATE_AT =(NULL, Null),
  GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATE_AT =(NULL, Null),
  GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATE_AT =(NULL, Null),
  GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATE_AT =(NULL, Null),
  GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATED_ENUM_VAL,
  GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATE_AT =(NULL, Null), GEM5_DEPRECATE_AT =(NULL, Null)
}
 
enum  DrainState { DrainState::Running, DrainState::Draining, DrainState::Drained, DrainState::Resuming }
 Object drain/handover states. More...
 

Functions

template<typename T , int N>
void initMemReqHelper (GPUDynInstPtr gpuDynInst, MemCmd mem_req_type, bool is_atomic=false)
 Helper function for instructions declared in op_encodings. More...
 
template<typename T , int N>
void initMemReqScalarHelper (GPUDynInstPtr gpuDynInst, MemCmd mem_req_type)
 Helper function for scalar instructions declared in op_encodings. More...
 
 GEM5_DEPRECATED_NAMESPACE (GuestABI, guest_abi)
 
 GEM5_DEPRECATED_NAMESPACE (FastModel, fastmodel)
 
const static uint64_t KVM_REG64_TTBR0 (regCp64(15, 0, 2))
 
const static uint64_t KVM_REG64_TTBR1 (regCp64(15, 1, 2))
 
constexpr uint64_t kvmXReg (const int num)
 
constexpr uint64_t kvmFPReg (const int num)
 
static bool tryTranslate (ThreadContext *tc, Addr addr)
 
std::ostream & operator<< (std::ostream &os, const ArmSemihosting::InPlaceArg &ipa)
 
 GEM5_DEPRECATED_NAMESPACE (FreeBSD, free_bsd)
 
 GEM5_DEPRECATED_NAMESPACE (Linux, linux)
 
template<class XC >
Fault initiateMemRead (XC *xc, Addr addr, std::size_t size, Request::Flags flags, const std::vector< bool > &byte_enable)
 
template<class XC , class MemT >
Fault initiateMemRead (XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem, Request::Flags flags)
 Initiate a read from memory in timing mode. More...
 
template<ByteOrder Order, class MemT >
void getMem (PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
 Extract the data returned from a timing mode read. More...
 
template<class MemT >
void getMemLE (PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
 
template<class MemT >
void getMemBE (PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
 
template<class XC >
Fault readMemAtomic (XC *xc, Addr addr, uint8_t *mem, std::size_t size, Request::Flags flags, const std::vector< bool > &byte_enable)
 Read from memory in atomic mode. More...
 
template<ByteOrder Order, class XC , class MemT >
Fault readMemAtomic (XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem, Request::Flags flags)
 Read from memory in atomic mode. More...
 
template<class XC , class MemT >
Fault readMemAtomicLE (XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem, Request::Flags flags)
 
template<class XC , class MemT >
Fault readMemAtomicBE (XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem, Request::Flags flags)
 
template<class XC >
Fault writeMemTiming (XC *xc, uint8_t *mem, Addr addr, std::size_t size, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)
 Write to memory in timing mode. More...
 
template<ByteOrder Order, class XC , class MemT >
Fault writeMemTiming (XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr, Request::Flags flags, uint64_t *res)
 
template<class XC , class MemT >
Fault writeMemTimingLE (XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr, Request::Flags flags, uint64_t *res)
 
template<class XC , class MemT >
Fault writeMemTimingBE (XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr, Request::Flags flags, uint64_t *res)
 
template<class XC >
Fault writeMemAtomic (XC *xc, uint8_t *mem, Addr addr, std::size_t size, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)
 Write to memory in atomic mode. More...
 
template<ByteOrder Order, class XC , class MemT >
Fault writeMemAtomic (XC *xc, Trace::InstRecord *traceData, const MemT &mem, Addr addr, Request::Flags flags, uint64_t *res)
 
template<class XC , class MemT >
Fault writeMemAtomicLE (XC *xc, Trace::InstRecord *traceData, const MemT &mem, Addr addr, Request::Flags flags, uint64_t *res)
 
template<class XC , class MemT >
Fault writeMemAtomicBE (XC *xc, Trace::InstRecord *traceData, const MemT &mem, Addr addr, Request::Flags flags, uint64_t *res)
 
template<ByteOrder Order, class XC , class MemT >
Fault amoMemAtomic (XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr, Request::Flags flags, AtomicOpFunctor *_amo_op)
 Do atomic read-modify-write (AMO) in atomic mode. More...
 
template<class XC , class MemT >
Fault amoMemAtomicLE (XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr, Request::Flags flags, AtomicOpFunctor *_amo_op)
 
template<class XC , class MemT >
Fault amoMemAtomicBE (XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr, Request::Flags flags, AtomicOpFunctor *_amo_op)
 
template<class XC , class MemT >
Fault initiateMemAMO (XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem, Request::Flags flags, AtomicOpFunctor *_amo_op)
 Do atomic read-modify-wrote (AMO) in timing mode. More...
 
typedef GEM5_ALIGNED (8) uint64_t uint64_ta
 
 GEM5_DEPRECATED_NAMESPACE (Loader, loader)
 
static Addr buildKey (Addr vpn, uint16_t asid)
 
static std::string getMiscRegName (RegIndex index)
 
template<class T >
void writeVal (T val, PortProxy &proxy, Addr &addr)
 
template<class T >
uint8_t writeOutField (PortProxy &proxy, Addr addr, T val)
 
uint8_t writeOutString (PortProxy &proxy, Addr addr, std::string str, int length)
 
template<class T >
uint64_t composeBitVector (T vec)
 
int divideFromConf (uint32_t conf)
 
template<>
void paramOut (CheckpointOut &cp, const std::string &name, ExtMachInst const &machInst)
 
template<>
void paramIn (CheckpointIn &cp, const std::string &name, ExtMachInst &machInst)
 
AddrRange RangeEx (Addr start, Addr end)
 
AddrRange RangeIn (Addr start, Addr end)
 
AddrRange RangeSize (Addr start, Addr size)
 
ssize_t atomic_read (int fd, void *s, size_t n)
 
ssize_t atomic_write (int fd, const void *s, size_t n)
 
constexpr uint64_t mask (unsigned nbits)
 Generate a 64-bit mask of 'nbits' 1s, right justified. More...
 
template<class T >
constexpr T bits (T val, unsigned first, unsigned last)
 Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it. More...
 
template<class T >
constexpr T bits (T val, unsigned bit)
 Extract the bit from this position from 'val' and right justify it. More...
 
template<class T >
constexpr T mbits (T val, unsigned first, unsigned last)
 Mask off the given bits in place like bits() but without shifting. More...
 
constexpr uint64_t mask (unsigned first, unsigned last)
 
template<int N>
constexpr uint64_t sext (uint64_t val)
 Sign-extend an N-bit value to 64 bits. More...
 
template<int N>
constexpr uint64_t szext (uint64_t val)
 Sign-extend an N-bit value to 64 bits. More...
 
template<class T , class B >
constexpr T insertBits (T val, unsigned first, unsigned last, B bit_val)
 Returns val with bits first to last set to the LSBs of bit_val. More...
 
template<class T , class B >
constexpr T insertBits (T val, unsigned bit, B bit_val)
 Overloaded for access to only one bit in value. More...
 
template<class T , class B >
constexpr void replaceBits (T &val, unsigned first, unsigned last, B bit_val)
 A convenience function to replace bits first to last of val with bit_val in place. More...
 
template<class T , class B >
constexpr void replaceBits (T &val, unsigned bit, B bit_val)
 Overloaded function to allow to access only 1 bit. More...
 
template<class T >
std::enable_if_t< std::is_integral< T >::value &&sizeof(T) !=1, T > reverseBits (T val, size_t size=sizeof(T))
 Takes a value and returns the bit reversed version. More...
 
template<class T >
std::enable_if_t< std::is_integral< T >::value &&sizeof(T)==1, T > reverseBits (T val, size_t size=sizeof(T))
 
constexpr int findMsbSet (uint64_t val)
 Returns the bit position of the MSB that is set in the input. More...
 
constexpr int findLsbSet (uint64_t val)
 Returns the bit position of the LSB that is set in the input. More...
 
constexpr int popCount (uint64_t val)
 Returns the number of set ones in the provided value. More...
 
constexpr uint64_t alignToPowerOfTwo (uint64_t val)
 Align to the next highest power of two. More...
 
constexpr int ctz32 (uint32_t value)
 Count trailing zeros in a 32-bit value. More...
 
constexpr int ctz64 (uint64_t value)
 Count trailing zeros in a 64-bit value. More...
 
template<typename T >
std::ostream & operator<< (std::ostream &os, const BitUnionType< T > &bu)
 A default << operator which casts a bitunion to its underlying type and passes it to bitfield_backend::bitfieldBackendPrinter. More...
 
template<class T , class U >
safe_cast (U ptr)
 
std::ostream & operator<< (std::ostream &out, const ChannelAddr &addr)
 
template<typename T >
void arrayParamOut (CheckpointOut &cp, const std::string &name, const CircleBuf< T > &param)
 
template<typename T >
void arrayParamIn (CheckpointIn &cp, const std::string &name, CircleBuf< T > &param)
 
template<typename T >
void arrayParamOut (CheckpointOut &cp, const std::string &name, const Fifo< T > &param)
 
template<typename T >
void arrayParamIn (CheckpointIn &cp, const std::string &name, Fifo< T > &param)
 
static bool findCarry (int width, uint64_t dest, uint64_t src1, uint64_t src2)
 Calculate the carry flag from an addition. More...
 
static bool findOverflow (int width, uint64_t dest, uint64_t src1, uint64_t src2)
 Calculate the overflow flag from an addition. More...
 
static bool findParity (int width, uint64_t dest)
 Calculate the parity of a value. More...
 
static bool findNegative (int width, uint64_t dest)
 Calculate the negative flag. More...
 
static bool findZero (int width, uint64_t dest)
 Calculate the zero flag. More...
 
void ccprintf (cp::Print &print)
 
template<typename T , typename ... Args>
void ccprintf (cp::Print &print, const T &value, const Args &...args)
 
template<typename ... Args>
void ccprintf (std::ostream &stream, const char *format, const Args &...args)
 
template<typename ... Args>
void cprintf (const char *format, const Args &...args)
 
template<typename ... Args>
std::string csprintf (const char *format, const Args &...args)
 
template<typename ... Args>
void ccprintf (std::ostream &stream, const std::string &format, const Args &...args)
 
template<typename ... Args>
void cprintf (const std::string &format, const Args &...args)
 
template<typename ... Args>
std::string csprintf (const std::string &format, const Args &...args)
 
void handle_alarm (int signal)
 
void do_test (int seconds)
 
int main ()
 
template<uint32_t Poly>
uint32_t crc32 (const uint8_t *data, uint32_t crc, std::size_t size)
 Evaluate the CRC32 of the first size bytes of a data buffer, using a specific polynomium and an initial value. More...
 
 GEM5_DEPRECATED_NAMESPACE (Debug, debug)
 
void setDebugFlag (const char *string)
 
void clearDebugFlag (const char *string)
 
void dumpDebugFlags (std::ostream &os)
 
void setFpRound (RoundingMode rm)
 
RoundingMode getFpRound ()
 
 GEM5_DEPRECATED_NAMESPACE (BloomFilter, bloom_filter)
 
uint64_t procInfo (const char *filename, const char *target)
 
uint64_t memUsage ()
 Determine the simulator process' total virtual memory usage. More...
 
std::unique_ptr< ImgWritercreateImgWriter (enums::ImageFormat type, const FrameBuffer *fb)
 Factory Function which allocates a ImgWriter object and returns a smart pointer to it. More...
 
 GEM5_DEPRECATED_NAMESPACE (Net, networking)
 
template<class T >
static constexpr std::enable_if_t< std::is_integral< T >::value, int > floorLog2 (T x)
 
template<class T >
static constexpr int ceilLog2 (const T &n)
 
template<class T >
static constexpr bool isPowerOf2 (const T &n)
 
template<class T , class U >
static constexpr T divCeil (const T &a, const U &b)
 
template<typename T >
static constexpr std::enable_if_t< sizeof(T)==sizeof(uint64_t)> mulUnsigned (std::make_unsigned_t< T > &high, std::make_unsigned_t< T > &low, std::make_unsigned_t< T > val_a, std::make_unsigned_t< T > val_b)
 
template<typename T >
static constexpr std::enable_if_t< sizeof(T)==sizeof(uint64_t)> mulSignedManual (std::make_signed_t< T > &high, std::make_signed_t< T > &low, std::make_signed_t< T > val_a, std::make_signed_t< T > val_b)
 
template<typename T >
static constexpr std::enable_if_t< sizeof(T)==sizeof(uint64_t)> mulSigned (std::make_signed_t< T > &high, std::make_signed_t< T > &low, std::make_signed_t< T > val_a, std::make_signed_t< T > val_b)
 
template<typename T >
static constexpr std::pair< std::make_unsigned_t< T >, std::make_unsigned_t< T > > mulUnsigned (std::make_unsigned_t< T > val_a, std::make_unsigned_t< T > val_b)
 
template<typename T >
static constexpr std::pair< std::make_signed_t< T >, std::make_signed_t< T > > mulSigned (std::make_signed_t< T > val_a, std::make_signed_t< T > val_b)
 
template<class T , class U >
static constexpr T roundUp (const T &val, const U &align)
 This function is used to align addresses in memory. More...
 
template<class T , class U >
static constexpr T roundDown (const T &val, const U &align)
 This function is used to align addresses in memory. More...
 
static constexpr int log2i (int value)
 Calculate the log2 of a power of 2 integer. More...
 
bool operator== (const Pixel &lhs, const Pixel &rhs)
 
bool to_number (const std::string &value, Pixel &retval)
 
std::ostream & operator<< (std::ostream &os, const Pixel &pxl)
 
static void writePng (png_structp pngPtr, png_bytep data, png_size_t length)
 Write callback to use with libpng APIs. More...
 
template<class ArgT >
static int fcntlHelper (int fd, int cmd, ArgT arg)
 
static int fcntlHelper (int fd, int cmd)
 
template<class T >
bool operator== (const RefCountingPtr< T > &l, const RefCountingPtr< T > &r)
 Check for equality of two reference counting pointers. More...
 
template<class T >
bool operator== (const RefCountingPtr< T > &l, const T *r)
 Check for equality of of a reference counting pointers and a regular pointer. More...
 
template<class T >
bool operator== (const T *l, const RefCountingPtr< T > &r)
 Check for equality of of a reference counting pointers and a regular pointer. More...
 
template<class T >
bool operator!= (const RefCountingPtr< T > &l, const RefCountingPtr< T > &r)
 Check for inequality of two reference counting pointers. More...
 
template<class T >
bool operator!= (const RefCountingPtr< T > &l, const T *r)
 Check for inequality of of a reference counting pointers and a regular pointer. More...
 
template<class T >
bool operator!= (const T *l, const RefCountingPtr< T > &r)
 Check for inequality of of a reference counting pointers and a regular pointer. More...
 
 GEM5_DEPRECATED_NAMESPACE (Stats, statistics)
 
void debugDumpStats ()
 
template<typename T >
bool emptyStrings (const T &labels)
 Check if all strings in a container are empty. More...
 
bool split_first (const std::string &s, std::string &lhs, std::string &rhs, char c)
 
bool split_last (const std::string &s, std::string &lhs, std::string &rhs, char c)
 
void tokenize (std::vector< std::string > &v, const std::string &s, char token, bool ignore)
 
void eat_lead_white (std::string &s)
 
void eat_end_white (std::string &s)
 
void eat_white (std::string &s)
 
std::string to_lower (const std::string &s)
 
template<class T >
std::enable_if_t<(std::is_integral< T >::value||std::is_floating_point< T >::value||std::is_enum< T >::value) &&!std::is_same< bool, T >::value, bool > to_number (const std::string &value, T &retval)
 Turn a string representation of a number, either integral, floating point, or enum into an actual number. More...
 
bool to_bool (const std::string &value, bool &retval)
 Turn a string representation of a boolean into a boolean value. More...
 
std::string quote (const std::string &s)
 
bool startswith (const char *s, const char *prefix)
 Return true if 's' starts with the prefix string 'prefix'. More...
 
bool startswith (const std::string &s, const char *prefix)
 Return true if 's' starts with the prefix string 'prefix'. More...
 
bool startswith (const std::string &s, const std::string &prefix)
 Return true if 's' starts with the prefix string 'prefix'. More...
 
std::ostream & operator<< (std::ostream &out, const Temperature &temp)
 
constexpr Temperature operator* (const Temperature &lhs, const double &rhs)
 
constexpr Temperature operator* (const double &lhs, const Temperature &rhs)
 
constexpr Temperature operator/ (const Temperature &lhs, const double &rhs)
 
void sleep (const Time &time)
 
time_t mkutctime (struct tm *time)
 
bool operator== (const Time &l, const Time &r)
 
bool operator!= (const Time &l, const Time &r)
 
bool operator< (const Time &l, const Time &r)
 
bool operator<= (const Time &l, const Time &r)
 
bool operator> (const Time &l, const Time &r)
 
bool operator>= (const Time &l, const Time &r)
 
Time operator+ (const Time &l, const Time &r)
 
Time operator- (const Time &l, const Time &r)
 
std::ostream & operator<< (std::ostream &out, const Time &time)
 
std::ostream & operator<< (std::ostream &out, const Cycles &cycles)
 
static MicroPC romMicroPC (MicroPC upc)
 
static MicroPC normalMicroPC (MicroPC upc)
 
static bool isRomMicroPC (MicroPC upc)
 
static uint32_t floatToBits32 (float val)
 
static uint64_t floatToBits64 (double val)
 
static uint64_t floatToBits (double val)
 
static uint32_t floatToBits (float val)
 
static float bitsToFloat32 (uint32_t val)
 
static double bitsToFloat64 (uint64_t val)
 
static double bitsToFloat (uint64_t val)
 
static float bitsToFloat (uint32_t val)
 
 GEM5_DEPRECATED_NAMESPACE (DecodeCache, decode_cache)
 
static void onKickSignal (int signo, siginfo_t *si, void *data)
 Dummy handler for KVM kick signals. More...
 
static pid_t sysGettid ()
 
template<typename STRUCT , typename ENTRY >
static STRUCT * newVarStruct (size_t entries)
 
static void dumpKvm (const struct kvm_regs &regs)
 
static void dumpKvm (const char *reg_name, const struct kvm_segment &seg)
 
static void dumpKvm (const char *reg_name, const struct kvm_dtable &dtable)
 
static void dumpKvm (const struct kvm_sregs &sregs)
 
static void dumpFpuSpec (const struct FXSave &xs)
 
static void dumpFpuSpec (const struct kvm_fpu &fpu)
 
template<typename T >
static void dumpFpuCommon (const T &fpu)
 
static void dumpKvm (const struct kvm_fpu &fpu)
 
static void dumpKvm (const struct kvm_xsave &xsave)
 
static void dumpKvm (const struct kvm_msrs &msrs)
 
static void dumpKvm (const struct kvm_xcrs &regs)
 
static void dumpKvm (const struct kvm_vcpu_events &events)
 
static bool isCanonicalAddress (uint64_t addr)
 
static void checkSeg (const char *name, const int idx, const struct kvm_segment &seg, struct kvm_sregs sregs)
 
static void setKvmSegmentReg (ThreadContext *tc, struct kvm_segment &kvm_seg, const int index)
 
static void setKvmDTableReg (ThreadContext *tc, struct kvm_dtable &kvm_dtable, const int index)
 
static void forceSegAccessed (struct kvm_segment &seg)
 
template<typename T >
static void updateKvmStateFPUCommon (ThreadContext *tc, T &fpu)
 
void setContextSegment (ThreadContext *tc, const struct kvm_segment &kvm_seg, const int index)
 
void setContextSegment (ThreadContext *tc, const struct kvm_dtable &kvm_dtable, const int index)
 
template<typename T >
static void updateThreadContextFPUCommon (ThreadContext *tc, const T &fpu)
 
static struct kvm_cpuid_entry2 makeKvmCpuid (uint32_t function, uint32_t index, CpuidResult &result)
 
 GEM5_DEPRECATED_NAMESPACE (Minor, minor)
 
void change_thread_state (ThreadID tid, int activate, int priority)
 Changes the status and priority of the thread with the given number. More...
 
std::ostream & operator<< (std::ostream &out, const Check &obj)
 
std::ostream & operator<< (std::ostream &out, const CheckTable &obj)
 
std::ostream & operator<< (std::ostream &out, const RubyTester &obj)
 
void pybind_init_tracers (py::module_ &m_native)
 
void takeOverFrom (ThreadContext &new_tc, ThreadContext &old_tc)
 Copy state between thread contexts in preparation for CPU handover. More...
 
Addr addrBlockOffset (Addr addr, Addr block_size)
 Calculates the offset of a given address wrt aligned fixed-size blocks. More...
 
Addr addrBlockAlign (Addr addr, Addr block_size)
 Returns the address of the closest aligned fixed-size block to the given address. More...
 
bool transferNeedsBurst (Addr addr, unsigned int size, unsigned int block_size)
 Returns true if the given memory access (address, size) needs to be fragmented across aligned fixed-size blocks. More...
 
bool isAnyActiveElement (const std::vector< bool >::const_iterator &it_start, const std::vector< bool >::const_iterator &it_end)
 Test if there is any active element in an enablement range. More...
 
 GEM5_DEPRECATED_NAMESPACE (SCMI, scmi)
 
static uint8_t bcdize (uint8_t val)
 
static uint8_t unbcdize (uint8_t val)
 
 GEM5_DEPRECATED_NAMESPACE (iGbReg, igbreg)
 
static int SPDSTS_POLARITY (int lnksts)
 
 GEM5_DEPRECATED_NAMESPACE (Sinic, sinic)
 
 GEM5_DEPRECATED_NAMESPACE (CopyEngineReg, copy_engine_reg)
 
 GEM5_DEPRECATED_NAMESPACE (Ps2, ps2)
 
void SafeRead (std::ifstream &stream, void *data, int count)
 
template<class T >
void SafeRead (std::ifstream &stream, T &data)
 
template<class T >
void SafeReadSwap (std::ifstream &stream, T &data)
 
void SafeWrite (std::ofstream &stream, const void *data, int count)
 
template<class T >
void SafeWrite (std::ofstream &stream, const T &data)
 
template<class T >
void SafeWriteSwap (std::ofstream &stream, const T &data)
 
template<typename T >
p9toh (T v)
 Convert p9 byte order (LE) to host byte order. More...
 
template<typename T >
htop9 (T v)
 Convert host byte order to p9 byte order (LE) More...
 
template<>
P9MsgHeader p9toh (P9MsgHeader v)
 
template<>
P9MsgHeader htop9 (P9MsgHeader v)
 
static int dumpDmesgEntry (const uint8_t *base, const uint8_t *end, const ByteOrder bo, std::ostream &os)
 
 GEM5_DEPRECATED_NAMESPACE (Prefetcher, prefetch)
 
 GEM5_DEPRECATED_NAMESPACE (Compressor, compression)
 
static void replaceUpgrade (PacketPtr pkt)
 
 GEM5_DEPRECATED_NAMESPACE (ReplacementPolicy, replacement_policy)
 
void printSize (std::ostream &stream, size_t size)
 
std::string htmFailureToStr (HtmFailureFaultCause cause)
 Convert enum into string to be used for debug purposes. More...
 
std::string htmFailureToStr (HtmCacheFailure rc)
 Convert enum into string to be used for debug purposes. More...
 
 GEM5_DEPRECATED_NAMESPACE (ContextSwitchTaskId, context_switch_task_id)
 Special TaskIds that are used for per-context-switch stats dumps and Cache Occupancy. More...
 
static void init_drain (py::module_ &m_native)
 
static void init_serialize (py::module_ &m_native)
 
static void init_range (py::module_ &m_native)
 
static void init_net (py::module_ &m_native)
 
static void init_loader (py::module_ &m_native)
 
void pybind_init_core (py::module_ &m_native)
 
static void output (const char *filename)
 
static void ignore (const char *expr)
 
void pybind_init_debug (py::module_ &m_native)
 
void pybind_init_event (py::module_ &m_native)
 
void pybind_init_core (pybind11::module_ &m_native)
 
void pybind_init_debug (pybind11::module_ &m_native)
 
void pybind_init_event (pybind11::module_ &m_native)
 
void pybind_init_stats (pybind11::module_ &m_native)
 
static const py::object cast_stat_info (const statistics::Info *info)
 
void pybind_init_stats (py::module_ &m_native)
 
void print_backtrace ()
 Print a gem5 post-mortem report. More...
 
uint64_t swap_byte64 (uint64_t x)
 
uint32_t swap_byte32 (uint32_t x)
 
uint16_t swap_byte16 (uint16_t x)
 
template<typename T >
std::enable_if_t< sizeof(T)==8 &&std::is_convertible< T, uint64_t >::value, T > swap_byte (T x)
 
template<typename T >
std::enable_if_t< sizeof(T)==4 &&std::is_convertible< T, uint32_t >::value, T > swap_byte (T x)
 
template<typename T >
std::enable_if_t< sizeof(T)==2 &&std::is_convertible< T, uint16_t >::value, T > swap_byte (T x)
 
template<typename T >
std::enable_if_t< sizeof(T)==1 &&std::is_convertible< T, uint8_t >::value, T > swap_byte (T x)
 
template<typename T , size_t N>
std::array< T, N > swap_byte (std::array< T, N > a)
 
template<typename T >
betole (T value)
 
template<typename T >
letobe (T value)
 
template<typename T >
htole (T value)
 
template<typename T >
letoh (T value)
 
template<typename T >
htobe (T value)
 
template<typename T >
betoh (T value)
 
template<typename T >
htog (T value, ByteOrder guest_byte_order)
 
template<typename T >
gtoh (T value, ByteOrder guest_byte_order)
 
void fixClockFrequency ()
 
bool clockFrequencyFixed ()
 
void setClockFrequency (Tick tps)
 
Tick getClockFrequency ()
 
void setOutputDir (const std::string &dir)
 
CallbackQueueexitCallbacks ()
 Queue of C++ callbacks to invoke on simulator exit. More...
 
void registerExitCallback (const std::function< void()> &callback)
 Register an exit callback. More...
 
void doExitCleanup ()
 Do C++ simulator exit processing. More...
 
Tick curTick ()
 The universal simulation clock. More...
 
void cxxConfigInit ()
 Initialise cxx_config_directory. More...
 
static std::string formatParamList (const std::vector< std::string > &param_values)
 
void schedBreak (Tick when)
 Cause the simulator to execute a breakpoint. More...
 
void schedRelBreak (Tick delta)
 Cause the simulator to execute a breakpoint relative to the current tick. More...
 
void takeCheckpoint (Tick when)
 Function to cause the simulator to take a checkpoint from the debugger. More...
 
void eventqDump ()
 Dump all the events currently on the event queue. More...
 
int getRemoteGDBPort ()
 
void setRemoteGDBPort (int port)
 
EventQueuegetEventQueue (uint32_t index)
 Function for returning eventq queue for the provided index. More...
 
void dumpMainQueue ()
 
EventQueuecurEventQueue ()
 
void curEventQueue (EventQueue *q)
 
bool operator< (const Event &l, const Event &r)
 
bool operator> (const Event &l, const Event &r)
 
bool operator<= (const Event &l, const Event &r)
 
bool operator>= (const Event &l, const Event &r)
 
bool operator== (const Event &l, const Event &r)
 
bool operator!= (const Event &l, const Event &r)
 
template<typename ABI , bool store_ret, typename Ret , typename ... Args>
Ret invokeSimcall (ThreadContext *tc, std::function< Ret(ThreadContext *, Args...)> target)
 
template<typename ABI , typename Ret , typename ... Args>
Ret invokeSimcall (ThreadContext *tc, std::function< Ret(ThreadContext *, Args...)> target)
 
template<typename ABI , bool store_ret, typename Ret , typename ... Args>
Ret invokeSimcall (ThreadContext *tc, Ret(*target)(ThreadContext *, Args...))
 
template<typename ABI , typename Ret , typename ... Args>
Ret invokeSimcall (ThreadContext *tc, Ret(*target)(ThreadContext *, Args...))
 
template<typename ABI , typename ... Args>
void invokeSimcall (ThreadContext *tc, std::function< void(ThreadContext *, Args...)> target)
 
template<typename ABI , typename ... Args>
void invokeSimcall (ThreadContext *tc, void(*target)(ThreadContext *, Args...))
 
template<typename ABI , typename Ret , typename ... Args>
std::string dumpSimcall (std::string name, ThreadContext *tc, std::function< Ret(ThreadContext *, Args...)> target=std::function< Ret(ThreadContext *, Args...)>())
 
template<typename ABI , typename Ret , typename ... Args>
std::string dumpSimcall (std::string name, ThreadContext *tc, Ret(*target)(ThreadContext *, Args...))
 
void registerNativeModules ()
 
int m5Main (int argc, char **_argv)
 
static bool setupAltStack ()
 
static void installSignalHandler (int signal, void(*handler)(int sigtype), int flags=SA_RESTART)
 
static void raiseFatalSignal (int signo)
 
void dumpStatsHandler (int sigtype)
 Stats signal handler. More...
 
void dumprstStatsHandler (int sigtype)
 
void exitNowHandler (int sigtype)
 Exit signal handler. More...
 
void abortHandler (int sigtype)
 Abort signal handler. More...
 
static void segvHandler (int sigtype)
 Segmentation fault signal handler. More...
 
static void ioHandler (int sigtype)
 
void initSignals ()
 
static std::ostream & operator<< (std::ostream &os, const Port &port)
 
 GEM5_DEPRECATED_NAMESPACE (ProbePoints, probing)
 Name space containing shared probe point declarations. More...
 
static std::string normalize (const std::string &directory)
 
template<class AddrType >
void copyStringArray (std::vector< std::string > &strings, AddrType array_ptr, AddrType data_ptr, const ByteOrder bo, PortProxy &memProxy)
 
template<typename T , typename Proxy , typename A >
std::enable_if_t< std::is_integral< A >::value, ConstProxyPtr< T, Proxy > > operator+ (A a, const ConstProxyPtr< T, Proxy > &other)
 
template<typename T , typename Proxy , typename A >
std::enable_if_t< std::is_integral< A >::value, ProxyPtr< T, Proxy > > operator+ (A a, const ProxyPtr< T, Proxy > &other)
 
template<typename T , typename Proxy >
std::ostream & operator<< (std::ostream &os, const ConstProxyPtr< T, Proxy > &vptr)
 
 GEM5_DEPRECATED_NAMESPACE (PseudoInst, pseudo_inst)
 
void py_interact ()
 
static std::string normalizePath (std::string path)
 
template<class T >
void paramOut (CheckpointOut &os, const std::string &name, const T &param)
 This function is used for writing parameters to a checkpoint. More...
 
template<class T >
bool paramInImpl (CheckpointIn &cp, const std::string &name, T &param)
 
template<class T >
bool optParamIn (CheckpointIn &cp, const std::string &name, T &param, bool do_warn=true)
 This function is used for restoring optional parameters from the checkpoint. More...
 
template<class T >
void paramIn (CheckpointIn &cp, const std::string &name, T &param)
 This function is used for restoring parameters from a checkpoint. More...
 
template<class InputIterator >
void arrayParamOut (CheckpointOut &os, const std::string &name, InputIterator start, InputIterator end)
 
template<class T >
void arrayParamOut (CheckpointOut &os, const std::string &name, const T *param, unsigned size)
 
template<class T , class InsertIterator >
void arrayParamIn (CheckpointIn &cp, const std::string &name, InsertIterator inserter, ssize_t fixed_size=-1)
 Extract values stored in the checkpoint, and assign them to the provided array container. More...
 
template<class T >
decltype(std::declval< T >().insert(std::declval< typename T::value_type >()), void()) arrayParamIn (CheckpointIn &cp, const std::string &name, T &param)
 
template<class T >
decltype(std::declval< T >().push_back(std::declval< typename T::value_type >()), void()) arrayParamIn (CheckpointIn &cp, const std::string &name, T &param)
 
template<class T >
void arrayParamIn (CheckpointIn &cp, const std::string &name, T *param, unsigned size)
 
template<class T >
void mappingParamOut (CheckpointOut &os, const char *sectionName, const char *const names[], const T *param, unsigned size)
 Serialize a mapping represented as two arrays: one containing names and the other containing values. More...
 
template<class T >
void mappingParamIn (CheckpointIn &cp, const char *sectionName, const char *const names[], T *param, unsigned size)
 Restore mappingParamOut. More...
 
void exitSimLoop (const std::string &message, int exit_code=0, Tick when=curTick(), Tick repeat=0, bool serialize=false)
 Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (curTick()). More...
 
void exitSimLoopNow (const std::string &message, int exit_code=0, Tick repeat=0, bool serialize=false)
 Schedule an event as above, but make it high priority so it runs before any normal events which are schedule at the current time. More...
 
void objParamIn (CheckpointIn &cp, const std::string &name, SimObject *&param)
 To avoid circular dependencies the unserialization of SimObjects must be implemented here. More...
 
void debug_serialize (const std::string &cpt_dir)
 
EventdoSimLoop (EventQueue *)
 forward declaration More...
 
static void thread_loop (EventQueue *queue)
 The main function for all subordinate threads (i.e., all threads other than the main thread). More...
 
GlobalSimLoopExitEventsimulate (Tick num_cycles)
 Simulate for num_cycles additional cycles. More...
 
static bool testAndClearAsyncEvent ()
 Test and clear the global async_event flag, such that each time the flag is cleared, only one thread returns true (and thus is assigned to handle the corresponding async event(s)). More...
 
SyscallReturn unimplementedFunc (SyscallDesc *desc, ThreadContext *tc)
 Handler for unimplemented syscalls that we haven't thought about. More...
 
void warnUnsupportedOS (std::string syscall_name)
 
SyscallReturn ignoreFunc (SyscallDesc *desc, ThreadContext *tc)
 Handler for unimplemented syscalls that we never intend to implement (signal handling, etc.) and should not affect the correct behavior of the program. More...
 
SyscallReturn ignoreWarnOnceFunc (SyscallDesc *desc, ThreadContext *tc)
 Like above, but only prints a warning once per syscall desc it's used with. More...
 
static void exitFutexWake (ThreadContext *tc, VPtr<> addr, uint64_t tgid)
 
static SyscallReturn exitImpl (SyscallDesc *desc, ThreadContext *tc, bool group, int status)
 
SyscallReturn exitFunc (SyscallDesc *desc, ThreadContext *tc, int status)
 Target exit() handler: terminate current context. More...
 
SyscallReturn exitGroupFunc (SyscallDesc *desc, ThreadContext *tc, int status)
 Target exit_group() handler: terminate simulation. (exit all threads) More...
 
SyscallReturn getpagesizeFunc (SyscallDesc *desc, ThreadContext *tc)
 Target getpagesize() handler. More...
 
SyscallReturn brkFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> new_brk)
 Target brk() handler: set brk address. More...
 
SyscallReturn setTidAddressFunc (SyscallDesc *desc, ThreadContext *tc, uint64_t tidPtr)
 Target set_tid_address() handler. More...
 
SyscallReturn closeFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd)
 Target close() handler. More...
 
SyscallReturn lseekFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, uint64_t offs, int whence)
 Target lseek() handler. More...
 
SyscallReturn _llseekFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, uint64_t offset_high, uint32_t offset_low, VPtr<> result_ptr, int whence)
 Target _llseek() handler. More...
 
SyscallReturn munmapFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> start, size_t length)
 Target munmap() handler. More...
 
SyscallReturn gethostnameFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> buf_ptr, int name_len)
 Target gethostname() handler. More...
 
SyscallReturn getcwdFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> buf_ptr, unsigned long size)
 Target getcwd() handler. More...
 
SyscallReturn readlinkFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr<> buf, size_t bufsiz)
 Target readlink() handler. More...
 
SyscallReturn unlinkFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname)
 Target unlink() handler. More...
 
SyscallReturn linkFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr<> new_pathname)
 Target link() handler. More...
 
SyscallReturn symlinkFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr<> new_pathname)
 Target symlink() handler. More...
 
SyscallReturn mkdirFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, mode_t mode)
 Target mkdir() handler. More...
 
SyscallReturn renameFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> oldpath, VPtr<> newpath)
 Target rename() handler. More...
 
SyscallReturn truncateFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, off_t length)
 Target truncate() handler. More...
 
SyscallReturn ftruncateFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, off_t length)
 Target ftruncate() handler. More...
 
SyscallReturn truncate64Func (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, int64_t length)
 Target truncate64() handler. More...
 
SyscallReturn ftruncate64Func (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, int64_t length)
 Target ftruncate64() handler. More...
 
SyscallReturn umaskFunc (SyscallDesc *desc, ThreadContext *tc)
 Target umask() handler. More...
 
SyscallReturn chownFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, uint32_t owner, uint32_t group)
 Target chown() handler. More...
 
SyscallReturn fchownFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, uint32_t owner, uint32_t group)
 Target fchown() handler. More...
 
SyscallReturn dupFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd)
 FIXME: The file description is not shared among file descriptors created with dup. More...
 
SyscallReturn dup2Func (SyscallDesc *desc, ThreadContext *tc, int old_tgt_fd, int new_tgt_fd)
 Target dup2() handler. More...
 
SyscallReturn fcntlFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, int cmd, guest_abi::VarArgs< int > varargs)
 Target fcntl() handler. More...
 
SyscallReturn fcntl64Func (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, int cmd)
 Target fcntl64() handler. More...
 
SyscallReturn pipePseudoFunc (SyscallDesc *desc, ThreadContext *tc)
 Pseudo Funcs - These functions use a different return convension, returning a second value in a register other than the normal return register. More...
 
SyscallReturn pipeFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> tgt_addr)
 Target pipe() handler. More...
 
SyscallReturn pipe2Func (SyscallDesc *desc, ThreadContext *tc, VPtr<> tgt_addr, int flags)
 Target pipe() handler. More...
 
SyscallReturn getpgrpFunc (SyscallDesc *desc, ThreadContext *tc)
 Target getpgrpFunc() handler. More...
 
SyscallReturn setpgidFunc (SyscallDesc *desc, ThreadContext *tc, int pid, int pgid)
 Target setpgid() handler. More...
 
SyscallReturn getpidFunc (SyscallDesc *desc, ThreadContext *tc)
 Target getpid() handler. More...
 
SyscallReturn gettidFunc (SyscallDesc *desc, ThreadContext *tc)
 Target gettid() handler. More...
 
SyscallReturn getppidFunc (SyscallDesc *desc, ThreadContext *tc)
 Target getppid() handler. More...
 
SyscallReturn getuidFunc (SyscallDesc *desc, ThreadContext *tc)
 
SyscallReturn geteuidFunc (SyscallDesc *desc, ThreadContext *tc)
 Target geteuid() handler. More...
 
SyscallReturn getgidFunc (SyscallDesc *desc, ThreadContext *tc)
 Target getgid() handler. More...
 
SyscallReturn getegidFunc (SyscallDesc *desc, ThreadContext *tc)
 Target getegid() handler. More...
 
SyscallReturn fallocateFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, int mode, off_t offset, off_t len)
 
SyscallReturn accessFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, mode_t mode)
 Target access() handler. More...
 
SyscallReturn mknodFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, mode_t mode, dev_t dev)
 Target mknod() handler. More...
 
SyscallReturn chdirFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname)
 Target chdir() handler. More...
 
SyscallReturn rmdirFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname)
 
SyscallReturn shutdownFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, int how)
 Target shutdown() handler. More...
 
SyscallReturn bindFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> buf_ptr, int addrlen)
 
SyscallReturn listenFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, int backlog)
 
SyscallReturn connectFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> buf_ptr, int addrlen)
 
SyscallReturn recvfromFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> bufrPtr, size_t bufrLen, int flags, VPtr<> addrPtr, VPtr<> addrlenPtr)
 
SyscallReturn sendtoFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> bufrPtr, size_t bufrLen, int flags, VPtr<> addrPtr, socklen_t addrLen)
 
SyscallReturn recvmsgFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> msgPtr, int flags)
 
SyscallReturn sendmsgFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> msgPtr, int flags)
 
SyscallReturn getsockoptFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, int level, int optname, VPtr<> valPtr, VPtr<> lenPtr)
 
SyscallReturn getsocknameFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> addrPtr, VPtr<> lenPtr)
 
SyscallReturn getpeernameFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> sockAddrPtr, VPtr<> addrlenPtr)
 
SyscallReturn setsockoptFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, int level, int optname, VPtr<> valPtr, socklen_t len)
 
SyscallReturn getcpuFunc (SyscallDesc *desc, ThreadContext *tc, VPtr< uint32_t > cpu, VPtr< uint32_t > node, VPtr< uint32_t > tcache)
 
template<class OS >
SyscallReturn futexFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> uaddr, int op, int val, int timeout, VPtr<> uaddr2, int val3)
 Futex system call Implemented by Daniel Sanchez Used by printf's in multi-threaded apps. More...
 
template<class T1 , class T2 >
void getElapsedTimeMicro (T1 &sec, T2 &usec)
 Helper function to convert current elapsed time to seconds and microseconds. More...
 
template<class T1 , class T2 >
void getElapsedTimeNano (T1 &sec, T2 &nsec)
 Helper function to convert current elapsed time to seconds and nanoseconds. More...
 
template<typename OS , typename TgtStatPtr , typename HostStatPtr >
void copyOutStatBuf (TgtStatPtr tgt, HostStatPtr host, bool fakeTTY=false)
 
template<typename OS , typename TgtStatPtr , typename HostStatPtr >
void copyOutStat64Buf (TgtStatPtr tgt, HostStatPtr host, bool fakeTTY=false)
 
template<class OS , typename TgtStatPtr , typename HostStatPtr >
void copyOutStatfsBuf (TgtStatPtr tgt, HostStatPtr host)
 
template<class OS >
SyscallReturn ioctlFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, unsigned req, VPtr<> addr)
 Target ioctl() handler. More...
 
template<class OS >
SyscallReturn openatFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_dirfd, VPtr<> pathname, int tgt_flags, int mode)
 Target open() handler. More...
 
template<class OS >
SyscallReturn openFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, int tgt_flags, int mode)
 Target open() handler. More...
 
template<class OS >
SyscallReturn unlinkatFunc (SyscallDesc *desc, ThreadContext *tc, int dirfd, VPtr<> pathname)
 Target unlinkat() handler. More...
 
template<class OS >
SyscallReturn faccessatFunc (SyscallDesc *desc, ThreadContext *tc, int dirfd, VPtr<> pathname, int mode)
 Target facessat() handler. More...
 
template<class OS >
SyscallReturn readlinkatFunc (SyscallDesc *desc, ThreadContext *tc, int dirfd, VPtr<> pathname, VPtr<> buf, size_t bufsiz)
 Target readlinkat() handler. More...
 
template<class OS >
SyscallReturn renameatFunc (SyscallDesc *desc, ThreadContext *tc, int olddirfd, VPtr<> oldpath, int newdirfd, VPtr<> newpath)
 Target renameat() handler. More...
 
template<class OS >
SyscallReturn sysinfoFunc (SyscallDesc *desc, ThreadContext *tc, VPtr< typename OS::tgt_sysinfo > sysinfo)
 Target sysinfo() handler. More...
 
template<class OS >
SyscallReturn chmodFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, mode_t mode)
 Target chmod() handler. More...
 
template<class OS >
SyscallReturn pollFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> fdsPtr, int nfds, int tmout)
 
template<class OS >
SyscallReturn fchmodFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, uint32_t mode)
 Target fchmod() handler. More...
 
template<class OS >
SyscallReturn mremapFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> start, uint64_t old_length, uint64_t new_length, uint64_t flags, guest_abi::VarArgs< uint64_t > varargs)
 Target mremap() handler. More...
 
template<class OS >
SyscallReturn statFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr< typename OS::tgt_stat > tgt_stat)
 Target stat() handler. More...
 
template<class OS >
SyscallReturn stat64Func (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr< typename OS::tgt_stat64 > tgt_stat)
 Target stat64() handler. More...
 
template<class OS >
SyscallReturn fstatat64Func (SyscallDesc *desc, ThreadContext *tc, int dirfd, VPtr<> pathname, VPtr< typename OS::tgt_stat64 > tgt_stat)
 Target fstatat64() handler. More...
 
template<class OS >
SyscallReturn fstat64Func (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr< typename OS::tgt_stat64 > tgt_stat)
 Target fstat64() handler. More...
 
template<class OS >
SyscallReturn lstatFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr< typename OS::tgt_stat > tgt_stat)
 Target lstat() handler. More...
 
template<class OS >
SyscallReturn lstat64Func (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr< typename OS::tgt_stat64 > tgt_stat)
 Target lstat64() handler. More...
 
template<class OS >
SyscallReturn fstatFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr< typename OS::tgt_stat > tgt_stat)
 Target fstat() handler. More...
 
template<class OS >
SyscallReturn statfsFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr< typename OS::tgt_statfs > tgt_stat)
 Target statfs() handler. More...
 
template<class OS >
SyscallReturn cloneFunc (SyscallDesc *desc, ThreadContext *tc, RegVal flags, RegVal newStack, VPtr<> ptidPtr, VPtr<> ctidPtr, VPtr<> tlsPtr)
 
template<class OS >
SyscallReturn cloneBackwardsFunc (SyscallDesc *desc, ThreadContext *tc, RegVal flags, RegVal newStack, VPtr<> ptidPtr, VPtr<> tlsPtr, VPtr<> ctidPtr)
 
template<class OS >
SyscallReturn fstatfsFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr< typename OS::tgt_statfs > tgt_stat)
 Target fstatfs() handler. More...
 
template<class OS >
SyscallReturn readvFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, uint64_t tiov_base, size_t count)
 Target readv() handler. More...
 
template<class OS >
SyscallReturn writevFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, uint64_t tiov_base, size_t count)
 Target writev() handler. More...
 
template<class OS >
SyscallReturn mmapFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> start, typename OS::size_t length, int prot, int tgt_flags, int tgt_fd, typename OS::off_t offset)
 Target mmap() handler. More...
 
template<class OS >
SyscallReturn pread64Func (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> bufPtr, int nbytes, int offset)
 
template<class OS >
SyscallReturn pwrite64Func (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> bufPtr, int nbytes, int offset)
 
template<class OS >
SyscallReturn mmap2Func (SyscallDesc *desc, ThreadContext *tc, VPtr<> start, typename OS::size_t length, int prot, int tgt_flags, int tgt_fd, typename OS::off_t offset)
 Target mmap2() handler. More...
 
template<class OS >
SyscallReturn getrlimitFunc (SyscallDesc *desc, ThreadContext *tc, unsigned resource, VPtr< typename OS::rlimit > rlp)
 Target getrlimit() handler. More...
 
template<class OS >
SyscallReturn prlimitFunc (SyscallDesc *desc, ThreadContext *tc, int pid, int resource, VPtr<> n, VPtr< typename OS::rlimit > rlp)
 
template<class OS >
SyscallReturn clock_gettimeFunc (SyscallDesc *desc, ThreadContext *tc, int clk_id, VPtr< typename OS::timespec > tp)
 Target clock_gettime() function. More...
 
template<class OS >
SyscallReturn clock_getresFunc (SyscallDesc *desc, ThreadContext *tc, int clk_id, VPtr< typename OS::timespec > tp)
 Target clock_getres() function. More...
 
template<class OS >
SyscallReturn gettimeofdayFunc (SyscallDesc *desc, ThreadContext *tc, VPtr< typename OS::timeval > tp, VPtr<> tz_ptr)
 Target gettimeofday() handler. More...
 
template<class OS >
SyscallReturn utimesFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr< typename OS::timeval[2]> tp)
 Target utimes() handler. More...
 
template<class OS >
SyscallReturn execveFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> pathname, VPtr<> argv_mem_loc, VPtr<> envp_mem_loc)
 
template<class OS >
SyscallReturn getrusageFunc (SyscallDesc *desc, ThreadContext *tc, int who, VPtr< typename OS::rusage > rup)
 Target getrusage() function. More...
 
template<class OS >
SyscallReturn timesFunc (SyscallDesc *desc, ThreadContext *tc, VPtr< typename OS::tms > bufp)
 Target times() function. More...
 
template<class OS >
SyscallReturn timeFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> taddr)
 Target time() function. More...
 
template<class OS >
SyscallReturn tgkillFunc (SyscallDesc *desc, ThreadContext *tc, int tgid, int tid, int sig)
 
template<class OS >
SyscallReturn socketFunc (SyscallDesc *desc, ThreadContext *tc, int domain, int type, int prot)
 
template<class OS >
SyscallReturn socketpairFunc (SyscallDesc *desc, ThreadContext *tc, int domain, int type, int prot, VPtr<> svPtr)
 
template<class OS >
SyscallReturn selectFunc (SyscallDesc *desc, ThreadContext *tc, int nfds, VPtr< typename OS::fd_set > readfds, VPtr< typename OS::fd_set > writefds, VPtr< typename OS::fd_set > errorfds, VPtr< typename OS::timeval > timeout)
 
template<class OS >
SyscallReturn readFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> buf_ptr, int nbytes)
 
template<class OS >
SyscallReturn writeFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> buf_ptr, int nbytes)
 
template<class OS >
SyscallReturn wait4Func (SyscallDesc *desc, ThreadContext *tc, pid_t pid, VPtr<> statPtr, int options, VPtr<> rusagePtr)
 
template<class OS >
SyscallReturn acceptFunc (SyscallDesc *desc, ThreadContext *tc, int tgt_fd, VPtr<> addrPtr, VPtr<> lenPtr)
 
template<class OS >
SyscallReturn eventfdFunc (SyscallDesc *desc, ThreadContext *tc, unsigned initval, int in_flags)
 Target eventfd() function. More...
 
template<class OS >
SyscallReturn schedGetaffinityFunc (SyscallDesc *desc, ThreadContext *tc, pid_t pid, size_t cpusetsize, VPtr<> cpu_set_mask)
 Target sched_getaffinity. More...
 
void printSystems ()
 

Variables

const typedef char * FaultName
 
static const int ROW_SIZE = 16
 
static const int NUM_BANKS = 4
 
static const int ROW_SIZE = 16
 
static const int NUM_BANKS = 4
 
static uint64_t invariant_reg_vector []
 
constexpr static unsigned NUM_XREGS = NUM_ARCH_INTREGS - 1
 
constexpr static unsigned NUM_QREGS = NumVecV8ArchRegs
 
constexpr unsigned MaxVecRegLenInBytes = 4096
 
const uint8_t reverseBitsLookUpTable []
 Lookup table used for High Speed bit reversing. More...
 
volatile int stop = false
 
const char * compileDate = __DATE__ " " __TIME__
 
static const int roundOps []
 
thread_local GTestLogOutput gtestLogOutput
 
 c2 = 31
 
 high = AB + c2
 
const uint8_t image_file []
 This image file contains the text "This is a test image.\n" 31 times. More...
 
const uint8_t image_file_gzipped []
 This is "image_file" compressed using GZip. More...
 
OutputDirectory simout
 
PollQueue pollQueue
 
Random random_mt
 
static const char GDBStart = '$'
 
static const char GDBEnd = '#'
 
static const char GDBGoodP = '+'
 
static const char GDBBadP = '-'
 
const Tick MaxTick = 0xffffffffffffffffULL
 
static const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1)
 
const Addr MaxAddr = (Addr)-1
 
static const ElemIndex IllegalElemIndex
 ElemIndex value that indicates that the register is not a vector. More...
 
const ThreadID InvalidThreadID = (ThreadID)-1
 
const ContextID InvalidContextID = (ContextID)-1
 
const PortID InvalidPortID = (PortID)-1
 
constexpr decltype(nullptr) NoFault = nullptr
 
const char * gem5Version = "21.1.0.2"
 
int maxThreadsPerCPU = 1
 The maximum number of active threads across all cpus. More...
 
static const uint64_t MIN_HOST_CYCLES = 1000
 Minimum number of cycles that a host can spend in a KVM call (used to calculate the resolution of some timers). More...
 
StaticInstPtr nopStaticInstPtr = new NopStaticInst
 Pointer to a statically allocated generic "nop" instruction object. More...
 
const StaticInstPtr nullStaticInstPtr
 Statically allocated null StaticInstPtr. More...
 
static const OpClass IntAluOp = enums::IntAlu
 
static const OpClass IntMultOp = enums::IntMult
 
static const OpClass IntDivOp = enums::IntDiv
 
static const OpClass FloatAddOp = enums::FloatAdd
 
static const OpClass FloatCmpOp = enums::FloatCmp
 
static const OpClass FloatCvtOp = enums::FloatCvt
 
static const OpClass FloatMultOp = enums::FloatMult
 
static const OpClass FloatMultAccOp = enums::FloatMultAcc
 
static const OpClass FloatDivOp = enums::FloatDiv
 
static const OpClass FloatMiscOp = enums::FloatMisc
 
static const OpClass FloatSqrtOp = enums::FloatSqrt
 
static const OpClass SimdAddOp = enums::SimdAdd
 
static const OpClass SimdAddAccOp = enums::SimdAddAcc
 
static const OpClass SimdAluOp = enums::SimdAlu
 
static const OpClass SimdCmpOp = enums::SimdCmp
 
static const OpClass SimdCvtOp = enums::SimdCvt
 
static const OpClass SimdMiscOp = enums::SimdMisc
 
static const OpClass SimdMultOp = enums::SimdMult
 
static const OpClass SimdMultAccOp = enums::SimdMultAcc
 
static const OpClass SimdShiftOp = enums::SimdShift
 
static const OpClass SimdShiftAccOp = enums::SimdShiftAcc
 
static const OpClass SimdDivOp = enums::SimdDiv
 
static const OpClass SimdSqrtOp = enums::SimdSqrt
 
static const OpClass SimdReduceAddOp = enums::SimdReduceAdd
 
static const OpClass SimdReduceAluOp = enums::SimdReduceAlu
 
static const OpClass SimdReduceCmpOp = enums::SimdReduceCmp
 
static const OpClass SimdFloatAddOp = enums::SimdFloatAdd
 
static const OpClass SimdFloatAluOp = enums::SimdFloatAlu
 
static const OpClass SimdFloatCmpOp = enums::SimdFloatCmp
 
static const OpClass SimdFloatCvtOp = enums::SimdFloatCvt
 
static const OpClass SimdFloatDivOp = enums::SimdFloatDiv
 
static const OpClass SimdFloatMiscOp = enums::SimdFloatMisc
 
static const OpClass SimdFloatMultOp = enums::SimdFloatMult
 
static const OpClass SimdFloatMultAccOp = enums::SimdFloatMultAcc
 
static const OpClass SimdFloatSqrtOp = enums::SimdFloatSqrt
 
static const OpClass SimdFloatReduceCmpOp = enums::SimdFloatReduceCmp
 
static const OpClass SimdFloatReduceAddOp = enums::SimdFloatReduceAdd
 
static const OpClass SimdAesOp = enums::SimdAes
 
static const OpClass SimdAesMixOp = enums::SimdAesMix
 
static const OpClass SimdSha1HashOp = enums::SimdSha1Hash
 
static const OpClass SimdSha1Hash2Op = enums::SimdSha1Hash2
 
static const OpClass SimdSha256HashOp = enums::SimdSha256Hash
 
static const OpClass SimdSha256Hash2Op = enums::SimdSha256Hash2
 
static const OpClass SimdShaSigma2Op = enums::SimdShaSigma2
 
static const OpClass SimdShaSigma3Op = enums::SimdShaSigma3
 
static const OpClass SimdPredAluOp = enums::SimdPredAlu
 
static const OpClass MemReadOp = enums::MemRead
 
static const OpClass MemWriteOp = enums::MemWrite
 
static const OpClass FloatMemReadOp = enums::FloatMemRead
 
static const OpClass FloatMemWriteOp = enums::FloatMemWrite
 
static const OpClass IprAccessOp = enums::IprAccess
 
static const OpClass InstPrefetchOp = enums::InstPrefetch
 
static const OpClass Num_OpClasses = enums::Num_OpClass
 
int TESTER_NETWORK =0
 
static unsigned int TESTER_ALLOCATOR = 0
 
const int CHECK_SIZE_BITS = 2
 
const int CHECK_SIZE = (1 << CHECK_SIZE_BITS)
 
static EmbeddedPyBind _py_tracers ("trace", pybind_init_tracers)
 
constexpr int FRAMEBUFFER_BAR = 0
 
constexpr int DOORBELL_BAR = 2
 
constexpr int MMIO_BAR = 5
 
constexpr uint32_t VGA_ROM_DEFAULT = 0xc0000
 
constexpr uint32_t ROM_SIZE = 0x20000
 
const uint64_t AmbaVendor = 0xb105f00d00000000ULL
 
static const std::map< enums::NoMaliGpuType, nomali_gpu_type_t > gpuTypeMap
 
const char * NsRxStateStrings []
 
const char * NsTxStateStrings []
 
const char * NsDmaState []
 
const uint16_t FHASH_ADDR = 0x100
 
const uint16_t FHASH_SIZE = 0x100
 
const uint8_t EEPROM_READ = 0x2
 
const uint8_t EEPROM_SIZE = 64
 
const uint8_t EEPROM_PMATCH2_ADDR = 0xA
 
const uint8_t EEPROM_PMATCH1_ADDR = 0xB
 
const uint8_t EEPROM_PMATCH0_ADDR = 0xC
 
const int RX_INT = 0x1
 
const int TX_INT = 0x2
 
const uint8_t UART_MCR_LOOP = 0x10
 
const int MaxNiagaraProcs = 32
 
const Addr IntManAddr = 0x0000
 
const Addr IntManSize = 0x0020
 
const Addr IntCtlAddr = 0x0400
 
const Addr IntCtlSize = 0x0020
 
const Addr JIntVecAddr = 0x0A00
 
const Addr IntVecDisAddr = 0x0800
 
const Addr IntVecDisSize = 0x0100
 
const Addr JIntData0Addr = 0x0400
 
const Addr JIntData1Addr = 0x0500
 
const Addr JIntDataA0Addr = 0x0600
 
const Addr JIntDataA1Addr = 0x0700
 
const Addr JIntBusyAddr = 0x0900
 
const Addr JIntBusySize = 0x0100
 
const Addr JIntABusyAddr = 0x0B00
 
const uint64_t IntManMask = 0x01F3F
 
const uint64_t IntCtlMask = 0x00006
 
const uint64_t JIntVecMask = 0x0003F
 
const uint64_t IntVecDis = 0x31F3F
 
const uint64_t JIntBusyMask = 0x0003F
 
static const P9MsgInfoMap p9_msg_info
 
const uint8_t RamSize = 32
 
const uint8_t NumOutputBits = 14
 
static const int LDS_SIZE = 65536
 
PybindSimObjectResolver pybindSimObjectResolver
 
const bool flag_DEBUG = false
 
const bool flag_NDEBUG = false
 
const bool flag_TRACING_ON = TRACING_ON
 
const ByteOrder HostByteOrder = ByteOrder::big
 
std::map< std::string, CxxConfigDirectoryEntry * > cxx_config_directory
 Directory of all SimObject classes config details. More...
 
int remote_gdb_base_port = 7000
 
Tick simQuantum = 0
 Simulation Quantum for multiple eventq simulation. More...
 
uint32_t numMainEventQueues = 0
 Current number of allocated main event queues. More...
 
std::vector< EventQueue * > mainEventQueue
 Array for main event queues. More...
 
__thread EventQueue_curEventQueue = NULL
 The current event queue for the running thread. More...
 
bool inParallelMode = false
 Current mode of execution: parallel / serial. More...
 
bool FullSystem
 The FullSystem variable can be used to determine the current mode of simulation. More...
 
unsigned int FullSystemInt
 In addition to the boolean flag we make use of an unsigned int since the CPU instruction decoder makes use of the variable in switch statements. More...
 
std::set< std::string > version_tags
 The version tags for this build of the simulator, to be stored in the Globals section during serialization and compared upon unserialization. More...
 
const GEM5_WEAK char * m5MainCommands []
 
static uint8_t fatalSigStack [2 *SIGSTKSZ]
 
Root::RootStatsrootStats = Root::RootStats::instance
 Global simulator statistics that are not associated with a specific SimObject. More...
 
int ckptMaxCount = 0
 
int ckptCount = 0
 
int ckptPrevCount = -1
 
template<class T >
decltype(std::begin(std::declval< const T & >()), std::end(std::declval< const T & >()), void()) arrayParamOut (CheckpointOut &os, const std::string &name, const T &param)
 
std::mutex asyncEventMutex
 Mutex for handling async events. More...
 
BarrierthreadBarrier
 Global barrier for synchronizing threads entering/exiting the simulation loop. More...
 
GlobalSimLoopExitEventsimulate_limit_event = nullptr
 
statistics::FormulasimSeconds = rootStats.simSeconds
 
statistics::ValuesimTicks = rootStats.simTicks
 
statistics::ValuesimFreq = rootStats.simFreq
 
statistics::ValuehostSeconds = rootStats.hostSeconds
 
const char * hostname = "m5.eecs.umich.edu"
 
const unsigned seconds_since_epoch = 1000 * 1000 * 1000
 Approximate seconds since the epoch (1/1/1970). More...
 
using DummyVecElem = uint32_t
 Dummy type aliases and constants for architectures that do not implement vector registers. More...
 
using DummyVecRegContainer = VecRegContainer< DummyNumVecElemPerVecReg *sizeof(DummyVecElem)>
 
constexpr unsigned DummyNumVecElemPerVecReg = 2
 

Detailed Description

Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.

the profiler uses GPUCoalescer code even though the GPUCoalescer is not built for all ISAs, which can lead to run/link time errors.

On Linux, MAP_NORESERVE allow us to simulate a very large memory without committing to actually providing the swap space on the host.

When building the debug binary, we need to undo the command-line definition of DEBUG not to clash with DRAMsim3 print macros that are included for no obvious reason.

When building the debug binary, we need to undo the command-line definition of DEBUG not to clash with DRAMSim2 print macros that are included for no obvious reason.

Copyright (c) 2020 Inria All rights reserved.

Copyright (c) 2019, 2020 Inria All rights reserved.

Copyright (c) 2018-2020 Inria All rights reserved.

Copyright (c) 2019 Metempsy Technology Consulting All rights reserved.

Copyright (c) 2018 Metempsy Technology Consulting All rights reserved.

Note: For details on the implementation see https://wiki.osdev.org/%228042%22_PS/2_Controller.

UFS command flow state machine digraph CommandFlow{ node [fontsize=10]; IDLE -> transferHandler [ label=" transfer/task/command request " fontsize=6]; transferHandler -> command [ label=" It is a command " fontsize=6]; command -> IDLE [ label=" Command done, no further action " fontsize=6]; transferHandler -> taskStart [ label=" It is a task " fontsize=6]; taskStart -> finalUTP [ label=" Task handled, now acknowledge (UFS) " fontsize=6]; transferHandler -> transferStart [ label=" It is a transfer " fontsize=6]; transferStart -> SCSIResume [ label=" Transfer, obtain the specific command " fontsize=6]; SCSIResume -> DiskDataFlowPhase [ label=" Disk data transfer (see other graphs) " fontsize=6]; SCSIResume -> DeviceDataPhase [ label=" Device info transfer (handled in SCSIResume) " fontsize=6]; DiskDataFlowPhase -> transferDone [ label=" Transfer done, acknowledge SCSI command " fontsize=6]; DeviceDataPhase -> transferDone [ label=" Transfer done, acknowledge SCSI command " fontsize=6]; transferDone -> finalUTP [ label=" Transfer handled, now acknowledge (UFS) " fontsize=6]; finalUTP -> readDone [ label=" All handled, clear data structures " fontsize=6]; readDone -> IDLE [ label=" All handled, nothing outstanding " fontsize=6]; readDone -> transferHandler [ label=" All handled, handle next outstanding " fontsize=6]; }.

Todo:

Generalized N-dimensinal vector documentation key stats interval stats – these both can use the same function that prints out a specific set of stats VectorStandardDeviation totals Document Namespaces

UFS read transaction flow state machine digraph readFlow{ node [fontsize=10]; getScatterGather -> commitReadFromDisk [ label=" Put the information about the data transfer to the disk " fontsize=6]; commitReadFromDisk -> waitForReads [ label=" Push the reads to the flashmodel and wait for callbacks " fontsize=6]; waitForReads -> pushToDMA [ label=" Push to the DMA and wait for them to finish " fontsize=6]; pushToDMA -> waitForReads [ label=" Wait for the next disk event " fontsize=6]; pushToDMA -> waitForDMA [ label=" Wait for the last DMA transfer to finish " fontsize=6]; waitForDMA -> finishTransfer [ label=" Continue with the command flow " fontsize=6]; } UFS write transaction flow state machine digraph WriteFlow{ node [fontsize=10]; getScatterGather -> getFromDMA [ label=" Put the transfer information to the DMA " fontsize=6]; getFromDMA -> waitForDMA [ label=" Wait for dma actions to arrive " fontsize=6]; waitForDMA -> pushToDisk [ label=" Push arrived DMA to disk " fontsize=6]; pushToDisk -> waitForDMA [ label=" Wait for next DMA action " fontsize=6]; pushToDisk -> waitForDisk [ label=" All DMA actions are done, wait for disk " fontsize=6]; waitForDisk -> finishTransfer [ label=" All transactions are done , continue the command flow " fontsize=6]; }

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the Access Map Pattern Matching Prefetcher

References: Access map pattern matching for high performance data cache prefetch. Ishii, Y., Inaba, M., & Hiraki, K. (2011). Journal of Instruction-Level Parallelism, 13, 1-24.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the 'A Best-Offset Prefetcher' Reference: Michaud, P. (2015, June). A best-offset prefetcher. In 2nd Data Prefetching Championship.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the Indirect Memory Prefetcher

References: IMP: Indirect memory prefetcher. Yu, X., Hughes, C. J., Satish, N., & Devadas, S. (2015, December). In Proceedings of the 48th International Symposium on Microarchitecture (pp. 178-190). ACM.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the Irregular Stream Buffer prefetcher Reference: Jain, A., & Lin, C. (2013, December). Linearizing irregular memory accesses for improved correlated prefetching. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 247-259). ACM.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the 'Proactive Instruction Fetch' prefetcher Reference: Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December). Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 152-162). ACM.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the 'Sandbox Based Optimal Offset Estimation' Reference: Brown, N. T., & Sendag, R. Sandbox Based Optimal Offset Estimation.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the Signature Path Prefetcher

References: Lookahead prefetching with signature path J Kim, PV Gratz, ALN Reddy The 2nd Data Prefetching Championship (DPC2) The filter feature described in the paper is not implemented, as it redundant prefetches are dropped by the cache.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the Signature Path Prefetcher (v2)

References: Path confidence based lookahead prefetching Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy, Chris Wilkerson, and Zeshan Chishti. 2016. In The 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-49). IEEE Press, Piscataway, NJ, USA, Article 60, 12 pages.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. The SlimAMPM Prefetcher Reference: Towards Bandwidth-Efficient Prefetching with Slim AMPM. Young, Vinson, and A. Krishna. The 2nd Data Prefetching Championship (2015).

This prefetcher uses two other prefetchers, the AMPM and the DCPT.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer; redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution; neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Implementation of the Spatio-Temporal Memory Streaming Prefetcher (STeMS) Reference: Spatio-temporal memory streaming. Somogyi, S., Wenisch, T. F., Ailamaki, A., & Falsafi, B. (2009). ACM SIGARCH Computer Architecture News, 37(3), 69-80.

Notes:

eventually we should use probe points here, but until then these ifdefs will serve.

Typedef Documentation

◆ _amd_queue_properties32_t

Definition at line 64 of file hsa_queue.hh.

◆ Addr

typedef uint64_t gem5::Addr

Address type This will probably be moved somewhere else in the near future.

This should be at least as big as the biggest address width in use in the system, which will probably be 64 bits.

Definition at line 147 of file types.hh.

◆ amd_signal_kind64_t

typedef int64_t gem5::amd_signal_kind64_t

Definition at line 42 of file hsa_signal.hh.

◆ amd_signal_t

◆ ArchPageTable

Definition at line 81 of file process.cc.

◆ BaseHTMCheckpointPtr

Definition at line 125 of file htm.hh.

◆ BasicBlockRange

Probe for SimPoints BBV generation.

Start and end address of basic block for SimPoint profiling. This structure is used to look up the hash table of BBVs.

  • first: PC of first inst in basic block
  • second: PC of last inst in basic block

Definition at line 61 of file simpoint.hh.

◆ CachesMask

typedef uint32_t gem5::CachesMask

Definition at line 73 of file fa_lru.hh.

◆ CheckpointOut

typedef std::ostream gem5::CheckpointOut

Definition at line 66 of file serialize.hh.

◆ ConstVPtr

template<typename T >
using gem5::ConstVPtr = typedef ConstProxyPtr<T, SETranslatingPortProxy>

Definition at line 399 of file proxy_ptr.hh.

◆ ContextID

typedef int gem5::ContextID

Globally unique thread context ID.

Definition at line 246 of file types.hh.

◆ Counter

typedef int64_t gem5::Counter

Statistics counter type.

All counters are of 64-bit values.

Not much excuse for not using a 64-bit integer here, but if you're desperate and only run short simulations you could make this 32 bits.

Definition at line 53 of file types.hh.

◆ DummyVecElem

using gem5::DummyVecElem = typedef uint32_t

Dummy type aliases and constants for architectures that do not implement vector registers.

Definition at line 266 of file vec_reg.hh.

◆ DummyVecPredRegContainer

Dummy type aliases and constants for architectures that do not implement vector predicate registers.

Definition at line 395 of file vec_pred_reg.hh.

◆ DummyVecRegContainer

Definition at line 269 of file vec_reg.hh.

◆ ElemIndex

using gem5::ElemIndex = typedef uint16_t

Logical vector register elem index type.

Definition at line 179 of file types.hh.

◆ EthPacketPtr

typedef std::shared_ptr<EthPacketData> gem5::EthPacketPtr

Definition at line 90 of file etherpkt.hh.

◆ Fault

typedef std::shared_ptr<FaultBase> gem5::Fault

Definition at line 255 of file types.hh.

◆ FaultStat

Definition at line 56 of file faults.hh.

◆ FUDDiterator

typedef std::vector<FUDesc *>::const_iterator gem5::FUDDiterator

Definition at line 91 of file func_unit.hh.

◆ GPUDynInstPtr

typedef std::shared_ptr<GPUDynInst> gem5::GPUDynInstPtr

Definition at line 51 of file misc.hh.

◆ hst_stat

typedef struct stat gem5::hst_stat

Definition at line 556 of file syscall_emul.hh.

◆ hst_stat64

typedef struct stat64 gem5::hst_stat64

Definition at line 557 of file syscall_emul.hh.

◆ hst_statfs

typedef struct statfs gem5::hst_statfs

Definition at line 551 of file syscall_emul.hh.

◆ InstSeqNum

typedef uint64_t gem5::InstSeqNum

Definition at line 40 of file inst_seq.hh.

◆ InstTag

typedef unsigned int gem5::InstTag

Definition at line 43 of file inst_seq.hh.

◆ MemBackdoorPtr

Definition at line 127 of file backdoor.hh.

◆ MicroPC

typedef uint16_t gem5::MicroPC

Definition at line 149 of file types.hh.

◆ namespace

using gem5::namespace = typedef gem5::auxv::AuxVector<IntType>

Definition at line 136 of file aux_vector.hh.

◆ OPDDiterator

typedef std::vector<OpDesc *>::const_iterator gem5::OPDDiterator

Definition at line 90 of file func_unit.hh.

◆ P9MsgInfoMap

Definition at line 76 of file fs9p.cc.

◆ P9MsgType

typedef uint8_t gem5::P9MsgType

Definition at line 52 of file fs9p.hh.

◆ P9Tag

typedef uint16_t gem5::P9Tag

Definition at line 55 of file fs9p.hh.

◆ PacketDataPtr

typedef uint8_t* gem5::PacketDataPtr

Definition at line 71 of file packet.hh.

◆ PacketId

typedef uint64_t gem5::PacketId

Definition at line 73 of file packet.hh.

◆ PacketList

Definition at line 72 of file packet.hh.

◆ PacketPtr

Definition at line 75 of file thread_context.hh.

◆ PhysRegIdPtr

using gem5::PhysRegIdPtr = typedef PhysRegId*

Definition at line 308 of file reg_class.hh.

◆ PortID

typedef int16_t gem5::PortID

Port index/ID type, and a symbolic name for an invalid port id.

Definition at line 252 of file types.hh.

◆ RegIndex

using gem5::RegIndex = typedef uint16_t

Definition at line 176 of file types.hh.

◆ RegisterBankBE

using gem5::RegisterBankBE = typedef RegisterBank<ByteOrder::big>

Definition at line 942 of file reg_bank.hh.

◆ RegisterBankLE

using gem5::RegisterBankLE = typedef RegisterBank<ByteOrder::little>

Definition at line 941 of file reg_bank.hh.

◆ RegVal

using gem5::RegVal = typedef uint64_t

Definition at line 173 of file types.hh.

◆ ReplacementCandidates

Replacement candidates as chosen by the indexing policy.

Definition at line 46 of file base.hh.

◆ RequestorID

typedef uint16_t gem5::RequestorID

Definition at line 95 of file request.hh.

◆ RequestPtr

typedef std::shared_ptr<Request> gem5::RequestPtr

Definition at line 92 of file request.hh.

◆ SatCounter

Definition at line 344 of file sat_counter.hh.

◆ SenderState

Definition at line 40 of file Check.cc.

◆ StaticInstPtr

Definition at line 37 of file static_inst_fwd.hh.

◆ ThreadID

typedef int16_t gem5::ThreadID

Thread index/ID type.

Definition at line 242 of file types.hh.

◆ Tick

typedef uint64_t gem5::Tick

Tick count type.

Definition at line 58 of file types.hh.

◆ TlbEntryTrie

Definition at line 61 of file pagetable.hh.

◆ VectorMask

typedef std::bitset<std::numeric_limits<unsigned long long>::digits> gem5::VectorMask

Definition at line 47 of file misc.hh.

◆ VPtr

template<typename T = void>
using gem5::VPtr = typedef ProxyPtr<T, SETranslatingPortProxy>

Definition at line 401 of file proxy_ptr.hh.

◆ WaiterList

Definition at line 104 of file futex_map.hh.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
CoreTag 
MemTag 
RevTag 
SerialTag 
CmdTag 
NoneTag 

Definition at line 49 of file atag.hh.

◆ anonymous enum

anonymous enum
Enumerator
SMMU_CACHE_REPL_ROUND_ROBIN 
SMMU_CACHE_REPL_RANDOM 
SMMU_CACHE_REPL_LRU 

Definition at line 57 of file smmu_v3_caches.hh.

◆ anonymous enum

anonymous enum
Enumerator
SMMU_SECURE_SZ 
SMMU_PAGE_ZERO_SZ 
SMMU_PAGE_ONE_SZ 
SMMU_REG_SIZE 

Definition at line 48 of file smmu_v3_defs.hh.

◆ anonymous enum

anonymous enum
Enumerator
STE_CONFIG_ABORT 
STE_CONFIG_BYPASS 
STE_CONFIG_STAGE1_ONLY 
STE_CONFIG_STAGE2_ONLY 
STE_CONFIG_STAGE1_AND_2 

Definition at line 56 of file smmu_v3_defs.hh.

◆ anonymous enum

anonymous enum
Enumerator
STAGE1_CFG_1L 
STAGE1_CFG_2L_4K 
STAGE1_CFG_2L_64K 

Definition at line 65 of file smmu_v3_defs.hh.

◆ anonymous enum

anonymous enum
Enumerator
ST_CFG_SPLIT_SHIFT 
ST_CD_ADDR_SHIFT 
CD_TTB_SHIFT 
STE_S2TTB_SHIFT 

Definition at line 72 of file smmu_v3_defs.hh.

◆ anonymous enum

anonymous enum
Enumerator
TRANS_GRANULE_4K 
TRANS_GRANULE_64K 
TRANS_GRANULE_16K 
TRANS_GRANULE_INVALID 

Definition at line 80 of file smmu_v3_defs.hh.

◆ anonymous enum

anonymous enum
Enumerator
ST_BASE_ADDR_MASK 
ST_CFG_SIZE_MASK 
ST_CFG_SPLIT_MASK 
ST_CFG_FMT_MASK 
ST_CFG_FMT_LINEAR 
ST_CFG_FMT_2LEVEL 
ST_L2_SPAN_MASK 
ST_L2_ADDR_MASK 
VMT_BASE_ADDR_MASK 
VMT_BASE_SIZE_MASK 
Q_BASE_ADDR_MASK 
Q_BASE_SIZE_MASK 
E_BASE_ENABLE_MASK 
E_BASE_ADDR_MASK 

Definition at line 88 of file smmu_v3_defs.hh.

◆ anonymous enum

anonymous enum
Enumerator
CR0_SMMUEN_MASK 
CR0_PRIQEN_MASK 
CR0_EVENTQEN_MASK 
CR0_CMDQEN_MASK 
CR0_ATSCHK_MASK 
CR0_VMW_MASK 

Definition at line 321 of file smmu_v3_defs.hh.

◆ anonymous enum

anonymous enum
Enumerator
SMMU_MAX_TRANS_ID 

Definition at line 408 of file smmu_v3_defs.hh.

◆ _hsa_queue_type_t

Enumerator
_HSA_QUEUE_TYPE_MULTI 
_HSA_QUEUE_TYPE_SINGLE 

Definition at line 42 of file hsa_queue.hh.

◆ amd_signal_kind_t

Enumerator
AMD_SIGNAL_KIND_INVALID 
AMD_SIGNAL_KIND_USER 
AMD_SIGNAL_KIND_DOORBELL 
AMD_SIGNAL_KIND_LEGACY_DOORBELL 

Definition at line 43 of file hsa_signal.hh.

◆ AuxiliaryVectorType

Enumerator
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATED_ENUM_VAL 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 
GEM5_DEPRECATE_AT 

Definition at line 101 of file aux_vector.hh.

◆ BlockMemoryHop

Enumerator
BlockSend 
BlockRecv 

Definition at line 63 of file misc.hh.

◆ BMIRegOffset

Enumerator
BMICommand 
BMIStatus 
BMIDescTablePtr 

Definition at line 61 of file ide_ctrl.cc.

◆ ChipCommandRegister

Enumerator
CR_TXE 
CR_TXD 
CR_RXE 
CR_RXD 
CR_TXR 
CR_RXR 
CR_SWI 
CR_RST 

Definition at line 85 of file ns_gige_reg.h.

◆ ClockrunControlStatusRegister

Enumerator
CCSR_CLKRUN_EN 

Definition at line 335 of file ns_gige_reg.h.

◆ CMDSTSFlatsForDescriptors

Enumerator
CMDSTS_OWN 
CMDSTS_MORE 
CMDSTS_INTR 
CMDSTS_ERR 
CMDSTS_OK 
CMDSTS_LEN_MASK 
CMDSTS_DEST_MASK 
CMDSTS_DEST_SELF 
CMDSTS_DEST_MULTI 

Definition at line 394 of file ns_gige_reg.h.

◆ ConfigurationRegisters

Enumerator
CFGR_ZERO 
CFGR_LNKSTS 
CFGR_SPDSTS 
CFGR_SPDSTS1 
CFGR_SPDSTS0 
CFGR_DUPSTS 
CFGR_TBI_EN 
CFGR_RESERVED 
CFGR_MODE_1000 
CFGR_AUTO_1000 
CFGR_PINT_CTL 
CFGR_PINT_DUPSTS 
CFGR_PINT_LNKSTS 
CFGR_PINT_SPDSTS 
CFGR_TMRTEST 
CFGR_MRM_DIS 
CFGR_MWI_DIS 
CFGR_T64ADDR 
CFGR_PCI64_DET 
CFGR_DATA64_EN 
CFGR_M64ADDR 
CFGR_PHY_RST 
CFGR_PHY_DIS 
CFGR_EXTSTS_EN 
CFGR_REQALG 
CFGR_SB 
CFGR_POW 
CFGR_EXD 
CFGR_PESEL 
CFGR_BROM_DIS 
CFGR_EXT_125 
CFGR_BEM 

Definition at line 98 of file ns_gige_reg.h.

◆ DevAction_t

Enumerator
ACT_NONE 
ACT_CMD_WRITE 
ACT_CMD_COMPLETE 
ACT_CMD_ERROR 
ACT_SELECT_WRITE 
ACT_STAT_READ 
ACT_DATA_READY 
ACT_DATA_READ_BYTE 
ACT_DATA_READ_SHORT 
ACT_DATA_WRITE_BYTE 
ACT_DATA_WRITE_SHORT 
ACT_DMA_READY 
ACT_DMA_DONE 
ACT_SRST_SET 
ACT_SRST_CLEAR 

Definition at line 156 of file ide_disk.hh.

◆ DeviceRegisterAddress

Enumerator
CR 
CFGR 
MEAR 
PTSCR 
ISR 
IMR 
IER 
IHR 
TXDP 
TXDP_HI 
TX_CFG 
GPIOR 
RXDP 
RXDP_HI 
RX_CFG 
PQCR 
WCSR 
PCR 
RFCR 
RFDR 
BRAR 
BRDR 
SRR 
MIBC 
MIB_START 
MIB_END 
VRCR 
VTCR 
VDR 
CCSR 
TBICR 
TBISR 
TANAR 
TANLPAR 
TANER 
TESR 
M5REG 
LAST 
RESERVED 

Definition at line 41 of file ns_gige_reg.h.

◆ DevState_t

Enumerator
Device_Idle_S 
Device_Idle_SI 
Device_Idle_NS 
Device_Srst 
Command_Execution 
Prepare_Data_In 
Data_Ready_INTRQ_In 
Transfer_Data_In 
Prepare_Data_Out 
Data_Ready_INTRQ_Out 
Transfer_Data_Out 
Prepare_Data_Dma 
Transfer_Data_Dma 
Device_Dma_Abort 

Definition at line 175 of file ide_disk.hh.

◆ DISPATCH_STATUS

Enumerator
EMPTY 
EXREADY 
SKIP 

Definition at line 61 of file exec_stage.hh.

◆ DmaState_t

Enumerator
Dma_Idle 
Dma_Start 
Dma_Transfer 

Definition at line 204 of file ide_disk.hh.

◆ EEPROMAccessRegister

Enumerator
MEAR_EEDI 
MEAR_EEDO 
MEAR_EECLK 
MEAR_EESEL 
MEAR_MDIO 
MEAR_MDDIR 
MEAR_MDC 

Definition at line 135 of file ns_gige_reg.h.

◆ Events_t

Enumerator
None 
Transfer 
ReadWait 
WriteWait 
PrdRead 
DmaRead 
DmaWrite 

Definition at line 145 of file ide_disk.hh.

◆ EXEC_POLICY

Enumerator
OLDEST 
RR 

Definition at line 74 of file compute_unit.hh.

◆ ExtendedFlagsForDescriptors

Enumerator
EXTSTS_UDPERR 
EXTSTS_UDPPKT 
EXTSTS_TCPERR 
EXTSTS_TCPPKT 
EXTSTS_IPERR 
EXTSTS_IPPKT 

Definition at line 409 of file ns_gige_reg.h.

◆ GeneralPurposeIOControlRegister

Enumerator
GPIOR_UNUSED 
GPIOR_GP5_IN 
GPIOR_GP4_IN 
GPIOR_GP3_IN 
GPIOR_GP2_IN 
GPIOR_GP1_IN 
GPIOR_GP5_OE 
GPIOR_GP4_OE 
GPIOR_GP3_OE 
GPIOR_GP2_OE 
GPIOR_GP1_OE 
GPIOR_GP5_OUT 
GPIOR_GP4_OUT 
GPIOR_GP3_OUT 
GPIOR_GP2_OUT 
GPIOR_GP1_OUT 

Definition at line 227 of file ns_gige_reg.h.

◆ HtmCacheFailure

enum gem5::HtmCacheFailure
strong
Enumerator
NO_FAIL 
FAIL_SELF 
FAIL_REMOTE 
FAIL_OTHER 

Definition at line 59 of file htm.hh.

◆ HtmFailureFaultCause

enum gem5::HtmFailureFaultCause : int
strong
Enumerator
INVALID 
EXPLICIT 
NEST 
SIZE 
EXCEPTION 
MEMORY 
OTHER 
NUM_CAUSES 

Definition at line 47 of file htm.hh.

◆ InstMemoryHop

enum gem5::InstMemoryHop : int
Enumerator
Initiate 
CoalsrSend 
CoalsrRecv 
GMEnqueue 
Complete 
InstMemoryHopMax 

Definition at line 53 of file misc.hh.

◆ InterruptStatusRegister

Enumerator
ISR_RESERVE 
ISR_TXDESC3 
ISR_TXDESC2 
ISR_TXDESC1 
ISR_TXDESC0 
ISR_RXDESC3 
ISR_RXDESC2 
ISR_RXDESC1 
ISR_RXDESC0 
ISR_TXRCMP 
ISR_RXRCMP 
ISR_DPERR 
ISR_SSERR 
ISR_RMABT 
ISR_RTAB 
ISR_RXSOVR 
ISR_HIBINT 
ISR_PHY 
ISR_PME 
ISR_SWI 
ISR_MIB 
ISR_TXURN 
ISR_TXIDLE 
ISR_TXERR 
ISR_TXDESC 
ISR_TXOK 
ISR_RXORN 
ISR_RXIDLE 
ISR_RXEARLY 
ISR_RXERR 
ISR_RXDESC 
ISR_RXOK 
ISR_ALL 
ISR_DELAY 
ISR_NODELAY 
ISR_IMPL 
ISR_NOIMPL 

Definition at line 160 of file ns_gige_reg.h.

◆ ItsActionType

enum gem5::ItsActionType
strong
Enumerator
INITIAL_NOP 
SEND_REQ 
TERMINATE 

Definition at line 62 of file gic_v3_its.hh.

◆ kfd_mmio_remap

Enumerator
KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL 
KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL 

Definition at line 511 of file kfd_ioctl.h.

◆ kfd_smi_event

Enumerator
KFD_SMI_EVENT_NONE 
KFD_SMI_EVENT_VMFAULT 
KFD_SMI_EVENT_THERMAL_THROTTLE 
KFD_SMI_EVENT_GPU_PRE_RESET 
KFD_SMI_EVENT_GPU_POST_RESET 

Definition at line 492 of file kfd_ioctl.h.

◆ M5ControlRegister

Enumerator
M5REG_RESERVED 
M5REG_RSS 
M5REG_RX_THREAD 
M5REG_TX_THREAD 

Definition at line 369 of file ns_gige_reg.h.

◆ ManagementInformationBaseControlRegister

Enumerator
MIBC_MIBS 
MIBC_ACLR 
MIBC_FRZ 
MIBC_WRN 

Definition at line 304 of file ns_gige_reg.h.

◆ PauseControlStatusRegister

Enumerator
PCR_PSEN 
PCR_PS_MCAST 
PCR_PS_DA 
PCR_STHI_8 
PCR_STLO_4 
PCR_FFHI_8K 
PCR_FFLO_4K 
PCR_PAUSE_CNT 

Definition at line 263 of file ns_gige_reg.h.

◆ PciIntPin

enum gem5::PciIntPin : uint8_t
strong
Enumerator
NO_INT 
INTA 
INTB 
INTC 
INTD 

Definition at line 66 of file types.hh.

◆ PCITestControlRegister

Enumerator
PTSCR_EEBIST_FAIL 
PTSCR_EEBIST_EN 
PTSCR_EELOAD_EN 
PTSCR_RBIST_FAIL 
PTSCR_RBIST_DONE 
PTSCR_RBIST_EN 
PTSCR_RBIST_RST 
PTSCR_RBIST_RDONLY 

Definition at line 147 of file ns_gige_reg.h.

◆ Q_STATE

Enumerator
UNBLOCKED 
BLOCKED_BBIT 
BLOCKED_BPKT 

Definition at line 61 of file hsa_packet_processor.hh.

◆ ReceiveConfigurationRegister

Enumerator
RX_CFG_AEP 
RX_CFG_ARP 
RX_CFG_STRIPCRC 
RX_CFG_RX_FD 
RX_CFG_ALP 
RX_CFG_AIRL 
RX_CFG_MXDMA512 
RX_CFG_MXDMA 
RX_CFG_DRTH 
RX_CFG_DRTH0 

Definition at line 248 of file ns_gige_reg.h.

◆ ReceiveFilterMatchControlRegister

Enumerator
RFCR_RFEN 
RFCR_AAB 
RFCR_AAM 
RFCR_AAU 
RFCR_APM 
RFCR_APAT 
RFCR_APAT3 
RFCR_APAT2 
RFCR_APAT1 
RFCR_APAT0 
RFCR_AARP 
RFCR_MHEN 
RFCR_UHEN 
RFCR_ULM 
RFCR_RFADDR 

Definition at line 276 of file ns_gige_reg.h.

◆ ReceiveFilterMatchDataRegister

Enumerator
RFDR_BMASK 
RFDR_RFDATA0 
RFDR_RFDATA1 

Definition at line 296 of file ns_gige_reg.h.

◆ RegClass

Enumerate the classes of registers.

Enumerator
IntRegClass 

Integer register.

FloatRegClass 

Floating-point register.

VecRegClass 

Vector Register.

VecElemClass 

Vector Register Native Elem lane.

VecPredRegClass 
CCRegClass 

Condition-code register.

MiscRegClass 

Control (misc) register.

Definition at line 55 of file reg_class.hh.

◆ RoundingMode

enum gem5::RoundingMode
strong
Enumerator
Downward 
ToNearest 
TowardZero 
Upward 

Definition at line 37 of file fenv.hh.

◆ ScalarRegInitFields

these enums represent the indices into the initialRegState bitfields in HsaKernelInfo.

each bit specifies whether or not the particular piece of state that the bit corresponds to should be initialized into the VGPRs/SGPRs. the order in which the fields are placed matters, as all enabled pieces of state will be initialized into contiguous registers in the same order as their position in the bitfield - which is specified in the HSA ABI.

Enumerator
PrivateSegBuf 
DispatchPtr 
QueuePtr 
KernargSegPtr 
DispatchId 
FlatScratchInit 
PrivateSegSize 
GridWorkgroupCountX 
GridWorkgroupCountY 
GridWorkgroupCountZ 
WorkgroupIdX 
WorkgroupIdY 
WorkgroupIdZ 
WorkgroupInfo 
PrivSegWaveByteOffset 
NumScalarInitFields 

Definition at line 56 of file kernel_code.hh.

◆ SDWADstVals [1/2]