gem5 v24.0.0.0
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dramsys_wrapper.hh
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1/*
2 * Copyright (c) 2022 Fraunhofer IESE
3 * All rights reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
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13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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27 */
28
29#ifndef __MEM_DRAMSYS_WRAPPER_HH__
30#define __MEM_DRAMSYS_WRAPPER_HH__
31
32#include <iostream>
33#include <memory>
34
35#include "DRAMSys/config/DRAMSysConfiguration.h"
36#include "DRAMSys/simulation/DRAMSysRecordable.h"
37#include "mem/abstract_mem.hh"
38#include "params/DRAMSys.hh"
39#include "sim/core.hh"
42
43#include "systemc/ext/systemc"
44#include "systemc/ext/tlm"
47
48namespace gem5
49{
50
51namespace memory
52{
53
55{
56 friend class DRAMSys;
57
58 public:
61 ::DRAMSys::Config::Configuration const &config,
62 bool recordable,
64
65 private:
66 static std::shared_ptr<::DRAMSys::DRAMSys>
67 instantiateDRAMSys(bool recordable,
68 ::DRAMSys::Config::Configuration const &config);
69
71 tlm::tlm_phase &phase,
72 sc_core::sc_time &fwDelay);
73
75 tlm::tlm_phase &phase,
76 sc_core::sc_time &bwDelay);
77
79 sc_core::sc_time &delay);
80
81 unsigned int transport_dbg(tlm::tlm_generic_payload &trans);
82
85
86 std::shared_ptr<::DRAMSys::DRAMSys> dramsys;
87
89};
90
91} // namespace memory
92} // namespace gem5
93
94#endif // __MEM_DRAMSYS_WRAPPER_HH__
AbstractMemory declaration.
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition addr_range.hh:82
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_core::sc_time &bwDelay)
DRAMSysWrapper(sc_core::sc_module_name name, ::DRAMSys::Config::Configuration const &config, bool recordable, AddrRange range)
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_core::sc_time &fwDelay)
std::shared_ptr<::DRAMSys::DRAMSys > dramsys
tlm_utils::simple_initiator_socket< DRAMSysWrapper > iSocket
unsigned int transport_dbg(tlm::tlm_generic_payload &trans)
void b_transport(tlm::tlm_generic_payload &payload, sc_core::sc_time &delay)
tlm_utils::simple_target_socket< DRAMSysWrapper > tSocket
static std::shared_ptr<::DRAMSys::DRAMSys > instantiateDRAMSys(bool recordable, ::DRAMSys::Config::Configuration const &config)
SC_HAS_PROCESS(DRAMSysWrapper)
const char * name() const
Definition sc_object.cc:44
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
tlm_sync_enum
Definition fw_bw_ifs.hh:31
Definition mem.h:38

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