gem5
v24.0.0.0
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arch
amdgpu
vega
insts
exp.cc
Go to the documentation of this file.
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/*
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* Copyright (c) 2024 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
arch/amdgpu/vega/insts/instructions.hh
"
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namespace
gem5
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{
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namespace
VegaISA
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{
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// --- Inst_EXP__EXP class methods ---
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Inst_EXP__EXP::Inst_EXP__EXP
(
InFmt_EXP
*iFmt)
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:
Inst_EXP
(iFmt,
"exp"
)
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{
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}
// Inst_EXP__EXP
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Inst_EXP__EXP::~Inst_EXP__EXP
()
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{
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}
// ~Inst_EXP__EXP
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// --- description from .arch file ---
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// Export through SX.
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void
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Inst_EXP__EXP::execute
(
GPUDynInstPtr
gpuDynInst)
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{
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panicUnimplemented
();
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}
// execute
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}
// namespace VegaISA
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}
// namespace gem5
gem5::VegaISA::Inst_EXP__EXP::~Inst_EXP__EXP
~Inst_EXP__EXP()
Definition
exp.cc:46
gem5::VegaISA::Inst_EXP__EXP::execute
void execute(GPUDynInstPtr) override
Definition
exp.cc:53
gem5::VegaISA::Inst_EXP__EXP::Inst_EXP__EXP
Inst_EXP__EXP(InFmt_EXP *)
Definition
exp.cc:41
gem5::VegaISA::Inst_EXP
Definition
op_encodings.hh:1127
gem5::VegaISA::VEGAGPUStaticInst::panicUnimplemented
void panicUnimplemented() const
Definition
gpu_static_inst.cc:54
instructions.hh
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition
misc.hh:49
gem5::VegaISA::InFmt_EXP
Definition
gpu_decoder.hh:1698
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