hwreg_defines.hh File Reference

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Namespaces
namespace	gem5
	Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.

Enumerations
enum	gem5::amdgpu_hwreg {   gem5::HW_REG_MODE = 0x1 , gem5::HW_REG_STATUS = 0x2 , gem5::HW_REG_TRAPSTS = 0x3 , gem5::HW_REG_HW_ID = 0x4 ,   gem5::HW_REG_GPR_ALLOC = 0x5 , gem5::HW_REG_LDS_ALLOC = 0x6 , gem5::HW_REG_IB_STS = 0x7 , gem5::HW_REG_SH_MEM_BASES = 0xf ,   gem5::HW_REG_TBA_LO = 0x10 , gem5::HW_REG_TBA_HI = 0x11 , gem5::HW_REG_TMA_LO = 0x12 , gem5::HW_REG_TMA_HI = 0x13 ,   gem5::HW_REG_FLAT_SCR_LO = 0x14 , gem5::HW_REG_FLAT_SCR_HI = 0x15 , gem5::HW_REG_XNACK_MASK = 0x16 , gem5::HW_REG_HW_ID1 = 0x17 ,   gem5::HW_REG_HW_ID2 = 0x18 , gem5::HW_REG_POPS_PACKER = 0x19 , gem5::HW_REG_SHADER_CYCLES = 0x1d }