gem5  v22.0.0.2
segment.hh
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37 
38 #ifndef __ARCH_X86_SEGMENTREGS_HH__
39 #define __ARCH_X86_SEGMENTREGS_HH__
40 
41 namespace gem5
42 {
43 namespace X86ISA
44 {
45 namespace segment_idx
46 {
47 
48 enum
49 {
50  Es,
51  Cs,
52  Ss,
53  Ds,
54  Fs,
55  Gs,
56  Hs, // Temporary descriptor
57  Tsl, // Local descriptor table
58  Tsg, // Global descriptor table
59  Ls, // Flat segment
60  Ms, // Emulation memory
61  // These shouldn't be used directly in a load or store since they
62  // are likely accessed in other ways in a real machine. For instance,
63  // they may be loaded into the temporary segment register on demand.
64  Tr,
66 
68 };
69 
70 } // namespace segment_idx
71 } // namespace X86ISA
72 } // namespace gem5
73 
74 #endif // __ARCH_X86_SEGMENTREGS_HH__
gem5::X86ISA::segment_idx::Ls
@ Ls
Definition: segment.hh:59
gem5::X86ISA::segment_idx::Ds
@ Ds
Definition: segment.hh:53
gem5::X86ISA::segment_idx::Tsl
@ Tsl
Definition: segment.hh:57
gem5::X86ISA::segment_idx::Cs
@ Cs
Definition: segment.hh:51
gem5::X86ISA::segment_idx::Gs
@ Gs
Definition: segment.hh:55
gem5::X86ISA::segment_idx::Es
@ Es
Definition: segment.hh:50
gem5::X86ISA::segment_idx::Tr
@ Tr
Definition: segment.hh:64
gem5::X86ISA::segment_idx::Tsg
@ Tsg
Definition: segment.hh:58
gem5::X86ISA::segment_idx::Ss
@ Ss
Definition: segment.hh:52
gem5::X86ISA::segment_idx::Ms
@ Ms
Definition: segment.hh:60
gem5::X86ISA::segment_idx::Fs
@ Fs
Definition: segment.hh:54
gem5::X86ISA::segment_idx::NumIdxs
@ NumIdxs
Definition: segment.hh:67
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::segment_idx::Idtr
@ Idtr
Definition: segment.hh:65
gem5::X86ISA::segment_idx::Hs
@ Hs
Definition: segment.hh:56

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