#include <exec_context.hh>

Inheritance diagram for SimpleExecContext:

Public Member Functions
	SimpleExecContext (BaseSimpleCPU _cpu, SimpleThread _thread)
	Constructor. More...

RegVal	readIntRegOperand (const StaticInst *si, int idx) override
	Reads an integer register. More...

void	setIntRegOperand (const StaticInst *si, int idx, RegVal val) override
	Sets an integer register to a value. More...

RegVal	readFloatRegOperandBits (const StaticInst *si, int idx) override
	Reads a floating point register in its binary format, instead of by value. More...

void	setFloatRegOperandBits (const StaticInst *si, int idx, RegVal val) override
	Sets the bits of a floating point register of single width to a binary value. More...

const VecRegContainer &	readVecRegOperand (const StaticInst *si, int idx) const override
	Reads a vector register. More...

VecRegContainer &	getWritableVecRegOperand (const StaticInst *si, int idx) override
	Reads a vector register for modification. More...

void	setVecRegOperand (const StaticInst *si, int idx, const VecRegContainer &val) override
	Sets a vector register to a value. More...

VecElem	readVecElemOperand (const StaticInst *si, int idx) const override
	Reads an element of a vector register. More...

void	setVecElemOperand (const StaticInst *si, int idx, const VecElem val) override
	Sets an element of a vector register to a value. More...

const VecPredRegContainer &	readVecPredRegOperand (const StaticInst *si, int idx) const override
	Predicate registers interface. More...

VecPredRegContainer &	getWritableVecPredRegOperand (const StaticInst *si, int idx) override
	Gets destination predicate register operand for modification. More...

void	setVecPredRegOperand (const StaticInst *si, int idx, const VecPredRegContainer &val) override
	Sets a destination predicate register operand to a value. More...

RegVal	readCCRegOperand (const StaticInst *si, int idx) override

void	setCCRegOperand (const StaticInst *si, int idx, RegVal val) override

RegVal	readMiscRegOperand (const StaticInst *si, int idx) override

void	setMiscRegOperand (const StaticInst *si, int idx, RegVal val) override

RegVal	readMiscReg (int misc_reg) override
	Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...

void	setMiscReg (int misc_reg, RegVal val) override
	Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...

PCState	pcState () const override

void	pcState (const PCState &val) override

Fault	readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override
	Perform an atomic memory read operation. More...

Fault	initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override
	Initiate a timing memory read operation. More...

Fault	writeMem (uint8_t data, unsigned int size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable=std::vector< bool >()) override
	For atomic-mode contexts, perform an atomic memory write operation. More...

Fault	amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
	For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More...

Fault	initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
	For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More...

void	setStCondFailures (unsigned int sc_failures) override
	Sets the number of consecutive store conditional failures. More...

unsigned int	readStCondFailures () const override
	Returns the number of consecutive store conditional failures. More...

void	syscall (Fault *fault) override
	Executes a syscall specified by the callnum. More...

ThreadContext *	tcBase () override
	Returns a pointer to the ThreadContext. More...

bool	readPredicate () const override

void	setPredicate (bool val) override

bool	readMemAccPredicate () const override

void	setMemAccPredicate (bool val) override

void	demapPage (Addr vaddr, uint64_t asn) override
	Invalidate a page in the DTLB and ITLB. More...

void	armMonitor (Addr address) override

bool	mwait (PacketPtr pkt) override

void	mwaitAtomic (ThreadContext *tc) override

AddressMonitor *	getAddrMonitor () override


template<typename VecElem >
VecLaneT< VecElem, true >	readVecLaneOperand (const StaticInst *si, int idx) const
	Vector Register Lane Interfaces. More...

virtual ConstVecLane8	readVec8BitLaneOperand (const StaticInst *si, int idx) const override
	Reads source vector 8bit operand. More...

virtual ConstVecLane16	readVec16BitLaneOperand (const StaticInst *si, int idx) const override
	Reads source vector 16bit operand. More...

virtual ConstVecLane32	readVec32BitLaneOperand (const StaticInst *si, int idx) const override
	Reads source vector 32bit operand. More...

virtual ConstVecLane64	readVec64BitLaneOperand (const StaticInst *si, int idx) const override
	Reads source vector 64bit operand. More...

template<typename LD >
void	setVecLaneOperandT (const StaticInst *si, int idx, const LD &val)
	Write a lane of the destination vector operand. More...

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::Byte > &val) override
	Write a lane of the destination vector operand. More...

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::TwoByte > &val) override
	Write a lane of the destination vector operand. More...

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::FourByte > &val) override
	Write a lane of the destination vector operand. More...

virtual void	setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::EightByte > &val) override
	Write a lane of the destination vector operand. More...

Integer Register Interfaces
Floating Point Register Interfaces




Condition Code Registers
Misc Register Interfaces
PC Control
Memory Interface
SysCall Emulation Interfaces
ARM-Specific Interfaces
X86-Specific Interfaces

Public Attributes
BaseSimpleCPU *	cpu

SimpleThread *	thread

Addr	fetchOffset

bool	stayAtPC

TheISA::PCState	predPC

Counter	numInst
	PER-THREAD STATS. More...

Stats::Scalar	numInsts

Counter	numOp

Stats::Scalar	numOps

Stats::Scalar	numIntAluAccesses

Stats::Scalar	numFpAluAccesses

Stats::Scalar	numVecAluAccesses

Stats::Scalar	numCallsReturns

Stats::Scalar	numCondCtrlInsts

Stats::Scalar	numIntInsts

Stats::Scalar	numFpInsts

Stats::Scalar	numVecInsts

Stats::Scalar	numIntRegReads

Stats::Scalar	numIntRegWrites

Stats::Scalar	numFpRegReads

Stats::Scalar	numFpRegWrites

Stats::Scalar	numVecRegReads

Stats::Scalar	numVecRegWrites

Stats::Scalar	numVecPredRegReads

Stats::Scalar	numVecPredRegWrites

Stats::Scalar	numCCRegReads

Stats::Scalar	numCCRegWrites

Stats::Scalar	numMemRefs

Stats::Scalar	numLoadInsts

Stats::Scalar	numStoreInsts

Stats::Formula	numIdleCycles

Stats::Formula	numBusyCycles

Counter	numLoad

Stats::Average	notIdleFraction

Stats::Formula	idleFraction

Stats::Scalar	icacheStallCycles

Counter	lastIcacheStall

Stats::Scalar	dcacheStallCycles

Counter	lastDcacheStall

Stats::Vector	statExecutedInstType


Stats::Scalar	numBranches

Stats::Scalar	numPredictedBranches
	Number of branches predicted as taken. More...

Stats::Scalar	numBranchMispred
	Number of misprediced branches. More...

Protected Types
using	VecRegContainer = TheISA::VecRegContainer

using	VecElem = TheISA::VecElem

Additional Inherited Members
Public Types inherited from ExecContext
typedef TheISA::PCState	PCState

using	VecRegContainer = TheISA::VecRegContainer

using	VecElem = TheISA::VecElem

using	VecPredRegContainer = TheISA::VecPredRegContainer

Detailed Description

Definition at line 61 of file exec_context.hh.

Member Typedef Documentation

◆ VecElem

using SimpleExecContext::VecElem = TheISA::VecElem

protected

Definition at line 64 of file exec_context.hh.

◆ VecRegContainer

using SimpleExecContext::VecRegContainer = TheISA::VecRegContainer

protected

Definition at line 63 of file exec_context.hh.

Constructor & Destructor Documentation

◆ SimpleExecContext()

SimpleExecContext::SimpleExecContext	(	BaseSimpleCPU *	_cpu,
		SimpleThread *	_thread
	)

inline

Constructor.

Definition at line 171 of file exec_context.hh.

Member Function Documentation

◆ amoMem()

Fault SimpleExecContext::amoMem	(	Addr	addr,
		uint8_t *	data,
		unsigned int	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

inlineoverridevirtual

For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)

Reimplemented from ExecContext.

Definition at line 467 of file exec_context.hh.

References BaseSimpleCPU::amoMem().

◆ armMonitor()

void SimpleExecContext::armMonitor ( Addr address )

inlineoverridevirtual

Implements ExecContext.

Definition at line 548 of file exec_context.hh.

References BaseCPU::armMonitor(), and SimpleThread::threadId().

◆ demapPage()

void SimpleExecContext::demapPage	(	Addr	vaddr,
		uint64_t	asn
	)

inlineoverridevirtual

Invalidate a page in the DTLB and ITLB.

Implements ExecContext.

Definition at line 542 of file exec_context.hh.

References SimpleThread::demapPage().

◆ getAddrMonitor()

AddressMonitor* SimpleExecContext::getAddrMonitor ( )

inlineoverridevirtual

Implements ExecContext.

Definition at line 566 of file exec_context.hh.

References BaseCPU::getCpuAddrMonitor(), and SimpleThread::threadId().

◆ getWritableVecPredRegOperand()

VecPredRegContainer& SimpleExecContext::getWritableVecPredRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Gets destination predicate register operand for modification.

Implements ExecContext.

Definition at line 349 of file exec_context.hh.

References StaticInst::destRegIdx(), SimpleThread::getWritableVecPredReg(), RegId::isVecPredReg(), and X86ISA::reg.

◆ getWritableVecRegOperand()

VecRegContainer& SimpleExecContext::getWritableVecRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Reads a vector register for modification.

Implements ExecContext.

Definition at line 230 of file exec_context.hh.

References StaticInst::destRegIdx(), SimpleThread::getWritableVecReg(), RegId::isVecReg(), and X86ISA::reg.

◆ initiateMemAMO()

Fault SimpleExecContext::initiateMemAMO	(	Addr	addr,
		unsigned int	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

inlineoverridevirtual

For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)

Reimplemented from ExecContext.

Definition at line 473 of file exec_context.hh.

References BaseSimpleCPU::initiateMemAMO().

◆ initiateMemRead()

Fault SimpleExecContext::initiateMemRead	(	Addr	addr,
		unsigned int	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

inlineoverridevirtual

Initiate a timing memory read operation.

Must be overridden for exec contexts that support timing memory mode. Not pure virtual since exec contexts that only support atomic memory mode need not override (though in that case this function should never be called).

Reimplemented from ExecContext.

Definition at line 448 of file exec_context.hh.

References BaseSimpleCPU::initiateMemRead().

◆ mwait()

bool SimpleExecContext::mwait ( PacketPtr pkt )

inlineoverridevirtual

Implements ExecContext.

Definition at line 554 of file exec_context.hh.

References BaseCPU::mwait(), and SimpleThread::threadId().

◆ mwaitAtomic()

void SimpleExecContext::mwaitAtomic ( ThreadContext * tc )

inlineoverridevirtual

Implements ExecContext.

Definition at line 560 of file exec_context.hh.

References SimpleThread::dtb, BaseCPU::mwaitAtomic(), and SimpleThread::threadId().

◆ pcState() [1/2]

PCState SimpleExecContext::pcState ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 426 of file exec_context.hh.

References SimpleThread::pcState().

◆ pcState() [2/2]

void SimpleExecContext::pcState ( const PCState & val )

inlineoverridevirtual

Implements ExecContext.

Definition at line 432 of file exec_context.hh.

References SimpleThread::pcState().

◆ readCCRegOperand()

RegVal SimpleExecContext::readCCRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 368 of file exec_context.hh.

References RegId::index(), RegId::isCCReg(), SimpleThread::readCCReg(), X86ISA::reg, and StaticInst::srcRegIdx().

◆ readFloatRegOperandBits()

RegVal SimpleExecContext::readFloatRegOperandBits	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Reads a floating point register in its binary format, instead of by value.

Implements ExecContext.

Definition at line 199 of file exec_context.hh.

References RegId::index(), RegId::isFloatReg(), SimpleThread::readFloatReg(), X86ISA::reg, and StaticInst::srcRegIdx().

◆ readIntRegOperand()

RegVal SimpleExecContext::readIntRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Reads an integer register.

Implements ExecContext.

Definition at line 178 of file exec_context.hh.

References RegId::index(), RegId::isIntReg(), SimpleThread::readIntReg(), X86ISA::reg, and StaticInst::srcRegIdx().

◆ readMem()

Fault SimpleExecContext::readMem	(	Addr	addr,
		uint8_t *	data,
		unsigned int	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

inlineoverridevirtual

Perform an atomic memory read operation.

Must be overridden for exec contexts that support atomic memory mode. Not pure virtual since exec contexts that only support timing memory mode need not override (though in that case this function should never be called).

Reimplemented from ExecContext.

Definition at line 438 of file exec_context.hh.

References BaseSimpleCPU::readMem().

◆ readMemAccPredicate()

bool SimpleExecContext::readMemAccPredicate ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 527 of file exec_context.hh.

References SimpleThread::readMemAccPredicate().

◆ readMiscReg()

RegVal SimpleExecContext::readMiscReg ( int misc_reg )

inlineoverridevirtual

Reads a miscellaneous register, handling any architectural side effects due to reading that register.

Implements ExecContext.

Definition at line 408 of file exec_context.hh.

References SimpleThread::readMiscReg().

◆ readMiscRegOperand()

RegVal SimpleExecContext::readMiscRegOperand	(	const StaticInst *	si,
		int	idx
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 386 of file exec_context.hh.

References RegId::index(), RegId::isMiscReg(), SimpleThread::readMiscReg(), X86ISA::reg, and StaticInst::srcRegIdx().

◆ readPredicate()

bool SimpleExecContext::readPredicate ( ) const

inlineoverridevirtual

Implements ExecContext.

Definition at line 511 of file exec_context.hh.

References SimpleThread::readPredicate().

◆ readStCondFailures()

unsigned int SimpleExecContext::readStCondFailures ( ) const

inlineoverridevirtual

Returns the number of consecutive store conditional failures.

Implements ExecContext.

Definition at line 493 of file exec_context.hh.

References SimpleThread::readStCondFailures().

◆ readVec16BitLaneOperand()

virtual ConstVecLane16 SimpleExecContext::readVec16BitLaneOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Reads source vector 16bit operand.

Implements ExecContext.

Definition at line 269 of file exec_context.hh.

References PowerISA::si.

◆ readVec32BitLaneOperand()

virtual ConstVecLane32 SimpleExecContext::readVec32BitLaneOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Reads source vector 32bit operand.

Implements ExecContext.

Definition at line 275 of file exec_context.hh.

References PowerISA::si.

◆ readVec64BitLaneOperand()

virtual ConstVecLane64 SimpleExecContext::readVec64BitLaneOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Reads source vector 64bit operand.

Implements ExecContext.

Definition at line 281 of file exec_context.hh.

References PowerISA::si.

◆ readVec8BitLaneOperand()

virtual ConstVecLane8 SimpleExecContext::readVec8BitLaneOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Reads source vector 8bit operand.

Implements ExecContext.

Definition at line 263 of file exec_context.hh.

References PowerISA::si.

◆ readVecElemOperand()

VecElem SimpleExecContext::readVecElemOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Reads an element of a vector register.

Implements ExecContext.

Definition at line 320 of file exec_context.hh.

References RegId::isVecElem(), SimpleThread::readVecElem(), X86ISA::reg, and StaticInst::srcRegIdx().

◆ readVecLaneOperand()

template<typename VecElem >

VecLaneT<VecElem, true> SimpleExecContext::readVecLaneOperand	(	const StaticInst *	si,
		int	idx
	)		const

inline

Vector Register Lane Interfaces.

Reads source vector lane.

Definition at line 254 of file exec_context.hh.

References RegId::isVecReg(), SimpleThread::readVecLane(), X86ISA::reg, and StaticInst::srcRegIdx().

◆ readVecPredRegOperand()

const VecPredRegContainer& SimpleExecContext::readVecPredRegOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Predicate registers interface.

Reads source predicate register operand.

Implements ExecContext.

Definition at line 340 of file exec_context.hh.

References RegId::isVecPredReg(), SimpleThread::readVecPredReg(), X86ISA::reg, and StaticInst::srcRegIdx().

◆ readVecRegOperand()

const VecRegContainer& SimpleExecContext::readVecRegOperand	(	const StaticInst *	si,
		int	idx
	)		const

inlineoverridevirtual

Reads a vector register.

Implements ExecContext.

Definition at line 220 of file exec_context.hh.

References RegId::isVecReg(), SimpleThread::readVecReg(), X86ISA::reg, and StaticInst::srcRegIdx().

◆ setCCRegOperand()

void SimpleExecContext::setCCRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 377 of file exec_context.hh.

References StaticInst::destRegIdx(), RegId::index(), RegId::isCCReg(), X86ISA::reg, SimpleThread::setCCReg(), and X86ISA::val.

◆ setFloatRegOperandBits()

void SimpleExecContext::setFloatRegOperandBits	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Sets the bits of a floating point register of single width to a binary value.

Implements ExecContext.

Definition at line 210 of file exec_context.hh.

References StaticInst::destRegIdx(), RegId::index(), RegId::isFloatReg(), X86ISA::reg, SimpleThread::setFloatReg(), and X86ISA::val.

◆ setIntRegOperand()

void SimpleExecContext::setIntRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Sets an integer register to a value.

Implements ExecContext.

Definition at line 188 of file exec_context.hh.

References StaticInst::destRegIdx(), RegId::index(), RegId::isIntReg(), X86ISA::reg, SimpleThread::setIntReg(), and X86ISA::val.

◆ setMemAccPredicate()

void SimpleExecContext::setMemAccPredicate ( bool val )

inlineoverridevirtual

Implements ExecContext.

Definition at line 533 of file exec_context.hh.

References SimpleThread::setMemAccPredicate().

Referenced by BaseSimpleCPU::preExecute().

◆ setMiscReg()

void SimpleExecContext::setMiscReg	(	int	misc_reg,
		RegVal	val
	)

inlineoverridevirtual

Sets a miscellaneous register, handling any architectural side effects due to writing that register.

Implements ExecContext.

Definition at line 419 of file exec_context.hh.

References SimpleThread::setMiscReg().

◆ setMiscRegOperand()

void SimpleExecContext::setMiscRegOperand	(	const StaticInst *	si,
		int	idx,
		RegVal	val
	)

inlineoverridevirtual

Implements ExecContext.

Definition at line 395 of file exec_context.hh.

References StaticInst::destRegIdx(), RegId::index(), RegId::isMiscReg(), X86ISA::reg, SimpleThread::setMiscReg(), and X86ISA::val.

◆ setPredicate()

void SimpleExecContext::setPredicate ( bool val )

inlineoverridevirtual

Implements ExecContext.

Definition at line 517 of file exec_context.hh.

References Trace::InstRecord::setPredicate(), SimpleThread::setPredicate(), and BaseSimpleCPU::traceData.

Referenced by BaseSimpleCPU::preExecute().

◆ setStCondFailures()

void SimpleExecContext::setStCondFailures ( unsigned int sc_failures )

inlineoverridevirtual

Sets the number of consecutive store conditional failures.

Implements ExecContext.

Definition at line 484 of file exec_context.hh.

References SimpleThread::setStCondFailures().

◆ setVecElemOperand()

void SimpleExecContext::setVecElemOperand	(	const StaticInst *	si,
		int	idx,
		const VecElem	val
	)

inlineoverridevirtual

Sets an element of a vector register to a value.

Implements ExecContext.

Definition at line 330 of file exec_context.hh.

References StaticInst::destRegIdx(), RegId::isVecElem(), X86ISA::reg, and SimpleThread::setVecElem().

◆ setVecLaneOperand() [1/4]

virtual void SimpleExecContext::setVecLaneOperand	(	const StaticInst *	si,
		int	idx,
		const LaneData< LaneSize::Byte > &	val
	)

inlineoverridevirtual

Write a lane of the destination vector operand.

Implements ExecContext.

Definition at line 298 of file exec_context.hh.

References setVecLaneOperandT().

◆ setVecLaneOperand() [2/4]

virtual void SimpleExecContext::setVecLaneOperand	(	const StaticInst *	si,
		int	idx,
		const LaneData< LaneSize::TwoByte > &	val
	)

inlineoverridevirtual

Write a lane of the destination vector operand.

Implements ExecContext.

Definition at line 303 of file exec_context.hh.

References setVecLaneOperandT().

◆ setVecLaneOperand() [3/4]

virtual void SimpleExecContext::setVecLaneOperand	(	const StaticInst *	si,
		int	idx,
		const LaneData< LaneSize::FourByte > &	val
	)

inlineoverridevirtual

Write a lane of the destination vector operand.

Implements ExecContext.

Definition at line 308 of file exec_context.hh.

References setVecLaneOperandT().

◆ setVecLaneOperand() [4/4]

virtual void SimpleExecContext::setVecLaneOperand	(	const StaticInst *	si,
		int	idx,
		const LaneData< LaneSize::EightByte > &	val
	)

inlineoverridevirtual

Write a lane of the destination vector operand.

Implements ExecContext.

Definition at line 313 of file exec_context.hh.

References setVecLaneOperandT().

◆ setVecLaneOperandT()

template<typename LD >

void SimpleExecContext::setVecLaneOperandT	(	const StaticInst *	si,
		int	idx,
		const LD &	val
	)

inline

Write a lane of the destination vector operand.

Definition at line 288 of file exec_context.hh.

References StaticInst::destRegIdx(), RegId::isVecReg(), X86ISA::reg, and SimpleThread::setVecLane().

Referenced by setVecLaneOperand().

◆ setVecPredRegOperand()

void SimpleExecContext::setVecPredRegOperand	(	const StaticInst *	si,
		int	idx,
		const VecPredRegContainer &	val
	)

inlineoverridevirtual

Sets a destination predicate register operand to a value.

Implements ExecContext.

Definition at line 358 of file exec_context.hh.

References StaticInst::destRegIdx(), RegId::isVecPredReg(), X86ISA::reg, and SimpleThread::setVecPredReg().

◆ setVecRegOperand()

void SimpleExecContext::setVecRegOperand	(	const StaticInst *	si,
		int	idx,
		const VecRegContainer &	val
	)

inlineoverridevirtual

Sets a vector register to a value.

Implements ExecContext.

Definition at line 240 of file exec_context.hh.

References StaticInst::destRegIdx(), RegId::isVecReg(), X86ISA::reg, and SimpleThread::setVecReg().

◆ syscall()

void SimpleExecContext::syscall ( Fault * fault )

inlineoverridevirtual

Executes a syscall specified by the callnum.

Implements ExecContext.

Definition at line 502 of file exec_context.hh.

References SimpleThread::syscall().

◆ tcBase()

ThreadContext* SimpleExecContext::tcBase ( )

inlineoverridevirtual

Returns a pointer to the ThreadContext.

Implements ExecContext.

Definition at line 508 of file exec_context.hh.

References SimpleThread::getTC().

◆ writeMem()

Fault SimpleExecContext::writeMem	(	uint8_t *	data,
		unsigned int	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable = `std::vector< bool >()`
	)