| A3V | Gicv3CPUInterface | protected |
| A3V | Gicv3CPUInterface | protected |
| assertWakeRequest(void) | Gicv3CPUInterface | protected |
| BaseISADevice() | ArmISA::BaseISADevice | |
| BitUnion32(ICH_LRC) Bitfield< 31 | Gicv3CPUInterface | protected |
| BitUnion64(ICC_CTLR_EL1) Bitfield< 63 | Gicv3CPUInterface | protected |
| BitUnion64(ICH_HCR_EL2) Bitfield< 63 | Gicv3CPUInterface | protected |
| bpr1(Gicv3::GroupId group) | Gicv3CPUInterface | protected |
| CBPR | Gicv3CPUInterface | protected |
| CBPR_EL1NS | Gicv3CPUInterface | protected |
| CBPR_EL1S | Gicv3CPUInterface | protected |
| clearPendingInterrupts(void) | Gicv3CPUInterface | protected |
| cpuId | Gicv3CPUInterface | protected |
| currEL() const | Gicv3CPUInterface | protected |
| currentSection() | Serializable | static |
| deactivateIRQ(uint32_t intid, Gicv3::GroupId group) | Gicv3CPUInterface | protected |
| deassertWakeRequest(void) | Gicv3CPUInterface | protected |
| DFB | Gicv3CPUInterface | protected |
| DIB | Gicv3CPUInterface | protected |
| distributor | Gicv3CPUInterface | protected |
| dropPriority(Gicv3::GroupId group) | Gicv3CPUInterface | protected |
| En | Gicv3CPUInterface | protected |
| Enable | Gicv3CPUInterface | protected |
| Enable | Gicv3CPUInterface | protected |
| EnableGrp1NS | Gicv3CPUInterface | protected |
| EnableGrp1S | Gicv3CPUInterface | protected |
| EndBitUnion(ICC_CTLR_EL1) BitUnion64(ICC_CTLR_EL3) Bitfield< 63 | Gicv3CPUInterface | protected |
| EndBitUnion(ICC_CTLR_EL3) BitUnion64(ICC_IGRPEN0_EL1) Bitfield< 63 | Gicv3CPUInterface | protected |
| EndBitUnion(ICC_IGRPEN0_EL1) BitUnion64(ICC_IGRPEN1_EL1) Bitfield< 63 | Gicv3CPUInterface | protected |
| EndBitUnion(ICC_IGRPEN1_EL1) BitUnion64(ICC_IGRPEN1_EL3) Bitfield< 63 | Gicv3CPUInterface | protected |
| EndBitUnion(ICC_IGRPEN1_EL3) BitUnion64(ICC_SRE_EL1) Bitfield< 63 | Gicv3CPUInterface | protected |
| EndBitUnion(ICC_SRE_EL1) BitUnion64(ICC_SRE_EL2) Bitfield< 63 | Gicv3CPUInterface | protected |
| EndBitUnion(ICC_SRE_EL2) BitUnion64(ICC_SRE_EL3) Bitfield< 63 | Gicv3CPUInterface | protected |
| EndBitUnion(ICC_SRE_EL3) static const uint8_t PRIORITY_BITS | Gicv3CPUInterface | protected |
| EndBitUnion(ICH_HCR_EL2) BitUnion64(ICH_LR_EL2) Bitfield< 63 | Gicv3CPUInterface | protected |
| EndBitUnion(ICH_LR_EL2) static const uint64_t ICH_LR_EL2_STATE_INVALID=0 | Gicv3CPUInterface | protectedpure virtual |
| EndBitUnion(ICH_LRC) BitUnion64(ICH_MISR_EL2) Bitfield< 63 | Gicv3CPUInterface | protected |
| EndBitUnion(ICH_MISR_EL2) BitUnion64(ICH_VMCR_EL2) Bitfield< 63 | Gicv3CPUInterface | protected |
| EndBitUnion(ICH_VMCR_EL2) BitUnion64(ICH_VTR_EL2) Bitfield< 63 | Gicv3CPUInterface | protected |
| EndBitUnion(ICH_VTR_EL2) BitUnion64(ICV_CTLR_EL1) Bitfield< 63 | Gicv3CPUInterface | protected |
| EOI | Gicv3CPUInterface | protected |
| EOI | Gicv3CPUInterface | protected |
| EOI | Gicv3CPUInterface | protected |
| EOIcount | Gicv3CPUInterface | protected |
| eoiMaintenanceInterruptStatus() const | Gicv3CPUInterface | protected |
| EOImode | Gicv3CPUInterface | protected |
| EOImode_EL1NS | Gicv3CPUInterface | protected |
| EOImode_EL1S | Gicv3CPUInterface | protected |
| EOImode_EL3 | Gicv3CPUInterface | protected |
| ExtRange | Gicv3CPUInterface | protected |
| generateSGI(RegVal val, Gicv3::GroupId group) | Gicv3CPUInterface | protected |
| getHCREL2FMO() const | Gicv3CPUInterface | protected |
| getHCREL2IMO() const | Gicv3CPUInterface | protected |
| getHPPIR0() const | Gicv3CPUInterface | protected |
| getHPPIR1() const | Gicv3CPUInterface | protected |
| getHPPVILR() const | Gicv3CPUInterface | protected |
| gic | Gicv3CPUInterface | protected |
| GIC_MIN_BPR | Gicv3CPUInterface | protectedstatic |
| GIC_MIN_BPR_NS | Gicv3CPUInterface | protectedstatic |
| GIC_MIN_VBPR | Gicv3CPUInterface | protectedstatic |
| GICC_ABPR enum value | Gicv3CPUInterface | protected |
| GICC_AEOIR enum value | Gicv3CPUInterface | protected |
| GICC_AHPPIR enum value | Gicv3CPUInterface | protected |
| GICC_AIAR enum value | Gicv3CPUInterface | protected |
| GICC_APR | Gicv3CPUInterface | protectedstatic |
| GICC_BPR enum value | Gicv3CPUInterface | protected |
| GICC_CTLR enum value | Gicv3CPUInterface | protected |
| GICC_EOIR enum value | Gicv3CPUInterface | protected |
| GICC_HPPI enum value | Gicv3CPUInterface | protected |
| GICC_IAR enum value | Gicv3CPUInterface | protected |
| GICC_IIDR enum value | Gicv3CPUInterface | protected |
| GICC_NSAPR | Gicv3CPUInterface | protectedstatic |
| GICC_PMR enum value | Gicv3CPUInterface | protected |
| GICC_RPR enum value | Gicv3CPUInterface | protected |
| GICC_STATUSR enum value | Gicv3CPUInterface | protected |
| GICH_APR | Gicv3CPUInterface | protectedstatic |
| GICH_EISR enum value | Gicv3CPUInterface | protected |
| GICH_ELRSR enum value | Gicv3CPUInterface | protected |
| GICH_HCR enum value | Gicv3CPUInterface | protected |
| GICH_LR | Gicv3CPUInterface | protectedstatic |
| GICH_MISR enum value | Gicv3CPUInterface | protected |
| GICH_VMCR enum value | Gicv3CPUInterface | protected |
| GICH_VTR enum value | Gicv3CPUInterface | protected |
| Gicv3CPUInterface(Gicv3 *gic, uint32_t cpu_id) | Gicv3CPUInterface | |
| Gicv3Distributor class | Gicv3CPUInterface | friend |
| Gicv3Redistributor class | Gicv3CPUInterface | friend |
| Group | Gicv3CPUInterface | protected |
| Group | Gicv3CPUInterface | protected |
| groupEnabled(Gicv3::GroupId group) const | Gicv3CPUInterface | protected |
| groupPriorityMask(Gicv3::GroupId group) | Gicv3CPUInterface | protected |
| haveEL(ArmISA::ExceptionLevel el) const | Gicv3CPUInterface | protected |
| havePendingInterrupts(void) const | Gicv3CPUInterface | protected |
| highestActiveGroup() const | Gicv3CPUInterface | protected |
| highestActivePriority() const | Gicv3CPUInterface | protected |
| hppi | Gicv3CPUInterface | protected |
| hppiCanPreempt() | Gicv3CPUInterface | protected |
| hppviCanPreempt(int lrIdx) const | Gicv3CPUInterface | protected |
| HW | Gicv3CPUInterface | protected |
| HW | Gicv3CPUInterface | protected |
| ICH_LR_EL2_STATE_ACTIVE | Gicv3CPUInterface | protectedstatic |
| ICH_LR_EL2_STATE_ACTIVE_PENDING | Gicv3CPUInterface | protectedstatic |
| ICH_LR_EL2_STATE_PENDING | Gicv3CPUInterface | protectedstatic |
| IDbits | Gicv3CPUInterface | protected |
| IDbits | Gicv3CPUInterface | protected |
| init() | Gicv3CPUInterface | |
| inSecureState() const | Gicv3CPUInterface | protected |
| intSignalType(Gicv3::GroupId group) const | Gicv3CPUInterface | protected |
| isa | ArmISA::BaseISADevice | protected |
| isAA64() const | Gicv3CPUInterface | protected |
| isEL3OrMon() const | Gicv3CPUInterface | protected |
| isEOISplitMode() const | Gicv3CPUInterface | protected |
| isSecureBelowEL3() const | Gicv3CPUInterface | protected |
| ListRegs | Gicv3CPUInterface | protected |
| LRENP | Gicv3CPUInterface | protected |
| LRENPIE | Gicv3CPUInterface | protected |
| maintenanceInterrupt | Gicv3CPUInterface | protected |
| maintenanceInterruptStatus() const | Gicv3CPUInterface | protected |
| nDS | Gicv3CPUInterface | protected |
| NP | Gicv3CPUInterface | protected |
| NPIE | Gicv3CPUInterface | protected |
| pINTID | Gicv3CPUInterface | protected |
| pINTID | Gicv3CPUInterface | protected |
| PMHE | Gicv3CPUInterface | protected |
| PREbits | Gicv3CPUInterface | protected |
| PRIbits | Gicv3CPUInterface | protected |
| PRIbits | Gicv3CPUInterface | protected |
| Priority | Gicv3CPUInterface | protected |
| Priority | Gicv3CPUInterface | protected |
| readBankedMiscReg(MiscRegIndex misc_reg) const | Gicv3CPUInterface | protected |
| readMiscReg(int misc_reg) override | Gicv3CPUInterface | virtual |
| redistributor | Gicv3CPUInterface | protected |
| res0 | Gicv3CPUInterface | protected |
| res0_0 | Gicv3CPUInterface | protected |
| res0_0 | Gicv3CPUInterface | protected |
| res0_0 | Gicv3CPUInterface | protected |
| res0_0 | Gicv3CPUInterface | protected |
| res0_0 | Gicv3CPUInterface | protected |
| res0_0 | Gicv3CPUInterface | protected |
| res0_0 | Gicv3CPUInterface | protected |
| res0_0 | Gicv3CPUInterface | protected |
| res0_1 | Gicv3CPUInterface | protected |
| res0_1 | Gicv3CPUInterface | protected |
| res0_1 | Gicv3CPUInterface | protected |
| res0_1 | Gicv3CPUInterface | protected |
| res0_1 | Gicv3CPUInterface | protected |
| res0_1 | Gicv3CPUInterface | protected |
| res0_1 | Gicv3CPUInterface | protected |
| res0_1 | Gicv3CPUInterface | protected |
| res0_2 | Gicv3CPUInterface | protected |
| res0_2 | Gicv3CPUInterface | protected |
| res0_3 | Gicv3CPUInterface | protected |
| res1 | Gicv3CPUInterface | protected |
| resetHppi(uint32_t intid) | Gicv3CPUInterface | protected |
| RM | Gicv3CPUInterface | protected |
| RSS | Gicv3CPUInterface | protected |
| SEIS | Gicv3CPUInterface | protected |
| SEIS | Gicv3CPUInterface | protected |
| Serializable() | Serializable | |
| serialize(CheckpointOut &cp) const override | Gicv3CPUInterface | protectedvirtual |
| serializeAll(const std::string &cpt_dir) | Serializable | static |
| serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
| setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const | Gicv3CPUInterface | protected |
| setISA(ISA *isa) | ArmISA::BaseISADevice | virtual |
| setMiscReg(int misc_reg, RegVal val) override | Gicv3CPUInterface | virtual |
| setThreadContext(ThreadContext *tc) override | Gicv3CPUInterface | virtual |
| SRE | Gicv3CPUInterface | protected |
| State | Gicv3CPUInterface | protected |
| TALL0 | Gicv3CPUInterface | protected |
| TALL1 | Gicv3CPUInterface | protected |
| TC | Gicv3CPUInterface | protected |
| TDIR | Gicv3CPUInterface | protected |
| TDS | Gicv3CPUInterface | protected |
| TSEI | Gicv3CPUInterface | protected |
| U | Gicv3CPUInterface | protected |
| UIE | Gicv3CPUInterface | protected |
| unserialize(CheckpointIn &cp) override | Gicv3CPUInterface | protectedvirtual |
| unserializeGlobals(CheckpointIn &cp) | Serializable | static |
| unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
| update() | Gicv3CPUInterface | protected |
| updateDistributor() | Gicv3CPUInterface | protected |
| VAckCtl | Gicv3CPUInterface | protected |
| VBPR0 | Gicv3CPUInterface | protected |
| VBPR1 | Gicv3CPUInterface | protected |
| VCBPR | Gicv3CPUInterface | protected |
| VENG0 | Gicv3CPUInterface | protected |
| VENG1 | Gicv3CPUInterface | protected |
| VEOIM | Gicv3CPUInterface | protected |
| VFIQEn | Gicv3CPUInterface | protected |
| VGrp0D | Gicv3CPUInterface | protected |
| VGrp0DIE | Gicv3CPUInterface | protected |
| VGrp0E | Gicv3CPUInterface | protected |
| VGrp0EIE | Gicv3CPUInterface | protected |
| VGrp1D | Gicv3CPUInterface | protected |
| VGrp1DIE | Gicv3CPUInterface | protected |
| VGrp1E | Gicv3CPUInterface | protected |
| VGrp1EIE | Gicv3CPUInterface | protected |
| vINTID | Gicv3CPUInterface | protected |
| VIRTUAL_NUM_LIST_REGS | Gicv3CPUInterface | protectedstatic |
| VIRTUAL_PREEMPTION_BITS | Gicv3CPUInterface | protectedstatic |
| VIRTUAL_PRIORITY_BITS | Gicv3CPUInterface | protectedstatic |
| virtualActivateIRQ(uint32_t lrIdx) | Gicv3CPUInterface | protected |
| virtualDeactivateIRQ(int lrIdx) | Gicv3CPUInterface | protected |
| virtualDropPriority() | Gicv3CPUInterface | protected |
| virtualFindActive(uint32_t intid) const | Gicv3CPUInterface | protected |
| virtualGroupPriorityMask(Gicv3::GroupId group) const | Gicv3CPUInterface | protected |
| virtualHighestActivePriority() const | Gicv3CPUInterface | protected |
| virtualIncrementEOICount() | Gicv3CPUInterface | protected |
| virtualIsEOISplitMode() const | Gicv3CPUInterface | protected |
| virtualUpdate() | Gicv3CPUInterface | protected |
| VPMR | Gicv3CPUInterface | protected |
| ~BaseISADevice() | ArmISA::BaseISADevice | inlinevirtual |
| ~Serializable() | Serializable | virtual |
