| _cacheLineSize | BaseCPU | protected |
| _cpuId | BaseCPU | protected |
| _dataMasterId | BaseCPU | protected |
| _instMasterId | BaseCPU | protected |
| _params | SimObject | protected |
| _pid | BaseCPU | protected |
| _socketId | BaseCPU | protected |
| _status | BaseSimpleCPU | protected |
| _switchedOut | BaseCPU | protected |
| _taskId | BaseCPU | protected |
| activateContext(ThreadID thread_num) override | TimingSimpleCPU | virtual |
| activeThreads | BaseSimpleCPU | |
| addStat(Stats::Info *info) | Stats::Group | |
| addStatGroup(const char *name, Group *block) | Stats::Group | |
| advanceInst(const Fault &fault) | TimingSimpleCPU | |
| advancePC(const Fault &fault) | BaseSimpleCPU | |
| amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) | BaseSimpleCPU | inlinevirtual |
| armMonitor(ThreadID tid, Addr address) | BaseCPU | |
| BaseCPU(Params *params, bool is_checker=false) | BaseCPU | |
| BaseSimpleCPU(BaseSimpleCPUParams *params) | BaseSimpleCPU | |
| branchPred | BaseSimpleCPU | protected |
| buildPacket(const RequestPtr &req, bool read) | TimingSimpleCPU | private |
| buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read) | TimingSimpleCPU | private |
| cacheLineSize() const | BaseCPU | inline |
| checker | BaseSimpleCPU | |
| checkForInterrupts() | BaseSimpleCPU | |
| checkInterrupts(ThreadContext *tc) const | BaseCPU | inline |
| checkPcEventQueue() | BaseSimpleCPU | protected |
| clearInterrupt(ThreadID tid, int int_num, int index) | BaseCPU | inline |
| clearInterrupts(ThreadID tid) | BaseCPU | inline |
| Clocked(ClockDomain &clk_domain) | Clocked | inlineprotected |
| Clocked(Clocked &)=delete | Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | Clocked | inline |
| ClockedObject(const ClockedObjectParams *p) | ClockedObject | |
| clockPeriod() const | Clocked | inline |
| clockPeriodUpdated() | Clocked | inlineprotectedvirtual |
| completeDataAccess(PacketPtr pkt) | TimingSimpleCPU | |
| completeIfetch(PacketPtr) | TimingSimpleCPU | |
| contextToThread(ContextID cid) | BaseCPU | inline |
| countInst() | BaseSimpleCPU | |
| CPU_STATE_ON enum value | BaseCPU | protected |
| CPU_STATE_SLEEP enum value | BaseCPU | protected |
| CPU_STATE_WAKEUP enum value | BaseCPU | protected |
| cpuId() const | BaseCPU | inline |
| CPUState enum name | BaseCPU | protected |
| curCycle() const | Clocked | inline |
| curMacroStaticInst | BaseSimpleCPU | |
| currentSection() | Serializable | static |
| curStaticInst | BaseSimpleCPU | |
| curThread | BaseSimpleCPU | protected |
| cyclesToTicks(Cycles c) const | Clocked | inline |
| dataMasterId() const | BaseCPU | inline |
| dcache_pkt | TimingSimpleCPU | private |
| dcachePort | TimingSimpleCPU | private |
| DcacheRetry enum value | BaseSimpleCPU | protected |
| DcacheWaitResponse enum value | BaseSimpleCPU | protected |
| DcacheWaitSwitch enum value | BaseSimpleCPU | protected |
| deschedule(Event &event) | EventManager | inline |
| deschedule(Event *event) | EventManager | inline |
| deschedulePowerGatingEvent() | BaseCPU | |
| drain() override | TimingSimpleCPU | virtual |
| Drainable() | Drainable | protected |
| drainResume() override | TimingSimpleCPU | virtual |
| drainState() const | Drainable | inline |
| DTBWaitResponse enum value | BaseSimpleCPU | protected |
| enterPwrGating() | BaseCPU | protected |
| enterPwrGatingEvent | BaseCPU | protected |
| EventManager(EventManager &em) | EventManager | inline |
| EventManager(EventManager *em) | EventManager | inline |
| EventManager(EventQueue *eq) | EventManager | inline |
| eventq | EventManager | protected |
| eventQueue() const | EventManager | inline |
| Faulting enum value | BaseSimpleCPU | protected |
| fetch() | TimingSimpleCPU | |
| fetchEvent | TimingSimpleCPU | private |
| fetchTranslation | TimingSimpleCPU | private |
| find(const char *name) | SimObject | static |
| findContext(ThreadContext *tc) | BaseCPU | |
| finishTranslation(WholeTranslationState *state) | TimingSimpleCPU | |
| flushTLBs() | BaseCPU | |
| frequency() const | Clocked | inline |
| getContext(int tn) | BaseCPU | inlinevirtual |
| getCpuAddrMonitor(ThreadID tid) | BaseCPU | inline |
| getCurrentInstCount(ThreadID tid) | BaseCPU | |
| getDataPort() override | TimingSimpleCPU | inlineprotectedvirtual |
| getInstPort() override | TimingSimpleCPU | inlineprotectedvirtual |
| getInterruptController(ThreadID tid) | BaseCPU | inline |
| getPid() const | BaseCPU | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | BaseCPU | virtual |
| getProbeManager() | SimObject | |
| getSendFunctional() | BaseCPU | inlinevirtual |
| getStatGroups() const | Stats::Group | |
| getStats() const | Stats::Group | |
| getTracer() | BaseCPU | inline |
| Group()=delete | Stats::Group | |
| Group(const Group &)=delete | Stats::Group | |
| Group(Group *parent, const char *name=nullptr) | Stats::Group | |
| haltContext(ThreadID thread_num) override | BaseSimpleCPU | virtual |
| handleReadPacket(PacketPtr pkt) | TimingSimpleCPU | private |
| handleWritePacket() | TimingSimpleCPU | private |
| icachePort | TimingSimpleCPU | private |
| IcacheRetry enum value | BaseSimpleCPU | protected |
| IcacheWaitResponse enum value | BaseSimpleCPU | protected |
| IcacheWaitSwitch enum value | BaseSimpleCPU | protected |
| Idle enum value | BaseSimpleCPU | protected |
| ifetch_pkt | TimingSimpleCPU | private |
| init() override | TimingSimpleCPU | virtual |
| initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override | TimingSimpleCPU | virtual |
| initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override | TimingSimpleCPU | virtual |
| initState() | SimObject | virtual |
| inst | BaseSimpleCPU | |
| instCnt | BaseCPU | protected |
| instCount() | BaseCPU | inline |
| instMasterId() const | BaseCPU | inline |
| interrupts | BaseCPU | protected |
| invldPid | BaseCPU | static |
| isCpuDrained() const | TimingSimpleCPU | inlineprivate |
| isSquashed() const | TimingSimpleCPU | inline |
| ITBWaitResponse enum value | BaseSimpleCPU | protected |
| loadState(CheckpointIn &cp) | SimObject | virtual |
| memInvalidate() | SimObject | inlinevirtual |
| memWriteback() | SimObject | inlinevirtual |
| microcodeRom | BaseCPU | |
| mwait(ThreadID tid, PacketPtr pkt) | BaseCPU | |
| mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb) | BaseCPU | |
| name() const | SimObject | inlinevirtual |
| nextCycle() const | Clocked | inline |
| notifyFork() | Drainable | inlinevirtual |
| numContexts() | BaseCPU | inline |
| numCycles | BaseCPU | |
| numSimulatedCPUs() | BaseCPU | inlinestatic |
| numSimulatedInsts() | BaseCPU | inlinestatic |
| numSimulatedInsts() | BaseCPU | inlinestatic |
| numSimulatedOps() | BaseCPU | inlinestatic |
| numSimulatedOps() | BaseCPU | inlinestatic |
| numThreads | BaseCPU | |
| numWorkItemsCompleted | BaseCPU | |
| numWorkItemsStarted | BaseCPU | |
| SimObject::operator=(const Group &)=delete | Stats::Group | |
| Clocked::operator=(Clocked &)=delete | Clocked | protected |
| params() const | BaseCPU | inline |
| Params typedef | BaseCPU | |
| PCMask | BaseCPU | static |
| pmuProbePoint(const char *name) | BaseCPU | protected |
| postExecute() | BaseSimpleCPU | |
| postInterrupt(ThreadID tid, int int_num, int index) | BaseCPU | inline |
| powerGatingOnIdle | BaseCPU | protected |
| powerState | ClockedObject | |
| ppActiveCycles | BaseCPU | protected |
| ppAllCycles | BaseCPU | protected |
| ppRetiredBranches | BaseCPU | protected |
| ppRetiredInsts | BaseCPU | protected |
| ppRetiredInstsPC | BaseCPU | protected |
| ppRetiredLoads | BaseCPU | protected |
| ppRetiredStores | BaseCPU | protected |
| ppSleeping | BaseCPU | protected |
| preDumpStats() | Stats::Group | virtual |
| preExecute() | BaseSimpleCPU | |
| previousCycle | TimingSimpleCPU | private |
| previousState | BaseCPU | protected |
| printAddr(Addr a) | TimingSimpleCPU | |
| probeInstCommit(const StaticInstPtr &inst, Addr pc) | BaseCPU | virtual |
| processProfileEvent() | BaseCPU | |
| profileEvent | BaseCPU | |
| pwrGatingLatency | BaseCPU | protected |
| readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) | BaseSimpleCPU | inlinevirtual |
| registerThreadContexts() | BaseCPU | |
| regProbeListeners() | SimObject | virtual |
| regProbePoints() override | BaseCPU | virtual |
| regStats() override | BaseSimpleCPU | virtual |
| reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
| resetClock() const | Clocked | inlineprotected |
| resetStats() override | BaseSimpleCPU | virtual |
| resolveStat(std::string name) const | Stats::Group | |
| Running enum value | BaseSimpleCPU | protected |
| schedule(Event &event, Tick when) | EventManager | inline |
| schedule(Event *event, Tick when) | EventManager | inline |
| scheduleInstStop(ThreadID tid, Counter insts, const char *cause) | BaseCPU | |
| schedulePowerGatingEvent() | BaseCPU | |
| sendData(const RequestPtr &req, uint8_t *data, uint64_t *res, bool read) | TimingSimpleCPU | private |
| sendFetch(const Fault &fault, const RequestPtr &req, ThreadContext *tc) | TimingSimpleCPU | |
| sendSplitData(const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read) | TimingSimpleCPU | private |
| Serializable() | Serializable | |
| serialize(CheckpointOut &cp) const override | BaseCPU | virtual |
| serializeAll(CheckpointOut &cp) | SimObject | static |
| Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
| serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
| serializeThread(CheckpointOut &cp, ThreadID tid) const override | BaseSimpleCPU | virtual |
| setCurTick(Tick newVal) | EventManager | inline |
| setPid(uint32_t pid) | BaseCPU | inline |
| setupFetchRequest(const RequestPtr &req) | BaseSimpleCPU | |
| signalDrainDone() const | Drainable | inlineprotected |
| SimObject(const Params *_params) | SimObject | |
| socketId() const | BaseCPU | inline |
| startup() override | BaseSimpleCPU | virtual |
| Status enum name | BaseSimpleCPU | protected |
| suspendContext(ThreadID thread_num) override | TimingSimpleCPU | virtual |
| swapActiveThread() | BaseSimpleCPU | protected |
| switchedOut() const | BaseCPU | inline |
| switchOut() override | TimingSimpleCPU | virtual |
| syscallRetryLatency | BaseCPU | |
| system | BaseCPU | |
| takeOverFrom(BaseCPU *oldCPU) override | TimingSimpleCPU | virtual |
| taskId() const | BaseCPU | inline |
| taskId(uint32_t id) | BaseCPU | inline |
| threadContexts | BaseCPU | protected |
| threadInfo | BaseSimpleCPU | |
| threadSnoop(PacketPtr pkt, ThreadID sender) | TimingSimpleCPU | private |
| ticksToCycles(Tick t) const | Clocked | inline |
| TimingSimpleCPU(TimingSimpleCPUParams *params) | TimingSimpleCPU | |
| totalInsts() const override | BaseSimpleCPU | virtual |
| totalOps() const override | BaseSimpleCPU | virtual |
| traceData | BaseSimpleCPU | |
| traceFunctions(Addr pc) | BaseCPU | inline |
| tracer | BaseCPU | protected |
| translationFault(const Fault &fault) | TimingSimpleCPU | private |
| tryCompleteDrain() | TimingSimpleCPU | private |
| unserialize(CheckpointIn &cp) override | BaseCPU | virtual |
| unserializeGlobals(CheckpointIn &cp) | Serializable | static |
| unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
| unserializeThread(CheckpointIn &cp, ThreadID tid) override | BaseSimpleCPU | virtual |
| updateClockPeriod() | Clocked | inline |
| updateCycleCounters(CPUState state) | BaseCPU | inlineprotected |
| updateCycleCounts() | TimingSimpleCPU | private |
| verifyMemoryMode() const override | TimingSimpleCPU | virtual |
| voltage() const | Clocked | inline |
| waitForRemoteGDB() const | BaseCPU | |
| wakeup(ThreadID tid) override | BaseSimpleCPU | virtual |
| wakeupEventQueue(Tick when=(Tick) -1) | EventManager | inline |
| workItemBegin() | BaseCPU | inline |
| workItemEnd() | BaseCPU | inline |
| writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >()) override | TimingSimpleCPU | virtual |
| ~BaseCPU() | BaseCPU | virtual |
| ~BaseSimpleCPU() | BaseSimpleCPU | virtual |
| ~Clocked() | Clocked | inlineprotectedvirtual |
| ~Drainable() | Drainable | protectedvirtual |
| ~Group() | Stats::Group | virtual |
| ~Serializable() | Serializable | virtual |
| ~SimObject() | SimObject | virtual |
| ~TimingSimpleCPU() | TimingSimpleCPU | virtual |
