gem5  v20.1.0.0
CacheMemory.hh
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41 
42 #ifndef __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
43 #define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
44 
45 #include <string>
46 #include <unordered_map>
47 #include <vector>
48 
49 #include "base/statistics.hh"
53 #include "mem/ruby/protocol/CacheRequestType.hh"
54 #include "mem/ruby/protocol/CacheResourceType.hh"
55 #include "mem/ruby/protocol/RubyRequest.hh"
60 #include "params/RubyCache.hh"
61 #include "sim/sim_object.hh"
62 
63 class CacheMemory : public SimObject
64 {
65  public:
66  typedef RubyCacheParams Params;
67  typedef std::shared_ptr<ReplacementData> ReplData;
68  CacheMemory(const Params *p);
69  ~CacheMemory();
70 
71  void init();
72 
73  // Public Methods
74  // perform a cache access and see if we hit or not. Return true on a hit.
75  bool tryCacheAccess(Addr address, RubyRequestType type,
76  DataBlock*& data_ptr);
77 
78  // similar to above, but doesn't require full access check
79  bool testCacheAccess(Addr address, RubyRequestType type,
80  DataBlock*& data_ptr);
81 
82  // tests to see if an address is present in the cache
83  bool isTagPresent(Addr address) const;
84 
85  // Returns true if there is:
86  // a) a tag match on this address or there is
87  // b) an unused line in the same cache "way"
88  bool cacheAvail(Addr address) const;
89 
90  // Returns a NULL entry that acts as a placeholder for invalid lines
92  getNullEntry() const
93  {
94  return nullptr;
95  }
96 
97  // find an unused entry and sets the tag appropriate for the address
98  AbstractCacheEntry* allocate(Addr address, AbstractCacheEntry* new_entry);
99  void allocateVoid(Addr address, AbstractCacheEntry* new_entry)
100  {
101  allocate(address, new_entry);
102  }
103 
104  // Explicitly free up this address
105  void deallocate(Addr address);
106 
107  // Returns with the physical address of the conflicting cache line
108  Addr cacheProbe(Addr address) const;
109 
110  // looks an address up in the cache
111  AbstractCacheEntry* lookup(Addr address);
112  const AbstractCacheEntry* lookup(Addr address) const;
113 
114  Cycles getTagLatency() const { return tagArray.getLatency(); }
116 
117  bool isBlockInvalid(int64_t cache_set, int64_t loc);
118  bool isBlockNotBusy(int64_t cache_set, int64_t loc);
119 
120  // Hook for checkpointing the contents of the cache
121  void recordCacheContents(int cntrl, CacheRecorder* tr) const;
122 
123  // Set this address to most recently used
124  void setMRU(Addr address);
125  void setMRU(Addr addr, int occupancy);
126  void setMRU(AbstractCacheEntry* entry);
127  int getReplacementWeight(int64_t set, int64_t loc);
128 
129  // Functions for locking and unlocking cache lines corresponding to the
130  // provided address. These are required for supporting atomic memory
131  // accesses. These are to be used when only the address of the cache entry
132  // is available. In case the entry itself is available. use the functions
133  // provided by the AbstractCacheEntry class.
134  void setLocked (Addr addr, int context);
135  void clearLocked (Addr addr);
136  void clearLockedAll (int context);
137  bool isLocked (Addr addr, int context);
138 
139  // Print cache contents
140  void print(std::ostream& out) const;
141  void printData(std::ostream& out) const;
142 
143  void regStats();
144  bool checkResourceAvailable(CacheResourceType res, Addr addr);
145  void recordRequestType(CacheRequestType requestType, Addr addr);
146 
147  // hardware transactional memory
148  void htmAbortTransaction();
149  void htmCommitTransaction();
150 
151  public:
155 
159 
161 
166 
169 
170  // hardware transactional memory
175 
176  int getCacheSize() const { return m_cache_size; }
177  int getCacheAssoc() const { return m_cache_assoc; }
178  int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
179  Addr getAddressAtIdx(int idx) const;
180 
181  private:
182  // convert a Address to its location in the cache
183  int64_t addressToCacheSet(Addr address) const;
184 
185  // Given a cache tag: returns the index of the tag in a set.
186  // returns -1 if the tag is not found.
187  int findTagInSet(int64_t line, Addr tag) const;
188  int findTagInSetIgnorePermissions(int64_t cacheSet, Addr tag) const;
189 
190  // Private copy constructor and assignment operator
191  CacheMemory(const CacheMemory& obj);
192  CacheMemory& operator=(const CacheMemory& obj);
193 
194  private:
195  // Data Members (m_prefix)
197 
198  // The first index is the # of cache lines.
199  // The second index is the the amount associativity.
200  std::unordered_map<Addr, int> m_tag_index;
202 
208 
211 
219 
229 
235 };
236 
237 std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
238 
239 #endif // __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
CacheMemory::recordCacheContents
void recordCacheContents(int cntrl, CacheRecorder *tr) const
Definition: CacheMemory.cc:414
AbstractCacheEntry
Definition: AbstractCacheEntry.hh:57
CacheMemory::findTagInSetIgnorePermissions
int findTagInSetIgnorePermissions(int64_t cacheSet, Addr tag) const
Definition: CacheMemory.cc:151
CacheMemory::m_cache_size
int m_cache_size
Definition: CacheMemory.hh:212
CacheMemory::Params
RubyCacheParams Params
Definition: CacheMemory.hh:66
CacheMemory::m_prefetches
Stats::Formula m_prefetches
Definition: CacheMemory.hh:158
CacheRecorder
Definition: CacheRecorder.hh:66
CacheMemory::m_hw_prefetches
Stats::Scalar m_hw_prefetches
Definition: CacheMemory.hh:157
CacheMemory::clearLocked
void clearLocked(Addr addr)
Definition: CacheMemory.cc:487
CacheMemory::lookup
AbstractCacheEntry * lookup(Addr address)
Definition: CacheMemory.cc:342
CacheMemory::tagArray
BankedArray tagArray
Definition: CacheMemory.hh:210
CacheMemory::isLocked
bool isLocked(Addr addr, int context)
Definition: CacheMemory.cc:513
CacheMemory::m_cache
std::vector< std::vector< AbstractCacheEntry * > > m_cache
Definition: CacheMemory.hh:201
CacheMemory::dataArray
BankedArray dataArray
Definition: CacheMemory.hh:209
CacheMemory::allocateVoid
void allocateVoid(Addr address, AbstractCacheEntry *new_entry)
Definition: CacheMemory.hh:99
CacheMemory::m_demand_misses
Stats::Scalar m_demand_misses
Definition: CacheMemory.hh:153
BankedArray::getLatency
Cycles getLatency() const
Definition: BankedArray.hh:75
CacheMemory::cacheProbe
Addr cacheProbe(Addr address) const
Definition: CacheMemory.cc:325
type
uint8_t type
Definition: inet.hh:421
CacheMemory::regStats
void regStats()
Callback to set stat parameters.
Definition: CacheMemory.cc:523
CacheMemory::~CacheMemory
~CacheMemory()
Definition: CacheMemory.cc:113
CacheMemory::m_replacementPolicy_ptr
BaseReplacementPolicy * m_replacementPolicy_ptr
We use BaseReplacementPolicy from Classic system here, hence we can use different replacement policie...
Definition: CacheMemory.hh:207
CacheMemory::htmTransCommitWriteSet
Stats::Histogram htmTransCommitWriteSet
Definition: CacheMemory.hh:172
std::vector
STL vector class.
Definition: stl.hh:37
CacheMemory::m_tag_index
std::unordered_map< Addr, int > m_tag_index
Definition: CacheMemory.hh:200
CacheMemory::m_cache_num_set_bits
int m_cache_num_set_bits
Definition: CacheMemory.hh:214
BankedArray.hh
CacheMemory::print
void print(std::ostream &out) const
Definition: CacheMemory.cc:453
Stats::Vector
A vector of scalar stats.
Definition: statistics.hh:2575
CacheMemory::setMRU
void setMRU(Addr address)
Definition: CacheMemory.cc:364
AbstractCacheEntry.hh
CacheMemory::deallocate
void deallocate(Addr address)
Definition: CacheMemory.cc:310
CacheMemory::testCacheAccess
bool testCacheAccess(Addr address, RubyRequestType type, DataBlock *&data_ptr)
Definition: CacheMemory.cc:211
CacheMemory::getTagLatency
Cycles getTagLatency() const
Definition: CacheMemory.hh:114
CacheMemory::m_use_occupancy
bool m_use_occupancy
Set to true when using WeightedLRU replacement policy, otherwise, set to false.
Definition: CacheMemory.hh:234
BankedArray
Definition: BankedArray.hh:41
DataBlock
Definition: DataBlock.hh:40
Stats::Histogram
A simple histogram stat.
Definition: statistics.hh:2654
replaceable_entry.hh
CacheMemory::getCacheAssoc
int getCacheAssoc() const
Definition: CacheMemory.hh:177
Stats::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:2533
CacheMemory::ReplData
std::shared_ptr< ReplacementData > ReplData
Definition: CacheMemory.hh:67
CacheMemory::allocate
AbstractCacheEntry * allocate(Addr address, AbstractCacheEntry *new_entry)
Definition: CacheMemory.cc:269
CacheMemory::init
void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: CacheMemory.cc:90
CacheMemory::m_demand_hits
Stats::Scalar m_demand_hits
Definition: CacheMemory.hh:152
CacheMemory::replacement_data
std::vector< std::vector< ReplData > > replacement_data
We store all the ReplacementData in a 2-dimensional array.
Definition: CacheMemory.hh:228
CacheMemory::numTagArrayStalls
Stats::Scalar numTagArrayStalls
Definition: CacheMemory.hh:167
sim_object.hh
BaseReplacementPolicy
A common base class of cache replacement policy objects.
Definition: base.hh:46
CacheMemory::printData
void printData(std::ostream &out) const
Definition: CacheMemory.cc:472
DataBlock.hh
statistics.hh
CacheMemory::cacheAvail
bool cacheAvail(Addr address) const
Definition: CacheMemory.cc:247
CacheMemory::CacheMemory
CacheMemory(const Params *p)
Definition: CacheMemory.cc:71
CacheMemory::getNullEntry
AbstractCacheEntry * getNullEntry() const
Definition: CacheMemory.hh:92
CacheMemory
Definition: CacheMemory.hh:63
CacheMemory::operator=
CacheMemory & operator=(const CacheMemory &obj)
CacheMemory::m_cache_assoc
int m_cache_assoc
Definition: CacheMemory.hh:215
CacheMemory::isBlockInvalid
bool isBlockInvalid(int64_t cache_set, int64_t loc)
Definition: CacheMemory.cc:706
base.hh
CacheMemory::m_block_size
int m_block_size
Definition: CacheMemory.hh:218
CacheMemory::m_sw_prefetches
Stats::Scalar m_sw_prefetches
Definition: CacheMemory.hh:156
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
CacheMemory::findTagInSet
int findTagInSet(int64_t line, Addr tag) const
Definition: CacheMemory.cc:136
CacheMemory::clearLockedAll
void clearLockedAll(int context)
Definition: CacheMemory.cc:496
RubySlicc_ComponentMapping.hh
CacheMemory::m_start_index_bit
int m_start_index_bit
Definition: CacheMemory.hh:216
CacheMemory::getDataLatency
Cycles getDataLatency() const
Definition: CacheMemory.hh:115
operator<<
std::ostream & operator<<(std::ostream &out, const CacheMemory &obj)
CacheMemory::tryCacheAccess
bool tryCacheAccess(Addr address, RubyRequestType type, DataBlock *&data_ptr)
Definition: CacheMemory.cc:186
CacheMemory::htmCommitTransaction
void htmCommitTransaction()
Definition: CacheMemory.cc:754
CacheMemory::setLocked
void setLocked(Addr addr, int context)
Definition: CacheMemory.cc:478
CacheMemory::htmTransAbortWriteSet
Stats::Histogram htmTransAbortWriteSet
Definition: CacheMemory.hh:174
CacheMemory::isTagPresent
bool isTagPresent(Addr address) const
Definition: CacheMemory.cc:231
Stats::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:3037
CacheMemory::numDataArrayWrites
Stats::Scalar numDataArrayWrites
Definition: CacheMemory.hh:163
addr
ip6_addr_t addr
Definition: inet.hh:423
CacheMemory::getAddressAtIdx
Addr getAddressAtIdx(int idx) const
Definition: CacheMemory.cc:166
CacheMemory::numDataArrayReads
Stats::Scalar numDataArrayReads
Definition: CacheMemory.hh:162
Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
CacheMemory::m_is_instruction_only_cache
bool m_is_instruction_only_cache
Definition: CacheMemory.hh:196
CacheMemory::addressToCacheSet
int64_t addressToCacheSet(Addr address) const
Definition: CacheMemory.cc:126
CacheMemory::getCacheSize
int getCacheSize() const
Definition: CacheMemory.hh:176
CacheMemory::htmTransCommitReadSet
Stats::Histogram htmTransCommitReadSet
Definition: CacheMemory.hh:171
CacheMemory::checkResourceAvailable
bool checkResourceAvailable(CacheResourceType res, Addr addr)
Definition: CacheMemory.cc:676
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
CacheRecorder.hh
CacheMemory::recordRequestType
void recordRequestType(CacheRequestType requestType, Addr addr)
Definition: CacheMemory.cc:644
CacheMemory::htmAbortTransaction
void htmAbortTransaction()
Definition: CacheMemory.cc:720
CacheMemory::getReplacementWeight
int getReplacementWeight(int64_t set, int64_t loc)
Definition: CacheMemory.cc:400
CacheMemory::m_cache_num_sets
int m_cache_num_sets
Definition: CacheMemory.hh:213
CacheMemory::numTagArrayWrites
Stats::Scalar numTagArrayWrites
Definition: CacheMemory.hh:165
CacheMemory::numTagArrayReads
Stats::Scalar numTagArrayReads
Definition: CacheMemory.hh:164
CacheMemory::m_demand_accesses
Stats::Formula m_demand_accesses
Definition: CacheMemory.hh:154
CacheMemory::numDataArrayStalls
Stats::Scalar numDataArrayStalls
Definition: CacheMemory.hh:168
CacheMemory::htmTransAbortReadSet
Stats::Histogram htmTransAbortReadSet
Definition: CacheMemory.hh:173
CacheMemory::getNumBlocks
int getNumBlocks() const
Definition: CacheMemory.hh:178
CacheMemory::m_resource_stalls
bool m_resource_stalls
Definition: CacheMemory.hh:217
CacheMemory::m_accessModeType
Stats::Vector m_accessModeType
Definition: CacheMemory.hh:160
CacheMemory::isBlockNotBusy
bool isBlockNotBusy(int64_t cache_set, int64_t loc)
Definition: CacheMemory.cc:712
SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:92

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