gem5  v20.1.0.0
PerfectCacheMemory.hh
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40 
41 #ifndef __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
42 #define __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
43 
44 #include <unordered_map>
45 
47 #include "mem/ruby/protocol/AccessPermission.hh"
48 
49 template<class ENTRY>
51 {
52  PerfectCacheLineState() { m_permission = AccessPermission_NUM; }
53  AccessPermission m_permission;
54  ENTRY m_entry;
55 };
56 
57 template<class ENTRY>
58 inline std::ostream&
59 operator<<(std::ostream& out, const PerfectCacheLineState<ENTRY>& obj)
60 {
61  return out;
62 }
63 
64 template<class ENTRY>
66 {
67  public:
69 
70  // tests to see if an address is present in the cache
71  bool isTagPresent(Addr address) const;
72 
73  // Returns true if there is:
74  // a) a tag match on this address or there is
75  // b) an Invalid line in the same cache "way"
76  bool cacheAvail(Addr address) const;
77 
78  // find an Invalid entry and sets the tag appropriate for the address
79  void allocate(Addr address);
80 
81  void deallocate(Addr address);
82 
83  // Returns with the physical address of the conflicting cache line
84  Addr cacheProbe(Addr newAddress) const;
85 
86  // looks an address up in the cache
87  ENTRY* lookup(Addr address);
88  const ENTRY* lookup(Addr address) const;
89 
90  // Get/Set permission of cache block
91  AccessPermission getPermission(Addr address) const;
92  void changePermission(Addr address, AccessPermission new_perm);
93 
94  // Print cache contents
95  void print(std::ostream& out) const;
96 
97  private:
98  // Private copy constructor and assignment operator
101 
102  // Data Members (m_prefix)
103  std::unordered_map<Addr, PerfectCacheLineState<ENTRY> > m_map;
104 };
105 
106 template<class ENTRY>
107 inline std::ostream&
108 operator<<(std::ostream& out, const PerfectCacheMemory<ENTRY>& obj)
109 {
110  obj.print(out);
111  out << std::flush;
112  return out;
113 }
114 
115 template<class ENTRY>
116 inline
118 {
119 }
120 
121 // tests to see if an address is present in the cache
122 template<class ENTRY>
123 inline bool
125 {
126  return m_map.count(makeLineAddress(address)) > 0;
127 }
128 
129 template<class ENTRY>
130 inline bool
132 {
133  return true;
134 }
135 
136 // find an Invalid or already allocated entry and sets the tag
137 // appropriate for the address
138 template<class ENTRY>
139 inline void
141 {
142  PerfectCacheLineState<ENTRY> line_state;
143  line_state.m_permission = AccessPermission_Invalid;
144  line_state.m_entry = ENTRY();
145  m_map[makeLineAddress(address)] = line_state;
146 }
147 
148 // deallocate entry
149 template<class ENTRY>
150 inline void
152 {
153  auto num_erased M5_VAR_USED = m_map.erase(makeLineAddress(address));
154  assert(num_erased == 1);
155 }
156 
157 // Returns with the physical address of the conflicting cache line
158 template<class ENTRY>
159 inline Addr
161 {
162  panic("cacheProbe called in perfect cache");
163  return newAddress;
164 }
165 
166 // looks an address up in the cache
167 template<class ENTRY>
168 inline ENTRY*
170 {
171  return &m_map[makeLineAddress(address)].m_entry;
172 }
173 
174 // looks an address up in the cache
175 template<class ENTRY>
176 inline const ENTRY*
178 {
179  return &m_map[makeLineAddress(address)].m_entry;
180 }
181 
182 template<class ENTRY>
183 inline AccessPermission
185 {
186  return m_map[makeLineAddress(address)].m_permission;
187 }
188 
189 template<class ENTRY>
190 inline void
192  AccessPermission new_perm)
193 {
194  Addr line_address = makeLineAddress(address);
195  PerfectCacheLineState<ENTRY>& line_state = m_map[line_address];
196  line_state.m_permission = new_perm;
197 }
198 
199 template<class ENTRY>
200 inline void
201 PerfectCacheMemory<ENTRY>::print(std::ostream& out) const
202 {
203 }
204 
205 #endif // __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
PerfectCacheLineState
Definition: PerfectCacheMemory.hh:50
PerfectCacheMemory::print
void print(std::ostream &out) const
Definition: PerfectCacheMemory.hh:201
PerfectCacheMemory::isTagPresent
bool isTagPresent(Addr address) const
Definition: PerfectCacheMemory.hh:124
makeLineAddress
Addr makeLineAddress(Addr addr)
Definition: Address.cc:54
PerfectCacheMemory::cacheAvail
bool cacheAvail(Addr address) const
Definition: PerfectCacheMemory.hh:131
PerfectCacheMemory::cacheProbe
Addr cacheProbe(Addr newAddress) const
Definition: PerfectCacheMemory.hh:160
PerfectCacheMemory::deallocate
void deallocate(Addr address)
Definition: PerfectCacheMemory.hh:151
PerfectCacheMemory::getPermission
AccessPermission getPermission(Addr address) const
Definition: PerfectCacheMemory.hh:184
PerfectCacheLineState::m_entry
ENTRY m_entry
Definition: PerfectCacheMemory.hh:54
PerfectCacheMemory::allocate
void allocate(Addr address)
Definition: PerfectCacheMemory.hh:140
PerfectCacheMemory::lookup
ENTRY * lookup(Addr address)
Definition: PerfectCacheMemory.hh:169
PerfectCacheMemory::m_map
std::unordered_map< Addr, PerfectCacheLineState< ENTRY > > m_map
Definition: PerfectCacheMemory.hh:103
PerfectCacheMemory::PerfectCacheMemory
PerfectCacheMemory()
Definition: PerfectCacheMemory.hh:117
operator<<
std::ostream & operator<<(std::ostream &out, const PerfectCacheLineState< ENTRY > &obj)
Definition: PerfectCacheMemory.hh:59
PerfectCacheMemory
Definition: PerfectCacheMemory.hh:65
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
PerfectCacheMemory::operator=
PerfectCacheMemory & operator=(const PerfectCacheMemory &obj)
PerfectCacheMemory::changePermission
void changePermission(Addr address, AccessPermission new_perm)
Definition: PerfectCacheMemory.hh:191
Address.hh
PerfectCacheLineState::m_permission
AccessPermission m_permission
Definition: PerfectCacheMemory.hh:53
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
PerfectCacheLineState::PerfectCacheLineState
PerfectCacheLineState()
Definition: PerfectCacheMemory.hh:52

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