gem5
v20.1.0.0
systemc
tests
systemc
misc
examples
a2901
a2901_edge.h
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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a2901_edge.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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#ifndef A2901_EDGE_H
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#define A2901_EDGE_H
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#include "
common.h
"
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SC_MODULE
( a2901_edge )
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{
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SC_HAS_PROCESS
( a2901_edge );
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// clock
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const
sc_clock& CLK;
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// shared state
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long
* RAM;
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// inputs
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const
sig9
& I;
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const
sig4
& Badd;
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const
sig4
& F;
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const
sig1
& Q3;
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const
sig1
& Q0;
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const
sig1
& RAM3;
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const
sig1
& RAM0;
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// outputs
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sig4
& Q;
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// temporaries
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sc_uint<3> i86;
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sc_uint<3> i87;
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sc_uint<3> q31, q20;
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sc_uint<3> f31, f20;
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// constructor
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a2901_edge( sc_module_name,
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const
sc_clock& CLK_,
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long
* RAM_,
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const
sig9
&
I_
,
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const
sig4
& Badd_,
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const
sig4
& F_,
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const
sig1
& Q3_,
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const
sig1
& Q0_,
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const
sig1
& RAM3_,
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const
sig1
& RAM0_,
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sig4
& Q_ )
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: CLK( CLK_ ),
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RAM( RAM_ ),
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I(
I_
),
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Badd( Badd_ ),
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F( F_ ),
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Q3( Q3_ ),
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Q0( Q0_ ),
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RAM3( RAM3_ ),
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RAM0( RAM0_ ),
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Q( Q_ )
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{
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SC_METHOD
( entry );
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sensitive << CLK.posedge_event();
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}
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void
entry();
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};
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#endif
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sig4
sc_signal< int4 > sig4
Definition:
common.h:49
I_
@ I_
Definition:
CommonTypes.hh:42
sig1
sc_signal< int1 > sig1
Definition:
common.h:48
SC_MODULE
SC_MODULE(a2901_edge)
Definition:
a2901_edge.h:43
SC_METHOD
#define SC_METHOD(name)
Definition:
sc_module.hh:299
sig9
sc_signal< int9 > sig9
Definition:
common.h:51
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition:
sc_module.hh:297
common.h
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