| _cacheLineSize | ComputeUnit | private |
| _drainManager | Drainable | private |
| _drainState | Drainable | mutableprivate |
| _numBarrierSlots | ComputeUnit | private |
| _params | SimObject | protected |
| _requestorId | ComputeUnit | protected |
| activeLanesPerGMemInstrDist | ComputeUnit | |
| activeLanesPerLMemInstrDist | ComputeUnit | |
| activeWaves | ComputeUnit | |
| addStat(Stats::Info *info) | Stats::Group | |
| addStatGroup(const char *name, Group *block) | Stats::Group | |
| allAtBarrier(int bar_id) | ComputeUnit | |
| argMemInsts | ComputeUnit | |
| argReads | ComputeUnit | |
| argWrites | ComputeUnit | |
| barrierSlot(int bar_id) | ComputeUnit | inlineprivate |
| cacheLineBits | ComputeUnit | private |
| cacheLineSize() const | ComputeUnit | inline |
| clockDomain | Clocked | private |
| Clocked(ClockDomain &clk_domain) | Clocked | inlineprotected |
| Clocked(Clocked &)=delete | Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | Clocked | inline |
| ClockedObject(const ClockedObjectParams *p) | ClockedObject | |
| clockPeriod() const | Clocked | inline |
| clockPeriodUpdated() | Clocked | inlineprotectedvirtual |
| coalescerToVrfBusWidth | ComputeUnit | |
| completedWfs | ComputeUnit | |
| completedWGs | ComputeUnit | |
| ComputeUnit(const Params *p) | ComputeUnit | |
| controlFlowDivergenceDist | ComputeUnit | |
| countPages | ComputeUnit | |
| cu_id | ComputeUnit | |
| curCycle() const | Clocked | inline |
| currentSection() | Serializable | static |
| cycle | Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | Clocked | inline |
| debugSegFault | ComputeUnit | |
| decMaxBarrierCnt(int bar_id) | ComputeUnit | |
| deleteFromPipeMap(Wavefront *w) | ComputeUnit | |
| deschedule(Event &event) | EventManager | inline |
| deschedule(Event *event) | EventManager | inline |
| dispWorkgroup(HSAQueueEntry *task, int num_wfs_in_wg) | ComputeUnit | |
| dmDrain() | Drainable | private |
| dmDrainResume() | Drainable | private |
| doFlush(GPUDynInstPtr gpuDynInst) | ComputeUnit | |
| doInvalidate(RequestPtr req, int kernId) | ComputeUnit | |
| doSmReturn(GPUDynInstPtr gpuDynInst) | ComputeUnit | |
| dpBypassLength() const | ComputeUnit | inline |
| dpBypassPipeLength | ComputeUnit | |
| drain() override | SimObject | inlinevirtual |
| Drainable() | Drainable | protected |
| drainResume() | Drainable | inlineprotectedvirtual |
| drainState() const | Drainable | inline |
| dynamicFlatMemInstrCnt | ComputeUnit | |
| dynamicGMemInstrCnt | ComputeUnit | |
| dynamicLMemInstrCnt | ComputeUnit | |
| EventManager(EventManager &em) | EventManager | inline |
| EventManager(EventManager *em) | EventManager | inline |
| EventManager(EventQueue *eq) | EventManager | inline |
| eventq | EventManager | protected |
| eventQueue() const | EventManager | inline |
| exec() | ComputeUnit | |
| exec_policy | ComputeUnit | |
| execRateDist | ComputeUnit | |
| execStage | ComputeUnit | |
| exitCallback() | ComputeUnit | |
| fetch(PacketPtr pkt, Wavefront *wavefront) | ComputeUnit | |
| fetchStage | ComputeUnit | |
| fillKernelState(Wavefront *w, HSAQueueEntry *task) | ComputeUnit | |
| find(const char *name) | SimObject | static |
| firstMemUnit() const | ComputeUnit | |
| flatLDSInsts | ComputeUnit | |
| flatLDSInstsPerWF | ComputeUnit | |
| flatVMemInsts | ComputeUnit | |
| flatVMemInstsPerWF | ComputeUnit | |
| freeBarrierIds | ComputeUnit | private |
| frequency() const | Clocked | inline |
| functionalTLB | ComputeUnit | |
| getAndIncSeqNum() | ComputeUnit | inline |
| getCacheLineBits() const | ComputeUnit | inline |
| getFreeBarrierId() | ComputeUnit | inlineprivate |
| getLds() const | ComputeUnit | inline |
| getPort(const std::string &if_name, PortID idx) override | ComputeUnit | inlinevirtual |
| getProbeManager() | SimObject | |
| getRefCounter(const uint32_t dispatchId, const uint32_t wgId) const | ComputeUnit | |
| getStatGroups() const | Stats::Group | |
| getStats() const | Stats::Group | |
| getTokenManager() | ComputeUnit | inline |
| glbMemToVrfBus | ComputeUnit | |
| globalMemInsts | ComputeUnit | |
| globalMemoryPipe | ComputeUnit | |
| globalReads | ComputeUnit | |
| globalSeqNum | ComputeUnit | private |
| globalWrites | ComputeUnit | |
| gmTokenPort | ComputeUnit | |
| Group()=delete | Stats::Group | |
| Group(const Group &)=delete | Stats::Group | |
| Group(Group *parent, const char *name=nullptr) | Stats::Group | |
| groupMemInsts | ComputeUnit | |
| groupReads | ComputeUnit | |
| groupWrites | ComputeUnit | |
| handleMemPacket(PacketPtr pkt, int memport_index) | ComputeUnit | |
| hasDispResources(HSAQueueEntry *task, int &num_wfs_in_wg) | ComputeUnit | |
| headTailLatency | ComputeUnit | |
| headTailMap | ComputeUnit | private |
| hitsPerTLBLevel | ComputeUnit | |
| idleCUTimeout | ComputeUnit | |
| idleWfs | ComputeUnit | |
| incNumAtBarrier(int bar_id) | ComputeUnit | |
| init() override | ComputeUnit | virtual |
| initiateFetch(Wavefront *wavefront) | ComputeUnit | |
| initState() | SimObject | virtual |
| injectGlobalMemFence(GPUDynInstPtr gpuDynInst, bool kernelMemSync, RequestPtr req=nullptr) | ComputeUnit | |
| insertInPipeMap(Wavefront *w) | ComputeUnit | |
| instCyclesLdsPerSimd | ComputeUnit | |
| instCyclesSALU | ComputeUnit | |
| instCyclesScMemPerSimd | ComputeUnit | |
| instCyclesVALU | ComputeUnit | |
| instCyclesVMemPerSimd | ComputeUnit | |
| instExecPerSimd | ComputeUnit | |
| instInterleave | ComputeUnit | |
| ipc | ComputeUnit | |
| isDone() const | ComputeUnit | |
| issuePeriod | ComputeUnit | |
| isVectorAluIdle(uint32_t simdId) const | ComputeUnit | |
| kernargMemInsts | ComputeUnit | |
| kernargReads | ComputeUnit | |
| kernargWrites | ComputeUnit | |
| lastExecCycle | ComputeUnit | |
| lastMemUnit() const | ComputeUnit | |
| lastVaddrCU | ComputeUnit | |
| lastVaddrSimd | ComputeUnit | |
| lastVaddrWF | ComputeUnit | |
| lds | ComputeUnit | protected |
| ldsBankAccesses | ComputeUnit | |
| ldsBankConflictDist | ComputeUnit | |
| ldsNoFlatInsts | ComputeUnit | |
| ldsNoFlatInstsPerWF | ComputeUnit | |
| ldsPort | ComputeUnit | |
| loadBusLength() const | ComputeUnit | inline |
| loadState(CheckpointIn &cp) | SimObject | virtual |
| localMemBarrier | ComputeUnit | |
| localMemoryPipe | ComputeUnit | |
| locMemToVrfBus | ComputeUnit | |
| mapWaveToGlobalMem(Wavefront *w) const | ComputeUnit | |
| mapWaveToLocalMem(Wavefront *w) const | ComputeUnit | |
| mapWaveToScalarAlu(Wavefront *w) const | ComputeUnit | |
| mapWaveToScalarAluGlobalIdx(Wavefront *w) const | ComputeUnit | |
| mapWaveToScalarMem(Wavefront *w) const | ComputeUnit | |
| maxBarrierCnt(int bar_id) | ComputeUnit | |
| memInvalidate() | SimObject | inlinevirtual |
| memPort | ComputeUnit | |
| memPortTokens | ComputeUnit | |
| memWriteback() | SimObject | inlinevirtual |
| mergedParent | Stats::Group | private |
| mergedStatGroups | Stats::Group | private |
| mergeStatGroup(Group *block) | Stats::Group | private |
| name() const | SimObject | inlinevirtual |
| nextCycle() const | Clocked | inline |
| notifyFork() | Drainable | inlinevirtual |
| numALUInstsExecuted | ComputeUnit | |
| numAtBarrier(int bar_id) | ComputeUnit | |
| numBarrierSlots() const | ComputeUnit | inline |
| numCASOps | ComputeUnit | |
| numCyclesPerLoadTransfer | ComputeUnit | |
| numCyclesPerStoreTransfer | ComputeUnit | |
| numExeUnits() const | ComputeUnit | |
| numFailedCASOps | ComputeUnit | |
| numInstrExecuted | ComputeUnit | |
| numScalarALUs | ComputeUnit | |
| numScalarMemUnits | ComputeUnit | |
| numScalarRegsPerSimd | ComputeUnit | |
| numTimesWgBlockedDueSgprAlloc | ComputeUnit | |
| numTimesWgBlockedDueVgprAlloc | ComputeUnit | |
| numVecOpsExecuted | ComputeUnit | |
| numVecOpsExecutedF16 | ComputeUnit | |
| numVecOpsExecutedF32 | ComputeUnit | |
| numVecOpsExecutedF64 | ComputeUnit | |
| numVecOpsExecutedFMA16 | ComputeUnit | |
| numVecOpsExecutedFMA32 | ComputeUnit | |
| numVecOpsExecutedFMA64 | ComputeUnit | |
| numVecOpsExecutedMAC16 | ComputeUnit | |
| numVecOpsExecutedMAC32 | ComputeUnit | |
| numVecOpsExecutedMAC64 | ComputeUnit | |
| numVecOpsExecutedMAD16 | ComputeUnit | |
| numVecOpsExecutedMAD32 | ComputeUnit | |
| numVecOpsExecutedMAD64 | ComputeUnit | |
| numVecOpsExecutedTwoOpFP | ComputeUnit | |
| numVecRegsPerSimd | ComputeUnit | |
| numVectorALUs | ComputeUnit | |
| numVectorGlobalMemUnits | ComputeUnit | |
| numVectorSharedMemUnits | ComputeUnit | |
| numWfsToSched | ComputeUnit | |
| numYetToReachBarrier(int bar_id) | ComputeUnit | |
| operandNetworkLength | ComputeUnit | |
| SimObject::operator=(const Group &)=delete | Stats::Group | |
| Clocked::operator=(Clocked &)=delete | Clocked | protected |
| oprNetPipeLength() const | ComputeUnit | inline |
| pageAccesses | ComputeUnit | |
| pageDataStruct typedef | ComputeUnit | |
| pageDivergenceDist | ComputeUnit | |
| pagesTouched | ComputeUnit | |
| params() const | ClockedObject | inline |
| Params typedef | ComputeUnit | |
| path | Serializable | privatestatic |
| perLaneTLB | ComputeUnit | |
| pipeMap | ComputeUnit | |
| powerState | ClockedObject | |
| preDumpStats() | Stats::Group | virtual |
| prefetchDepth | ComputeUnit | |
| prefetchStride | ComputeUnit | |
| prefetchType | ComputeUnit | |
| privMemInsts | ComputeUnit | |
| privReads | ComputeUnit | |
| privWrites | ComputeUnit | |
| probeManager | SimObject | private |
| processFetchReturn(PacketPtr pkt) | ComputeUnit | |
| processTimingPacket(PacketPtr pkt) | ComputeUnit | |
| readonlyMemInsts | ComputeUnit | |
| readonlyReads | ComputeUnit | |
| readonlyWrites | ComputeUnit | |
| registerManager | ComputeUnit | |
| regProbeListeners() | SimObject | virtual |
| regProbePoints() | SimObject | virtual |
| regStats() override | ComputeUnit | virtual |
| releaseBarrier(int bar_id) | ComputeUnit | |
| releaseWFsFromBarrier(int bar_id) | ComputeUnit | |
| req_tick_latency | ComputeUnit | |
| requestorId() | ComputeUnit | inline |
| reschedule(Event &event, Tick when, bool always=false) | EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | EventManager | inline |
| resetBarrier(int bar_id) | ComputeUnit | |
| resetClock() const | Clocked | inlineprotected |
| resetStats() | Stats::Group | virtual |
| resolveStat(std::string name) const | Stats::Group | |
| resp_tick_latency | ComputeUnit | |
| sALUInsts | ComputeUnit | |
| sALUInstsPerWF | ComputeUnit | |
| scalarALUs | ComputeUnit | |
| scalarDataPort | ComputeUnit | |
| scalarDTLBPort | ComputeUnit | |
| scalarMemInstsPerKiloInst | ComputeUnit | |
| scalarMemoryPipe | ComputeUnit | |
| scalarMemReads | ComputeUnit | |
| scalarMemReadsPerKiloInst | ComputeUnit | |
| scalarMemReadsPerWF | ComputeUnit | |
| scalarMemToSrfBus | ComputeUnit | |
| scalarMemUnit | ComputeUnit | |
| scalarMemWrites | ComputeUnit | |
| scalarMemWritesPerKiloInst | ComputeUnit | |
| scalarMemWritesPerWF | ComputeUnit | |
| scalarPipeLength() const | ComputeUnit | inline |
| scalarPipeStages | ComputeUnit | |
| scalarRegsReserved | ComputeUnit | |
| schedule(Event &event, Tick when) | EventManager | inline |
| schedule(Event *event, Tick when) | EventManager | inline |
| scheduleStage | ComputeUnit | |
| scheduleToExecute | ComputeUnit | private |
| scoreboardCheckStage | ComputeUnit | |
| scoreboardCheckToSchedule | ComputeUnit | private |
| sendRequest(GPUDynInstPtr gpuDynInst, PortID index, PacketPtr pkt) | ComputeUnit | |
| sendScalarRequest(GPUDynInstPtr gpuDynInst, PacketPtr pkt) | ComputeUnit | |
| sendToLds(GPUDynInstPtr gpuDynInst) __attribute__((warn_unused_result)) | ComputeUnit | |
| Serializable() | Serializable | |
| serialize(CheckpointOut &cp) const override | ClockedObject | virtual |
| serializeAll(CheckpointOut &cp) | SimObject | static |
| Serializable::serializeAll(const std::string &cpt_dir) | Serializable | static |
| serializeSection(CheckpointOut &cp, const char *name) const | Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | Serializable | inline |
| setCurTick(Tick newVal) | EventManager | inline |
| shader | ComputeUnit | |
| signalDrainDone() const | Drainable | inlineprotected |
| simdUnitWidth() const | ComputeUnit | inline |
| simdWidth | ComputeUnit | |
| SimObject(const Params *_params) | SimObject | |
| simObjectList | SimObject | privatestatic |
| SimObjectList typedef | SimObject | private |
| spBypassLength() const | ComputeUnit | inline |
| spBypassPipeLength | ComputeUnit | |
| spillMemInsts | ComputeUnit | |
| spillReads | ComputeUnit | |
| spillWrites | ComputeUnit | |
| sqcPort | ComputeUnit | |
| sqcTLBPort | ComputeUnit | |
| srf | ComputeUnit | |
| srf_scm_bus_latency | ComputeUnit | |
| srfToScalarMemPipeBus | ComputeUnit | |
| startup() | SimObject | virtual |
| startWavefront(Wavefront *w, int waveId, LdsChunk *ldsChunk, HSAQueueEntry *task, int bar_id, bool fetchContext=false) | ComputeUnit | |
| statGroups | Stats::Group | private |
| stats | Stats::Group | private |
| storeBusLength() const | ComputeUnit | inline |
| threadCyclesVALU | ComputeUnit | |
| tick | Clocked | mutableprivate |
| tickEvent | ComputeUnit | |
| ticksToCycles(Tick t) const | Clocked | inline |
| tlbCycles | ComputeUnit | |
| tlbLatency | ComputeUnit | |
| tlbPort | ComputeUnit | |
| tlbRequests | ComputeUnit | |
| totalCycles | ComputeUnit | |
| unserialize(CheckpointIn &cp) override | ClockedObject | virtual |
| unserializeGlobals(CheckpointIn &cp) | Serializable | static |
| unserializeSection(CheckpointIn &cp, const char *name) | Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | Serializable | inline |
| update() const | Clocked | inlineprivate |
| updateClockPeriod() | Clocked | inline |
| updateInstStats(GPUDynInstPtr gpuDynInst) | ComputeUnit | |
| updatePageDivergenceDist(Addr addr) | ComputeUnit | |
| vALUInsts | ComputeUnit | |
| vALUInstsPerWF | ComputeUnit | |
| vALUUtilization | ComputeUnit | |
| vectorALUs | ComputeUnit | |
| vectorGlobalMemUnit | ComputeUnit | |
| vectorMemInstsPerKiloInst | ComputeUnit | |
| vectorMemReads | ComputeUnit | |
| vectorMemReadsPerKiloInst | ComputeUnit | |
| vectorMemReadsPerWF | ComputeUnit | |
| vectorMemWrites | ComputeUnit | |
| vectorMemWritesPerKiloInst | ComputeUnit | |
| vectorMemWritesPerWF | ComputeUnit | |
| vectorRegsReserved | ComputeUnit | |
| vectorSharedMemUnit | ComputeUnit | |
| voltage() const | Clocked | inline |
| vpc | ComputeUnit | |
| vpc_f16 | ComputeUnit | |
| vpc_f32 | ComputeUnit | |
| vpc_f64 | ComputeUnit | |
| vrf | ComputeUnit | |
| vrf_gm_bus_latency | ComputeUnit | |
| vrf_lm_bus_latency | ComputeUnit | |
| vrfToCoalescerBusWidth | ComputeUnit | |
| vrfToGlobalMemPipeBus | ComputeUnit | |
| vrfToLocalMemPipeBus | ComputeUnit | |
| wakeupEventQueue(Tick when=(Tick) -1) | EventManager | inline |
| wavefrontSize | ComputeUnit | private |
| waveLevelParallelism | ComputeUnit | |
| wfBarrierSlots | ComputeUnit | private |
| wfList | ComputeUnit | |
| wfSize() const | ComputeUnit | inline |
| wgBlockedDueBarrierAllocation | ComputeUnit | |
| wgBlockedDueLdsAllocation | ComputeUnit | |
| ~Clocked() | Clocked | inlineprotectedvirtual |
| ~ComputeUnit() | ComputeUnit | |
| ~Drainable() | Drainable | protectedvirtual |
| ~Group() | Stats::Group | virtual |
| ~Serializable() | Serializable | virtual |
| ~SimObject() | SimObject | virtual |