gem5  v20.1.0.0
O3ThreadContext< Impl > Member List

This is the complete list of members for O3ThreadContext< Impl >, including all inherited members.

activate() overrideO3ThreadContext< Impl >
clearArchRegs() overrideO3ThreadContext< Impl >
conditionalSquash()O3ThreadContext< Impl >inline
contextId() const overrideO3ThreadContext< Impl >inline
copyArchRegs(ThreadContext *tc) overrideO3ThreadContext< Impl >
cpuO3ThreadContext< Impl >
cpuId() const overrideO3ThreadContext< Impl >inline
descheduleInstCountEvent(Event *event) overrideO3ThreadContext< Impl >inline
flattenRegId(const RegId &regId) const overrideO3ThreadContext< Impl >
getCheckerCpuPtr() overrideO3ThreadContext< Impl >inline
getCpuPtr() overrideO3ThreadContext< Impl >inline
getCurrentInstCount() overrideO3ThreadContext< Impl >inline
getDecoderPtr() overrideO3ThreadContext< Impl >inline
getDTBPtr() overrideO3ThreadContext< Impl >inline
getHtmCheckpointPtr() overrideO3ThreadContext< Impl >
getIsaPtr() overrideO3ThreadContext< Impl >inline
getITBPtr() overrideO3ThreadContext< Impl >inline
getPhysProxy() overrideO3ThreadContext< Impl >inline
getProcessPtr() overrideO3ThreadContext< Impl >inline
getSystemPtr() overrideO3ThreadContext< Impl >inline
getVirtProxy() overrideO3ThreadContext< Impl >
getWritableVecPredReg(const RegId &id) overrideO3ThreadContext< Impl >inline
getWritableVecPredRegFlat(RegIndex idx) overrideO3ThreadContext< Impl >
getWritableVecReg(const RegId &id) overrideO3ThreadContext< Impl >inline
getWritableVecRegFlat(RegIndex idx) overrideO3ThreadContext< Impl >
halt() overrideO3ThreadContext< Impl >
htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) overrideO3ThreadContext< Impl >
initMemProxies(ThreadContext *tc) overrideO3ThreadContext< Impl >inline
instAddr() const overrideO3ThreadContext< Impl >inline
microPC() const overrideO3ThreadContext< Impl >inline
nextInstAddr() const overrideO3ThreadContext< Impl >inline
O3CPU typedefO3ThreadContext< Impl >
pcState() const overrideO3ThreadContext< Impl >inline
pcState(const TheISA::PCState &val) overrideO3ThreadContext< Impl >
pcStateNoRecord(const TheISA::PCState &val) overrideO3ThreadContext< Impl >
readCCReg(RegIndex reg_idx) const overrideO3ThreadContext< Impl >inline
readCCRegFlat(RegIndex idx) const overrideO3ThreadContext< Impl >
readFloatReg(RegIndex reg_idx) const overrideO3ThreadContext< Impl >inline
readFloatRegFlat(RegIndex idx) const overrideO3ThreadContext< Impl >
readFuncExeInst() const overrideO3ThreadContext< Impl >inline
readIntReg(RegIndex reg_idx) const overrideO3ThreadContext< Impl >inline
readIntRegFlat(RegIndex idx) const overrideO3ThreadContext< Impl >
readLastActivate() overrideO3ThreadContext< Impl >
readLastSuspend() overrideO3ThreadContext< Impl >
readMiscReg(RegIndex misc_reg) overrideO3ThreadContext< Impl >inline
readMiscRegNoEffect(RegIndex misc_reg) const overrideO3ThreadContext< Impl >inline
readReg(RegIndex reg_idx)O3ThreadContext< Impl >inline
readStCondFailures() const overrideO3ThreadContext< Impl >inline
readVec16BitLaneReg(const RegId &id) const overrideO3ThreadContext< Impl >inline
readVec32BitLaneReg(const RegId &id) const overrideO3ThreadContext< Impl >inline
readVec64BitLaneReg(const RegId &id) const overrideO3ThreadContext< Impl >inline
readVec8BitLaneReg(const RegId &id) const overrideO3ThreadContext< Impl >inline
readVecElem(const RegId &reg) const overrideO3ThreadContext< Impl >inline
readVecElemFlat(RegIndex idx, const ElemIndex &elemIndex) const overrideO3ThreadContext< Impl >
readVecLaneFlat(RegIndex idx, int lId) constO3ThreadContext< Impl >inline
readVecPredReg(const RegId &id) const overrideO3ThreadContext< Impl >inline
readVecPredRegFlat(RegIndex idx) const overrideO3ThreadContext< Impl >
readVecReg(const RegId &id) const overrideO3ThreadContext< Impl >inline
readVecRegFlat(RegIndex idx) const overrideO3ThreadContext< Impl >
remove(PCEvent *e) overrideO3ThreadContext< Impl >inline
schedule(PCEvent *e) overrideO3ThreadContext< Impl >inline
scheduleInstCountEvent(Event *event, Tick count) overrideO3ThreadContext< Impl >inline
setCCReg(RegIndex reg_idx, RegVal val) overrideO3ThreadContext< Impl >inline
setCCRegFlat(RegIndex idx, RegVal val) overrideO3ThreadContext< Impl >
setContextId(ContextID id) overrideO3ThreadContext< Impl >inline
setFloatReg(RegIndex reg_idx, RegVal val) overrideO3ThreadContext< Impl >inline
setFloatRegFlat(RegIndex idx, RegVal val) overrideO3ThreadContext< Impl >
setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) overrideO3ThreadContext< Impl >
setIntReg(RegIndex reg_idx, RegVal val) overrideO3ThreadContext< Impl >inline
setIntRegFlat(RegIndex idx, RegVal val) overrideO3ThreadContext< Impl >
setMiscReg(RegIndex misc_reg, RegVal val) overrideO3ThreadContext< Impl >
setMiscRegNoEffect(RegIndex misc_reg, RegVal val) overrideO3ThreadContext< Impl >
setProcessPtr(Process *p) overrideO3ThreadContext< Impl >inline
setStatus(Status new_status) overrideO3ThreadContext< Impl >inline
setStCondFailures(unsigned sc_failures) overrideO3ThreadContext< Impl >inline
setThreadId(int id) overrideO3ThreadContext< Impl >inline
setVecElem(const RegId &reg, const VecElem &val) overrideO3ThreadContext< Impl >inline
setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx, const VecElem &val) overrideO3ThreadContext< Impl >
setVecLane(const RegId &reg, const LaneData< LaneSize::Byte > &val) overrideO3ThreadContext< Impl >inline
setVecLane(const RegId &reg, const LaneData< LaneSize::TwoByte > &val) overrideO3ThreadContext< Impl >inline
setVecLane(const RegId &reg, const LaneData< LaneSize::FourByte > &val) overrideO3ThreadContext< Impl >inline
setVecLane(const RegId &reg, const LaneData< LaneSize::EightByte > &val) overrideO3ThreadContext< Impl >inline
setVecLaneFlat(int idx, int lId, const LD &val)O3ThreadContext< Impl >inline
setVecPredReg(const RegId &reg, const VecPredRegContainer &val) overrideO3ThreadContext< Impl >inline
setVecPredRegFlat(RegIndex idx, const VecPredRegContainer &val) overrideO3ThreadContext< Impl >
setVecReg(const RegId &reg, const VecRegContainer &val) overrideO3ThreadContext< Impl >inline
setVecRegFlat(RegIndex idx, const VecRegContainer &val) overrideO3ThreadContext< Impl >
socketId() const overrideO3ThreadContext< Impl >inline
status() const overrideO3ThreadContext< Impl >inline
suspend() overrideO3ThreadContext< Impl >
syscall() overrideO3ThreadContext< Impl >inline
takeOverFrom(ThreadContext *old_context) overrideO3ThreadContext< Impl >
threadO3ThreadContext< Impl >
threadId() const overrideO3ThreadContext< Impl >inline

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