| countStat() | SparcISA::SparcFault< VecDisabled > | inlinevirtual |
| getNextLevel(PrivilegeLevel current) | SparcISA::SparcFault< VecDisabled > | inlinevirtual |
| H enum value | SparcISA::SparcFaultBase | |
| Hyperprivileged enum value | SparcISA::SparcFaultBase | |
| invoke(ThreadContext *tc, const StaticInstPtr &inst=StaticInst::nullStaticInstPtr) | SparcISA::SparcFaultBase | virtual |
| name() const | SparcISA::SparcFault< VecDisabled > | inline |
| SparcISA::SparcFaultBase::name() const =0 | FaultBase | pure virtual |
| NumLevels enum value | SparcISA::SparcFaultBase | |
| P enum value | SparcISA::SparcFaultBase | |
| priority() | SparcISA::SparcFault< VecDisabled > | inlinevirtual |
| Privileged enum value | SparcISA::SparcFaultBase | |
| PrivilegeLevel enum name | SparcISA::SparcFaultBase | |
| PrivilegeLevelSpec typedef | SparcISA::SparcFaultBase | |
| SH enum value | SparcISA::SparcFaultBase | |
| ShouldntHappen enum value | SparcISA::SparcFaultBase | |
| trapType() | SparcISA::SparcFault< VecDisabled > | inlinevirtual |
| U enum value | SparcISA::SparcFaultBase | |
| User enum value | SparcISA::SparcFaultBase | |
| vals | SparcISA::SparcFault< VecDisabled > | protectedstatic |
| vals("power_on_reset", 0x001, 0, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("watch_dog_reset", 0x002, 120, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("externally_initiated_reset", 0x003, 110, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("software_initiated_reset", 0x004, 130, {{SH, SH, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("RED_state_exception", 0x005, 1, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("store_error", 0x007, 201, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("instruction_access_exception", 0x008, 300, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("instruction_access_error", 0x00A, 400, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("illegal_instruction", 0x010, 620, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("privileged_opcode", 0x011, 700, {{P, SH, SH}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("fp_disabled", 0x020, 800, {{P, P, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("fp_disabled", 0x020, 800, {{P, P, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("fp_exception_ieee_754", 0x021, 1110, {{P, P, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("fp_exception_other", 0x022, 1110, {{P, P, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("tag_overflow", 0x023, 1400, {{P, P, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("clean_window", 0x024, 1010, {{P, P, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("division_by_zero", 0x028, 1500, {{P, P, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("internal_processor_error", 0x029, 4, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("instruction_invalid_tsb_entry", 0x02A, 210, {{H, H, SH}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("data_invalid_tsb_entry", 0x02B, 1203, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("data_access_exception", 0x030, 1201, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("data_access_error", 0x032, 1210, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("data_access_protection", 0x033, 1207, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("mem_address_not_aligned", 0x034, 1020, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("LDDF_mem_address_not_aligned", 0x035, 1010, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("STDF_mem_address_not_aligned", 0x036, 1010, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("privileged_action", 0x037, 1110, {{H, H, SH}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("LDQF_mem_address_not_aligned", 0x038, 1010, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("STQF_mem_address_not_aligned", 0x039, 1010, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("instruction_real_translation_miss", 0x03E, 208, {{H, H, SH}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("data_real_translation_miss", 0x03F, 1203, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("interrupt_level_n", 0x040, 0, {{P, P, SH}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("hstick_match", 0x05E, 1601, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("trap_level_zero", 0x05F, 202, {{H, H, SH}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("interrupt_vector", 0x060, 2630, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("PA_watchpoint", 0x061, 1209, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("VA_watchpoint", 0x062, 1120, {{P, P, SH}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("fast_instruction_access_MMU_miss", 0x064, 208, {{H, H, SH}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("fast_data_access_MMU_miss", 0x068, 1203, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("fast_data_access_protection", 0x06C, 1207, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("instruction_break", 0x076, 610, {{H, H, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("cpu_mondo", 0x07C, 1608, {{P, P, SH}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("dev_mondo", 0x07D, 1611, {{P, P, SH}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("resume_error", 0x07E, 3330, {{P, P, SH}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("spill_n_normal", 0x080, 900, {{P, P, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("spill_n_other", 0x0A0, 900, {{P, P, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("fill_n_normal", 0x0C0, 900, {{P, P, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("fill_n_other", 0x0E0, 900, {{P, P, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals("trap_instruction", 0x100, 1602, {{P, P, H}}) | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| vals | SparcISA::SparcFault< VecDisabled > | protected |
| ~FaultBase() | FaultBase | inlinevirtual |