gem5  v20.1.0.0
Classes | Typedefs | Enumerations | Functions | Variables
SparcISA Namespace Reference

Classes

class  BlockMem
 
class  BlockMemImm
 
class  BlockMemImmMicro
 
class  BlockMemMicro
 
class  Branch
 Base class for branch operations. More...
 
class  BranchDisp
 Base class for branch operations with an immediate displacement. More...
 
class  BranchImm13
 Base class for branches that use an immediate and a register to compute their displacements. More...
 
class  BranchNBits
 Base class for branches with n bit displacements. More...
 
class  BranchSplit
 Base class for 16bit split displacements. More...
 
class  CleanWindow
 
class  CpuMondo
 
class  DataAccessError
 
class  DataAccessException
 
class  DataAccessProtection
 
class  DataInvalidTSBEntry
 
class  DataRealTranslationMiss
 
class  Decoder
 
class  DevMondo
 
class  DivisionByZero
 
class  EnumeratedFault
 
class  ExternallyInitiatedReset
 
class  FailUnimplemented
 Static instruction class for unimplemented instructions that cause simulator termination. More...
 
class  FastDataAccessMMUMiss
 
class  FastDataAccessProtection
 
class  FastInstructionAccessMMUMiss
 
class  FillNNormal
 
class  FillNOther
 
class  FpDisabled
 
class  FpExceptionIEEE754
 
class  FpExceptionOther
 
class  FpUnimpl
 
class  FsWorkload
 
class  HstickMatch
 
class  IllegalInstruction
 
class  InstructionAccessError
 
class  InstructionAccessException
 
class  InstructionBreakpoint
 
class  InstructionInvalidTSBEntry
 
class  InstructionRealTranslationMiss
 
class  InternalProcessorError
 
class  InterruptLevelN
 
class  Interrupts
 
class  InterruptVector
 
class  IntOp
 Base class for integer operations. More...
 
class  IntOpImm
 Base class for immediate integer operations. More...
 
class  IntOpImm10
 Base class for 10 bit immediate integer operations. More...
 
class  IntOpImm11
 Base class for 11 bit immediate integer operations. More...
 
class  IntOpImm13
 Base class for 13 bit immediate integer operations. More...
 
class  ISA
 
class  LDDFMemAddressNotAligned
 
class  LDQFMemAddressNotAligned
 
class  Mem
 Base class for memory operations. More...
 
class  MemAddressNotAligned
 
class  MemImm
 Class for memory operations which use an immediate offset. More...
 
class  Nop
 Nop class. More...
 
class  PageTableEntry
 
class  PAWatchpoint
 
class  PowerOnReset
 
class  Priv
 Base class for privelege mode operations. More...
 
class  PrivilegedAction
 
class  PrivilegedOpcode
 
class  PrivImm
 Base class for privelege mode operations with immediates. More...
 
class  PrivReg
 
class  RdPriv
 
class  REDStateException
 
class  RemoteGDB
 
class  ResumableError
 
class  SetHi
 Base class for sethi. More...
 
class  SoftwareInitiatedReset
 
class  Sparc32LinuxProcess
 A process with emulated SPARC/Linux syscalls. More...
 
class  Sparc64LinuxProcess
 A process with emulated 32 bit SPARC/Linux syscalls. More...
 
class  SparcDelayedMicroInst
 
class  SparcFault
 
class  SparcFaultBase
 
class  SparcLinuxProcess
 
class  SparcMacroInst
 
class  SparcMicroInst
 
class  SparcSolarisProcess
 A process with emulated SPARC/Solaris syscalls. More...
 
class  SparcStaticInst
 Base class for all SPARC static instructions. More...
 
class  SpillNNormal
 
class  SpillNOther
 
class  StackTrace
 
class  STDFMemAddressNotAligned
 
class  StoreError
 
class  STQFMemAddressNotAligned
 
class  TagOverflow
 
class  TLB
 
struct  TlbEntry
 
class  TlbMap
 
struct  TlbRange
 
class  Trap
 Base class for trap instructions, or instructions that always fault. More...
 
class  TrapInstruction
 
class  TrapLevelZero
 
class  TteTag
 
class  Unknown
 Class for Unknown/Illegal instructions. More...
 
class  VAWatchpoint
 
class  VecDisabled
 
class  WarnUnimplemented
 Base class for unimplemented instructions that cause a warning to be printed (but do not terminate simulation). More...
 
class  WatchDogReset
 
class  WrPriv
 
class  WrPrivImm
 

Typedefs

typedef uint32_t TrapType
 
typedef uint32_t FaultPriority
 
using VecElem = ::DummyVecElem
 
using VecReg = ::DummyVecReg
 
using ConstVecReg = ::DummyConstVecReg
 
using VecRegContainer = ::DummyVecRegContainer
 
using VecPredReg = ::DummyVecPredReg
 
using ConstVecPredReg = ::DummyConstVecPredReg
 
using VecPredRegContainer = ::DummyVecPredRegContainer
 
typedef uint32_t MachInst
 
typedef uint64_t ExtMachInst
 
typedef GenericISA::DelaySlotUPCState< MachInst > PCState
 

Enumerations

enum  ASI {
  ASI_IMPLICIT = 0x00, ASI_NUCLEUS = 0x4, ASI_N = 0x4, ASI_NL = 0xC,
  ASI_NUCLEUS_LITTLE = ASI_NL, ASI_AIUP = 0x10, ASI_AS_IF_USER_PRIMARY = ASI_AIUP, ASI_AIUS = 0x11,
  ASI_AS_IF_USER_SECONDARY = ASI_AIUS, ASI_REAL = 0x14, ASI_REAL_IO = 0x15, ASI_BLK_AIUP = 0x16,
  ASI_BLOCK_AS_IF_USER_PRIMARY = ASI_BLK_AIUP, ASI_BLK_AIUS = 0x17, ASI_BLOCK_AS_IF_USER_SECONDARY = ASI_BLK_AIUS, ASI_AIUP_L = 0x18,
  ASI_AS_IF_USER_PRIMARY_LITTLE = ASI_AIUP_L, ASI_AIUS_L = 0x19, ASI_AS_IF_USER_SECONDARY_LITTLE = ASI_AIUS_L, ASI_REAL_L = 0x1C,
  ASI_REAL_LITTLE = ASI_REAL_L, ASI_REAL_IO_L = 0x1D, ASI_REAL_IO_LITTLE = ASI_REAL_IO_L, ASI_BLK_AIUP_L = 0x1E,
  ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE = ASI_BLK_AIUP_L, ASI_BLK_AIUS_L = 0x1F, ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE = ASI_BLK_AIUS_L, ASI_SCRATCHPAD = 0x20,
  ASI_MMU = 0x21, ASI_LDTX_AIUP = 0x22, ASI_LD_TWINX_AS_IF_USER_PRIMARY = ASI_LDTX_AIUP, ASI_LDTX_AIUS = 0x23,
  ASI_LD_TWINX_AS_IF_USER_SECONDARY = ASI_LDTX_AIUS, ASI_QUAD_LDD = 0x24, ASI_QUEUE = 0x25, ASI_QUAD_LDD_REAL = 0x26,
  ASI_LDTX_REAL = ASI_QUAD_LDD_REAL, ASI_LDTX_N = 0x27, ASI_LD_TWINX_NUCLEUS = ASI_LDTX_N, ASI_ST_BLKINIT_NUCLEUS = ASI_LDTX_N,
  ASI_STBI_N = ASI_LDTX_N, ASI_LDTX_AIUP_L = 0x2A, ASI_TWINX_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L, ASI_ST_BLKINIT_AS_IF_USER_PRIMARY_LITTLE = ASI_LDTX_AIUP_L,
  ASI_STBI_AIUP_L = ASI_LDTX_AIUP_L, ASI_LDTX_AIUS_L = 0x2B, ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L, ASI_ST_BLKINIT_AS_IF_USER_SECONDARY_LITTLE = ASI_LDTX_AIUS_L,
  ASI_STBI_AIUS_L = ASI_LDTX_AIUS_L, ASI_LTX_L = 0x2C, ASI_TWINX_LITTLE = ASI_LTX_L, ASI_LDTX_REAL_L = 0x2E,
  ASI_LD_TWINX_REAL_LITTLE = ASI_LDTX_REAL_L, ASI_LDTX_NL = 0x2F, ASI_LD_TWINX_NUCLEUS_LITTLE = ASI_LDTX_NL, ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x31,
  ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x32, ASI_DMMU_CTXT_ZERO_CONFIG = 0x33, ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0 = 0x35, ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1 = 0x36,
  ASI_IMMU_CTXT_ZERO_CONFIG = 0x37, ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x39, ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3A, ASI_DMMU_CTXT_NONZERO_CONFIG = 0x3B,
  ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x3D, ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3E, ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F, ASI_STREAM_MA = 0x40,
  ASI_CMT_SHARED = 0x41, ASI_SPARC_BIST_CONTROL = 0x42, ASI_INST_MASK_REG = 0x42, ASI_LSU_DIAG_REG = 0x42,
  ASI_STM_CTL_REG = 0x44, ASI_LSU_CONTROL_REG = 0x45, ASI_DCACHE_DATA = 0x46, ASI_DCACHE_TAG = 0x47,
  ASI_INTR_DISPATCH_STATUS = 0x48, ASI_INTR_RECEIVE = 0x49, ASI_UPA_CONFIG_REGISTER = 0x4A, ASI_SPARC_ERROR_EN_REG = 0x4B,
  ASI_SPARC_ERROR_STATUS_REG = 0x4C, ASI_SPARC_ERROR_ADDRESS_REG = 0x4D, ASI_ECACHE_TAG_DATA = 0x4E, ASI_HYP_SCRATCHPAD = 0x4F,
  ASI_IMMU = 0x50, ASI_IMMU_TSB_PS0_PTR_REG = 0x51, ASI_IMMU_TSB_PS1_PTR_REG = 0x52, ASI_ITLB_DATA_IN_REG = 0x54,
  ASI_ITLB_DATA_ACCESS_REG = 0x55, ASI_ITLB_TAG_READ_REG = 0x56, ASI_IMMU_DEMAP = 0x57, ASI_DMMU = 0x58,
  ASI_DMMU_TSB_PS0_PTR_REG = 0x59, ASI_DMMU_TSB_PS1_PTR_REG = 0x5A, ASI_DMMU_TSB_DIRECT_PTR_REG = 0x5B, ASI_DTLB_DATA_IN_REG = 0x5C,
  ASI_DTLB_DATA_ACCESS_REG = 0x5D, ASI_DTLB_TAG_READ_REG = 0x5E, ASI_DMMU_DEMAP = 0x5F, ASI_TLB_INVALIDATE_ALL = 0x60,
  ASI_CMT_PER_STRAND = 0x63, ASI_ICACHE_INSTR = 0x66, ASI_ICACHE_TAG = 0x67, ASI_SWVR_INTR_RECEIVE = 0x72,
  ASI_SWVR_UDB_INTR_W = 0x73, ASI_SWVR_UDB_INTR_R = 0x74, ASI_P = 0x80, ASI_PRIMARY = ASI_P,
  ASI_S = 0x81, ASI_SECONDARY = ASI_S, ASI_PNF = 0x82, ASI_PRIMARY_NO_FAULT = ASI_PNF,
  ASI_SNF = 0x83, ASI_SECONDARY_NO_FAULT = ASI_SNF, ASI_PL = 0x88, ASI_PRIMARY_LITTLE = ASI_PL,
  ASI_SL = 0x89, ASI_SECONDARY_LITTLE = ASI_SL, ASI_PNFL = 0x8A, ASI_PRIMARY_NO_FAULT_LITTLE = ASI_PNFL,
  ASI_SNFL = 0x8B, ASI_SECONDARY_NO_FAULT_LITTLE = ASI_SNFL, ASI_PST8_P = 0xC0, ASI_PST8_PRIMARY = ASI_PST8_P,
  ASI_PST8_S = 0xC1, ASI_PST8_SECONDARY = ASI_PST8_S, ASI_PST16_P = 0xC2, ASI_PST16_PRIMARY = ASI_PST16_P,
  ASI_PST16_S = 0xC3, ASI_PST16_SECONDARY = ASI_PST16_S, ASI_PST32_P = 0xC4, ASI_PST32_PRIMARY = ASI_PST32_P,
  ASI_PST32_S = 0xC5, ASI_PST32_SECONDARY = ASI_PST32_S, ASI_PST8_PL = 0xC8, ASI_PST8_PRIMARY_LITTLE = ASI_PST8_PL,
  ASI_PST8_SL = 0xC9, ASI_PST8_SECONDARY_LITTLE = ASI_PST8_SL, ASI_PST16_PL = 0xCA, ASI_PST16_PRIMARY_LITTLE = ASI_PST16_PL,
  ASI_PST16_SL = 0xCB, ASI_PST16_SECONDARY_LITTLE = ASI_PST16_SL, ASI_PST32_PL = 0xCC, ASI_PST32_PRIMARY_LITTLE = ASI_PST32_PL,
  ASI_PST32_SL = 0xCD, ASI_PST32_SECONDARY_LITTLE = ASI_PST32_SL, ASI_FL8_P = 0xD0, ASI_FL8_PRIMARY = ASI_FL8_P,
  ASI_FL8_S = 0xD1, ASI_FL8_SECONDARY = ASI_FL8_S, ASI_FL16_P = 0xD2, ASI_FL16_PRIMARY = ASI_FL16_P,
  ASI_FL16_S = 0xD3, ASI_FL16_SECONDARY = ASI_FL16_S, ASI_FL8_PL = 0xD8, ASI_FL8_PRIMARY_LITTLE = ASI_FL8_PL,
  ASI_FL8_SL = 0xD9, ASI_FL8_SECONDARY_LITTLE = ASI_FL8_SL, ASI_FL16_PL = 0xDA, ASI_FL16_PRIMARY_LITTLE = ASI_FL16_PL,
  ASI_FL16_SL = 0xDB, ASI_FL16_SECONDARY_LITTLE = ASI_FL16_SL, ASI_LDTX_P = 0xE2, ASI_LD_TWINX_PRIMARY = ASI_LDTX_P,
  ASI_LDTX_S = 0xE3, ASI_LD_TWINX_SECONDARY = ASI_LDTX_S, ASI_LDTX_PL = 0xEA, ASI_LD_TWINX_PRIMARY_LITTLE = ASI_LDTX_PL,
  ASI_LDTX_SL = 0xEB, ASI_LD_TWINX_SECONDARY_LITTLE = ASI_LDTX_SL, ASI_BLK_P = 0xF0, ASI_BLOCK_PRIMARY = ASI_BLK_P,
  ASI_BLK_S = 0xF1, ASI_BLOCK_SECONDARY = ASI_BLK_S, ASI_BLK_PL = 0xF8, ASI_BLOCK_PRIMARY_LITTLE = ASI_BLK_PL,
  ASI_BLK_SL = 0xF9, ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL, MAX_ASI = 0xFF
}
 
enum  CondTest {
  Always =0x8, Never =0x0, NotEqual =0x9, Equal =0x1,
  Greater =0xA, LessOrEqual =0x2, GreaterOrEqual =0xB, Less =0x3,
  GreaterUnsigned =0xC, LessOrEqualUnsigned =0x4, CarryClear =0xD, CarrySet =0x5,
  Positive =0xE, Negative =0x6, OverflowClear =0xF, OverflowSet =0x7
}
 
enum  FpCondTest {
  FAlways =0x8, FNever =0x0, FUnordered =0x7, FGreater =0x6,
  FUnorderedOrGreater =0x5, FLess =0x4, FUnorderedOrLess =0x3, FLessOrGreater =0x2,
  FNotEqual =0x1, FEqual =0x9, FUnorderedOrEqual =0xA, FGreaterOrEqual =0xB,
  FUnorderedOrGreaterOrEqual =0xC, FLessOrEqual =0xD, FUnorderedOrLessOrEqual =0xE, FOrdered =0xF
}
 
enum  InterruptTypes {
  IT_TRAP_LEVEL_ZERO, IT_HINTP, IT_INT_VEC, IT_CPU_MONDO,
  IT_DEV_MONDO, IT_RES_ERROR, IT_SOFT_INT, NumInterruptTypes
}
 
enum  MiscRegIndex {
  MISCREG_ASI, MISCREG_TICK, MISCREG_FPRS, MISCREG_PCR,
  MISCREG_PIC, MISCREG_GSR, MISCREG_SOFTINT_SET, MISCREG_SOFTINT_CLR,
  MISCREG_SOFTINT, MISCREG_TICK_CMPR, MISCREG_STICK, MISCREG_STICK_CMPR,
  MISCREG_TPC, MISCREG_TNPC, MISCREG_TSTATE, MISCREG_TT,
  MISCREG_PRIVTICK, MISCREG_TBA, MISCREG_PSTATE, MISCREG_TL,
  MISCREG_PIL, MISCREG_CWP, MISCREG_GL, MISCREG_HPSTATE,
  MISCREG_HTSTATE, MISCREG_HINTP, MISCREG_HTBA, MISCREG_HVER,
  MISCREG_STRAND_STS_REG, MISCREG_HSTICK_CMPR, MISCREG_FSR, MISCREG_MMU_P_CONTEXT,
  MISCREG_MMU_S_CONTEXT, MISCREG_MMU_PART_ID, MISCREG_MMU_LSU_CTRL, MISCREG_SCRATCHPAD_R0,
  MISCREG_SCRATCHPAD_R1, MISCREG_SCRATCHPAD_R2, MISCREG_SCRATCHPAD_R3, MISCREG_SCRATCHPAD_R4,
  MISCREG_SCRATCHPAD_R5, MISCREG_SCRATCHPAD_R6, MISCREG_SCRATCHPAD_R7, MISCREG_QUEUE_CPU_MONDO_HEAD,
  MISCREG_QUEUE_CPU_MONDO_TAIL, MISCREG_QUEUE_DEV_MONDO_HEAD, MISCREG_QUEUE_DEV_MONDO_TAIL, MISCREG_QUEUE_RES_ERROR_HEAD,
  MISCREG_QUEUE_RES_ERROR_TAIL, MISCREG_QUEUE_NRES_ERROR_HEAD, MISCREG_QUEUE_NRES_ERROR_TAIL, MISCREG_TLB_DATA,
  MISCREG_NUMMISCREGS
}
 
enum  {
  INTREG_G0, INTREG_G1, INTREG_G2, INTREG_G3,
  INTREG_G4, INTREG_G5, INTREG_G6, INTREG_G7,
  INTREG_O0, INTREG_O1, INTREG_O2, INTREG_O3,
  INTREG_O4, INTREG_O5, INTREG_O6, INTREG_O7,
  INTREG_L0, INTREG_L1, INTREG_L2, INTREG_L3,
  INTREG_L4, INTREG_L5, INTREG_L6, INTREG_L7,
  INTREG_I0, INTREG_I1, INTREG_I2, INTREG_I3,
  INTREG_I4, INTREG_I5, INTREG_I6, INTREG_I7,
  NumIntArchRegs, INTREG_UREG0 = NumIntArchRegs, INTREG_Y, INTREG_CCR,
  INTREG_CANSAVE, INTREG_CANRESTORE, INTREG_CLEANWIN, INTREG_OTHERWIN,
  INTREG_WSTATE, INTREG_GSR, NumMicroIntRegs = INTREG_GSR - INTREG_UREG0 + 1
}
 

Functions

bool asiIsBlock (ASI asi)
 
bool asiIsPrimary (ASI asi)
 
bool asiIsSecondary (ASI asi)
 
bool asiIsNucleus (ASI asi)
 
bool asiIsAsIfUser (ASI asi)
 
bool asiIsIO (ASI asi)
 
bool asiIsReal (ASI asi)
 
bool asiIsLittle (ASI asi)
 
bool asiIsTwin (ASI asi)
 
bool asiIsPartialStore (ASI asi)
 
bool asiIsFloatingLoad (ASI asi)
 
bool asiIsNoFault (ASI asi)
 
bool asiIsScratchPad (ASI asi)
 
bool asiIsCmt (ASI asi)
 
bool asiIsQueue (ASI asi)
 
bool asiIsInterrupt (ASI asi)
 
bool asiIsMmu (ASI asi)
 
bool asiIsUnPriv (ASI asi)
 
bool asiIsPriv (ASI asi)
 
bool asiIsHPriv (ASI asi)
 
bool asiIsReg (ASI asi)
 
bool asiIsSparcError (ASI asi)
 
bool asiIsDtlb (ASI)
 
void enterREDState (ThreadContext *tc)
 This causes the thread context to enter RED state. More...
 
void doREDFault (ThreadContext *tc, TrapType tt)
 This sets everything up for a RED state trap except for actually jumping to the handler. More...
 
void doNormalFault (ThreadContext *tc, TrapType tt, bool gotoHpriv)
 This sets everything up for a normal trap except for actually jumping to the handler. More...
 
void getREDVector (RegVal TT, Addr &PC, Addr &NPC)
 
void getHyperVector (ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT)
 
void getPrivVector (ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT, RegVal TL)
 
static PSTATE buildPstateMask ()
 
SyscallReturn getresuidFunc (SyscallDesc *desc, ThreadContext *tc, Addr ruid, Addr euid, Addr suid)
 
static SyscallReturn unameFunc (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
 Target uname() handler. More...
 
 BitUnion64 (HPSTATE) Bitfield< 0 > tlz
 
 EndBitUnion (HPSTATE) BitUnion16(PSTATE) Bitfield< 1 > ie
 
 EndBitUnion (PSTATE) BitUnion8(CCR) SubBitUnion(xcc
 
 EndSubBitUnion (xcc) SubBitUnion(icc
 
 EndSubBitUnion (icc) EndBitUnion(CCR) struct STS
 
uint64_t getArgument (ThreadContext *tc, int &number, uint16_t size, bool fp)
 
void copyMiscRegs (ThreadContext *src, ThreadContext *dest)
 
void copyRegs (ThreadContext *src, ThreadContext *dest)
 
PCState buildRetPC (const PCState &curPC, const PCState &callPC)
 
static bool inUserMode (ThreadContext *tc)
 
void advancePC (PCState &pc, const StaticInstPtr &inst)
 
uint64_t getExecutingAsid (ThreadContext *tc)
 

Variables

const int numFillInsts = 32
 
const int numSpillInsts = 32
 
const MachInst fillHandler64 [numFillInsts]
 
const MachInst fillHandler32 [numFillInsts]
 
const MachInst spillHandler64 [numSpillInsts]
 
const MachInst spillHandler32 [numSpillInsts]
 
const char * CondTestAbbrev []
 
static const PSTATE PstateMask = buildPstateMask()
 
const ByteOrder GuestByteOrder = ByteOrder::big
 
const Addr PageShift = 13
 
const Addr PageBytes = ULL(1) << PageShift
 
Bitfield< 2 > hpriv
 
Bitfield< 5 > red
 
Bitfield< 10 > ibe
 
Bitfield< 11 > id
 
Bitfield< 2 > priv
 
Bitfield< 3 > am
 
Bitfield< 4 > pef
 
Bitfield< 7, 6 > mm
 
Bitfield< 8 > tle
 
Bitfield< 9 > cle
 
Bitfield< 10 > pid0
 
Bitfield< 11 > pid1
 
Bitfield< 7 > n
 
Bitfield< 6 > z
 
Bitfield< 5 > v
 
Bitfield< 4 > c
 
const int NumMiscRegs = MISCREG_NUMMISCREGS
 
constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg
 
constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes
 
constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits
 
constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr
 
const int ZeroReg = 0
 
const int ReturnAddressReg = INTREG_I7
 
const int ReturnValueReg = INTREG_O0
 
const int StackPointerReg = INTREG_O6
 
const int FramePointerReg = INTREG_I6
 
const int SyscallPseudoReturnReg = INTREG_O1
 
const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs
 
const int NumVecRegs = 1
 
const int NumVecPredRegs = 1
 
const int NumCCRegs = 0
 
const int NumFloatRegs = 64
 
const int NumFloatArchRegs = NumFloatRegs
 
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs
 
const int MaxPTL = 2
 
const int MaxTL = 6
 
const int MaxGL = 3
 
const int MaxPGL = 2
 
const int NWindows = 8
 
const Addr StartVAddrHole = ULL(0x0000800000000000)
 
const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF)
 
const Addr VAddrAMask = ULL(0xFFFFFFFF)
 
const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF)
 

Typedef Documentation

◆ ConstVecPredReg

using SparcISA::ConstVecPredReg = typedef ::DummyConstVecPredReg

Definition at line 56 of file registers.hh.

◆ ConstVecReg

using SparcISA::ConstVecReg = typedef ::DummyConstVecReg

Definition at line 49 of file registers.hh.

◆ ExtMachInst

typedef uint64_t SparcISA::ExtMachInst

Definition at line 39 of file types.hh.

◆ FaultPriority

typedef uint32_t SparcISA::FaultPriority

Definition at line 41 of file faults.hh.

◆ MachInst

typedef uint32_t SparcISA::MachInst

Definition at line 38 of file types.hh.

◆ PCState

typedef GenericISA::DelaySlotUPCState<MachInst> SparcISA::PCState

Definition at line 41 of file types.hh.

◆ TrapType

typedef uint32_t SparcISA::TrapType

Definition at line 40 of file faults.hh.

◆ VecElem

using SparcISA::VecElem = typedef ::DummyVecElem

Definition at line 47 of file registers.hh.

◆ VecPredReg

using SparcISA::VecPredReg = typedef ::DummyVecPredReg

Definition at line 55 of file registers.hh.

◆ VecPredRegContainer

using SparcISA::VecPredRegContainer = typedef ::DummyVecPredRegContainer

Definition at line 57 of file registers.hh.

◆ VecReg

using SparcISA::VecReg = typedef ::DummyVecReg

Definition at line 48 of file registers.hh.

◆ VecRegContainer

using SparcISA::VecRegContainer = typedef ::DummyVecRegContainer

Definition at line 50 of file registers.hh.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
INTREG_G0 
INTREG_G1 
INTREG_G2 
INTREG_G3 
INTREG_G4 
INTREG_G5 
INTREG_G6 
INTREG_G7 
INTREG_O0 
INTREG_O1 
INTREG_O2 
INTREG_O3 
INTREG_O4 
INTREG_O5 
INTREG_O6 
INTREG_O7 
INTREG_L0 
INTREG_L1 
INTREG_L2 
INTREG_L3 
INTREG_L4 
INTREG_L5 
INTREG_L6 
INTREG_L7 
INTREG_I0 
INTREG_I1 
INTREG_I2 
INTREG_I3 
INTREG_I4 
INTREG_I5 
INTREG_I6 
INTREG_I7 
NumIntArchRegs 
INTREG_UREG0 
INTREG_Y 
INTREG_CCR 
INTREG_CANSAVE 
INTREG_CANRESTORE 
INTREG_CLEANWIN 
INTREG_OTHERWIN 
INTREG_WSTATE 
INTREG_GSR 
NumMicroIntRegs 

Definition at line 62 of file registers.hh.

◆ ASI

enum SparcISA::ASI
Enumerator
ASI_IMPLICIT 
ASI_NUCLEUS 
ASI_N 
ASI_NL 
ASI_NUCLEUS_LITTLE 
ASI_AIUP 
ASI_AS_IF_USER_PRIMARY 
ASI_AIUS 
ASI_AS_IF_USER_SECONDARY 
ASI_REAL 
ASI_REAL_IO 
ASI_BLK_AIUP 
ASI_BLOCK_AS_IF_USER_PRIMARY 
ASI_BLK_AIUS 
ASI_BLOCK_AS_IF_USER_SECONDARY 
ASI_AIUP_L 
ASI_AS_IF_USER_PRIMARY_LITTLE 
ASI_AIUS_L 
ASI_AS_IF_USER_SECONDARY_LITTLE 
ASI_REAL_L 
ASI_REAL_LITTLE 
ASI_REAL_IO_L 
ASI_REAL_IO_LITTLE 
ASI_BLK_AIUP_L 
ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 
ASI_BLK_AIUS_L 
ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 
ASI_SCRATCHPAD 
ASI_MMU 
ASI_LDTX_AIUP 
ASI_LD_TWINX_AS_IF_USER_PRIMARY 
ASI_LDTX_AIUS 
ASI_LD_TWINX_AS_IF_USER_SECONDARY 
ASI_QUAD_LDD 
ASI_QUEUE 
ASI_QUAD_LDD_REAL 
ASI_LDTX_REAL 
ASI_LDTX_N 
ASI_LD_TWINX_NUCLEUS 
ASI_ST_BLKINIT_NUCLEUS 
ASI_STBI_N 
ASI_LDTX_AIUP_L 
ASI_TWINX_AS_IF_USER_PRIMARY_LITTLE 
ASI_ST_BLKINIT_AS_IF_USER_PRIMARY_LITTLE 
ASI_STBI_AIUP_L 
ASI_LDTX_AIUS_L 
ASI_LD_TWINX_AS_IF_USER_SECONDARY_LITTLE 
ASI_ST_BLKINIT_AS_IF_USER_SECONDARY_LITTLE 
ASI_STBI_AIUS_L 
ASI_LTX_L 
ASI_TWINX_LITTLE 
ASI_LDTX_REAL_L 
ASI_LD_TWINX_REAL_LITTLE 
ASI_LDTX_NL 
ASI_LD_TWINX_NUCLEUS_LITTLE 
ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 
ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1 
ASI_DMMU_CTXT_ZERO_CONFIG 
ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0 
ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1 
ASI_IMMU_CTXT_ZERO_CONFIG 
ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 
ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1 
ASI_DMMU_CTXT_NONZERO_CONFIG 
ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0 
ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1 
ASI_IMMU_CTXT_NONZERO_CONFIG 
ASI_STREAM_MA 
ASI_CMT_SHARED 
ASI_SPARC_BIST_CONTROL 
ASI_INST_MASK_REG 
ASI_LSU_DIAG_REG 
ASI_STM_CTL_REG 
ASI_LSU_CONTROL_REG 
ASI_DCACHE_DATA 
ASI_DCACHE_TAG 
ASI_INTR_DISPATCH_STATUS 
ASI_INTR_RECEIVE 
ASI_UPA_CONFIG_REGISTER 
ASI_SPARC_ERROR_EN_REG 
ASI_SPARC_ERROR_STATUS_REG 
ASI_SPARC_ERROR_ADDRESS_REG 
ASI_ECACHE_TAG_DATA 
ASI_HYP_SCRATCHPAD 
ASI_IMMU 
ASI_IMMU_TSB_PS0_PTR_REG 
ASI_IMMU_TSB_PS1_PTR_REG 
ASI_ITLB_DATA_IN_REG 
ASI_ITLB_DATA_ACCESS_REG 
ASI_ITLB_TAG_READ_REG 
ASI_IMMU_DEMAP 
ASI_DMMU 
ASI_DMMU_TSB_PS0_PTR_REG 
ASI_DMMU_TSB_PS1_PTR_REG 
ASI_DMMU_TSB_DIRECT_PTR_REG 
ASI_DTLB_DATA_IN_REG 
ASI_DTLB_DATA_ACCESS_REG 
ASI_DTLB_TAG_READ_REG 
ASI_DMMU_DEMAP 
ASI_TLB_INVALIDATE_ALL 
ASI_CMT_PER_STRAND 
ASI_ICACHE_INSTR 
ASI_ICACHE_TAG 
ASI_SWVR_INTR_RECEIVE 
ASI_SWVR_UDB_INTR_W 
ASI_SWVR_UDB_INTR_R 
ASI_P 
ASI_PRIMARY 
ASI_S 
ASI_SECONDARY 
ASI_PNF 
ASI_PRIMARY_NO_FAULT 
ASI_SNF 
ASI_SECONDARY_NO_FAULT 
ASI_PL 
ASI_PRIMARY_LITTLE 
ASI_SL 
ASI_SECONDARY_LITTLE 
ASI_PNFL 
ASI_PRIMARY_NO_FAULT_LITTLE 
ASI_SNFL 
ASI_SECONDARY_NO_FAULT_LITTLE 
ASI_PST8_P 
ASI_PST8_PRIMARY 
ASI_PST8_S 
ASI_PST8_SECONDARY 
ASI_PST16_P 
ASI_PST16_PRIMARY 
ASI_PST16_S 
ASI_PST16_SECONDARY 
ASI_PST32_P 
ASI_PST32_PRIMARY 
ASI_PST32_S 
ASI_PST32_SECONDARY 
ASI_PST8_PL 
ASI_PST8_PRIMARY_LITTLE 
ASI_PST8_SL 
ASI_PST8_SECONDARY_LITTLE 
ASI_PST16_PL 
ASI_PST16_PRIMARY_LITTLE 
ASI_PST16_SL 
ASI_PST16_SECONDARY_LITTLE 
ASI_PST32_PL 
ASI_PST32_PRIMARY_LITTLE 
ASI_PST32_SL 
ASI_PST32_SECONDARY_LITTLE 
ASI_FL8_P 
ASI_FL8_PRIMARY 
ASI_FL8_S 
ASI_FL8_SECONDARY 
ASI_FL16_P 
ASI_FL16_PRIMARY 
ASI_FL16_S 
ASI_FL16_SECONDARY 
ASI_FL8_PL 
ASI_FL8_PRIMARY_LITTLE 
ASI_FL8_SL 
ASI_FL8_SECONDARY_LITTLE 
ASI_FL16_PL 
ASI_FL16_PRIMARY_LITTLE 
ASI_FL16_SL 
ASI_FL16_SECONDARY_LITTLE 
ASI_LDTX_P 
ASI_LD_TWINX_PRIMARY 
ASI_LDTX_S 
ASI_LD_TWINX_SECONDARY 
ASI_LDTX_PL 
ASI_LD_TWINX_PRIMARY_LITTLE 
ASI_LDTX_SL 
ASI_LD_TWINX_SECONDARY_LITTLE 
ASI_BLK_P 
ASI_BLOCK_PRIMARY 
ASI_BLK_S 
ASI_BLOCK_SECONDARY 
ASI_BLK_PL 
ASI_BLOCK_PRIMARY_LITTLE 
ASI_BLK_SL 
ASI_BLOCK_SECONDARY_LITTLE 
MAX_ASI 

Definition at line 35 of file asi.hh.

◆ CondTest

enum SparcISA::CondTest
Enumerator
Always 
Never 
NotEqual 
Equal 
Greater 
LessOrEqual 
GreaterOrEqual 
Less 
GreaterUnsigned 
LessOrEqualUnsigned 
CarryClear 
CarrySet 
Positive 
Negative 
OverflowClear 
OverflowSet 

Definition at line 42 of file static_inst.hh.

◆ FpCondTest

enum SparcISA::FpCondTest
Enumerator
FAlways 
FNever 
FUnordered 
FGreater 
FUnorderedOrGreater 
FLess 
FUnorderedOrLess 
FLessOrGreater 
FNotEqual 
FEqual 
FUnorderedOrEqual 
FGreaterOrEqual 
FUnorderedOrGreaterOrEqual 
FLessOrEqual 
FUnorderedOrLessOrEqual 
FOrdered 

Definition at line 64 of file static_inst.hh.

◆ InterruptTypes

enum SparcISA::InterruptTypes
Enumerator
IT_TRAP_LEVEL_ZERO 
IT_HINTP 
IT_INT_VEC 
IT_CPU_MONDO 
IT_DEV_MONDO 
IT_RES_ERROR 
IT_SOFT_INT 
NumInterruptTypes 

Definition at line 44 of file interrupts.hh.

◆ MiscRegIndex

enum SparcISA::MiscRegIndex
Enumerator
MISCREG_ASI 

Ancillary State Registers.

MISCREG_TICK 
MISCREG_FPRS 
MISCREG_PCR 
MISCREG_PIC 
MISCREG_GSR 
MISCREG_SOFTINT_SET 
MISCREG_SOFTINT_CLR 
MISCREG_SOFTINT 
MISCREG_TICK_CMPR 
MISCREG_STICK 
MISCREG_STICK_CMPR 
MISCREG_TPC 

Privilged Registers.

MISCREG_TNPC 
MISCREG_TSTATE 
MISCREG_TT 
MISCREG_PRIVTICK 
MISCREG_TBA 
MISCREG_PSTATE 
MISCREG_TL 
MISCREG_PIL 
MISCREG_CWP 
MISCREG_GL 
MISCREG_HPSTATE 

Hyper privileged registers.

MISCREG_HTSTATE 
MISCREG_HINTP 
MISCREG_HTBA 
MISCREG_HVER 
MISCREG_STRAND_STS_REG 
MISCREG_HSTICK_CMPR 
MISCREG_FSR 

Floating Point Status Register.

MISCREG_MMU_P_CONTEXT 

MMU Internal Registers.

MISCREG_MMU_S_CONTEXT 
MISCREG_MMU_PART_ID 
MISCREG_MMU_LSU_CTRL 
MISCREG_SCRATCHPAD_R0 

Scratchpad regiscers.

MISCREG_SCRATCHPAD_R1 
MISCREG_SCRATCHPAD_R2 
MISCREG_SCRATCHPAD_R3 
MISCREG_SCRATCHPAD_R4 
MISCREG_SCRATCHPAD_R5 
MISCREG_SCRATCHPAD_R6 
MISCREG_SCRATCHPAD_R7 
MISCREG_QUEUE_CPU_MONDO_HEAD 
MISCREG_QUEUE_CPU_MONDO_TAIL 
MISCREG_QUEUE_DEV_MONDO_HEAD 
MISCREG_QUEUE_DEV_MONDO_TAIL 
MISCREG_QUEUE_RES_ERROR_HEAD 
MISCREG_QUEUE_RES_ERROR_TAIL 
MISCREG_QUEUE_NRES_ERROR_HEAD 
MISCREG_QUEUE_NRES_ERROR_TAIL 
MISCREG_TLB_DATA 
MISCREG_NUMMISCREGS 

Definition at line 37 of file miscregs.hh.

Function Documentation

◆ advancePC()

void SparcISA::advancePC ( PCState &  pc,
const StaticInstPtr &  inst 
)
inline

Definition at line 68 of file utility.hh.

References StaticInst::advancePC(), and MipsISA::pc.

◆ asiIsAsIfUser()

bool SparcISA::asiIsAsIfUser ( ASI  asi)

Definition at line 115 of file asi.cc.

References ASI_AIUP, ASI_AIUP_L, ASI_AIUS, ASI_AIUS_L, ASI_BLK_AIUP, ASI_BLK_AIUP_L, ASI_BLK_AIUS, ASI_BLK_AIUS_L, ASI_LDTX_AIUP, ASI_LDTX_AIUP_L, ASI_LDTX_AIUS, and ASI_LDTX_AIUS_L.

Referenced by SparcISA::TLB::translateData().

◆ asiIsBlock()

bool SparcISA::asiIsBlock ( ASI  asi)

Definition at line 35 of file asi.cc.

References ASI_BLK_AIUP, ASI_BLK_AIUP_L, ASI_BLK_AIUS, ASI_BLK_AIUS_L, ASI_BLK_P, ASI_BLK_PL, ASI_BLK_S, and ASI_BLK_SL.

Referenced by SparcISA::TLB::translateData().

◆ asiIsCmt()

bool SparcISA::asiIsCmt ( ASI  asi)

Definition at line 246 of file asi.cc.

References ASI_CMT_PER_STRAND, and ASI_CMT_SHARED.

Referenced by asiIsReg(), and SparcISA::TLB::translateData().

◆ asiIsDtlb()

bool SparcISA::asiIsDtlb ( ASI  )

◆ asiIsFloatingLoad()

bool SparcISA::asiIsFloatingLoad ( ASI  asi)

Definition at line 217 of file asi.cc.

References ASI_FL16_P, ASI_FL16_PL, ASI_FL16_S, ASI_FL16_SL, ASI_FL8_P, ASI_FL8_PL, ASI_FL8_S, and ASI_FL8_SL.

◆ asiIsHPriv()

bool SparcISA::asiIsHPriv ( ASI  asi)

Definition at line 295 of file asi.cc.

Referenced by SparcISA::TLB::translateData().

◆ asiIsInterrupt()

bool SparcISA::asiIsInterrupt ( ASI  asi)

Definition at line 259 of file asi.cc.

References ASI_SWVR_INTR_RECEIVE, ASI_SWVR_UDB_INTR_R, and ASI_SWVR_UDB_INTR_W.

Referenced by asiIsReg(), and SparcISA::TLB::translateData().

◆ asiIsIO()

bool SparcISA::asiIsIO ( ASI  asi)

Definition at line 132 of file asi.cc.

References ASI_REAL_IO, and ASI_REAL_IO_L.

◆ asiIsLittle()

bool SparcISA::asiIsLittle ( ASI  asi)

Definition at line 150 of file asi.cc.

References ASI_AIUP_L, ASI_AIUS_L, ASI_BLK_AIUP_L, ASI_BLK_AIUS_L, ASI_BLK_PL, ASI_BLK_SL, ASI_FL16_PL, ASI_FL16_SL, ASI_FL8_PL, ASI_FL8_SL, ASI_LDTX_AIUP_L, ASI_LDTX_AIUS_L, ASI_LDTX_NL, ASI_LDTX_PL, ASI_LDTX_REAL_L, ASI_LDTX_SL, ASI_LTX_L, ASI_NL, ASI_PL, ASI_PNFL, ASI_PST16_PL, ASI_PST16_SL, ASI_PST32_PL, ASI_PST32_SL, ASI_PST8_PL, ASI_PST8_SL, ASI_REAL_IO_L, ASI_REAL_L, ASI_SL, and ASI_SNFL.

Referenced by SparcISA::TLB::translateData().

◆ asiIsMmu()

bool SparcISA::asiIsMmu ( ASI  asi)

Definition at line 267 of file asi.cc.

References ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0, ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0, ASI_IMMU, ASI_IMMU_CTXT_NONZERO_CONFIG, ASI_IMMU_CTXT_ZERO_CONFIG, ASI_IMMU_TSB_PS1_PTR_REG, ASI_ITLB_DATA_IN_REG, ASI_LSU_CONTROL_REG, ASI_MMU, and ASI_TLB_INVALIDATE_ALL.

Referenced by asiIsReg(), and SparcISA::TLB::translateData().

◆ asiIsNoFault()

bool SparcISA::asiIsNoFault ( ASI  asi)

Definition at line 230 of file asi.cc.

References ASI_PNF, ASI_PNFL, ASI_SNF, and ASI_SNFL.

Referenced by SparcISA::TLB::translateData().

◆ asiIsNucleus()

bool SparcISA::asiIsNucleus ( ASI  asi)

Definition at line 106 of file asi.cc.

References ASI_LDTX_N, ASI_LDTX_NL, ASI_N, and ASI_NL.

Referenced by SparcISA::TLB::translateData().

◆ asiIsPartialStore()

bool SparcISA::asiIsPartialStore ( ASI  asi)

Definition at line 200 of file asi.cc.

References ASI_PST16_P, ASI_PST16_PL, ASI_PST16_S, ASI_PST16_SL, ASI_PST32_P, ASI_PST32_PL, ASI_PST32_S, ASI_PST32_SL, ASI_PST8_P, ASI_PST8_PL, ASI_PST8_S, and ASI_PST8_SL.

Referenced by SparcISA::TLB::translateData().

◆ asiIsPrimary()

bool SparcISA::asiIsPrimary ( ASI  asi)

Definition at line 48 of file asi.cc.

References ASI_AIUP, ASI_AIUP_L, ASI_BLK_AIUP, ASI_BLK_AIUP_L, ASI_BLK_P, ASI_BLK_PL, ASI_FL16_P, ASI_FL16_PL, ASI_FL8_P, ASI_FL8_PL, ASI_LDTX_AIUP, ASI_LDTX_AIUP_L, ASI_LDTX_P, ASI_LDTX_PL, ASI_P, ASI_PL, ASI_PNF, ASI_PNFL, ASI_PST16_P, ASI_PST16_PL, ASI_PST32_P, ASI_PST32_PL, ASI_PST8_P, and ASI_PST8_PL.

Referenced by SparcISA::TLB::translateData().

◆ asiIsPriv()

bool SparcISA::asiIsPriv ( ASI  asi)

Definition at line 288 of file asi.cc.

◆ asiIsQueue()

bool SparcISA::asiIsQueue ( ASI  asi)

Definition at line 253 of file asi.cc.

References ASI_QUEUE.

Referenced by SparcISA::TLB::translateData().

◆ asiIsReal()

bool SparcISA::asiIsReal ( ASI  asi)

Definition at line 139 of file asi.cc.

References ASI_LDTX_REAL, ASI_LDTX_REAL_L, ASI_REAL, ASI_REAL_IO, ASI_REAL_IO_L, and ASI_REAL_L.

Referenced by SparcISA::FastDataAccessMMUMiss::invoke(), and SparcISA::TLB::translateData().

◆ asiIsReg()

bool SparcISA::asiIsReg ( ASI  asi)

Definition at line 301 of file asi.cc.

References asiIsCmt(), asiIsInterrupt(), asiIsMmu(), asiIsScratchPad(), and asiIsSparcError().

◆ asiIsScratchPad()

bool SparcISA::asiIsScratchPad ( ASI  asi)

Definition at line 239 of file asi.cc.

References ASI_HYP_SCRATCHPAD, and ASI_SCRATCHPAD.

Referenced by asiIsReg(), and SparcISA::TLB::translateData().

◆ asiIsSecondary()

bool SparcISA::asiIsSecondary ( ASI  asi)

Definition at line 77 of file asi.cc.

References ASI_AIUS, ASI_AIUS_L, ASI_BLK_AIUS, ASI_BLK_AIUS_L, ASI_BLK_S, ASI_BLK_SL, ASI_FL16_S, ASI_FL16_SL, ASI_FL8_S, ASI_FL8_SL, ASI_LDTX_AIUS, ASI_LDTX_AIUS_L, ASI_LDTX_S, ASI_LDTX_SL, ASI_PST16_S, ASI_PST16_SL, ASI_PST32_S, ASI_PST32_SL, ASI_PST8_S, ASI_PST8_SL, ASI_S, ASI_SL, ASI_SNF, and ASI_SNFL.

Referenced by SparcISA::TLB::translateData().

◆ asiIsSparcError()

bool SparcISA::asiIsSparcError ( ASI  asi)

Definition at line 309 of file asi.cc.

References ASI_SPARC_ERROR_EN_REG, and ASI_SPARC_ERROR_STATUS_REG.

Referenced by asiIsReg(), and SparcISA::TLB::translateData().

◆ asiIsTwin()

bool SparcISA::asiIsTwin ( ASI  asi)

Definition at line 185 of file asi.cc.

References ASI_LDTX_AIUP, ASI_LDTX_AIUP_L, ASI_LDTX_N, ASI_LDTX_NL, ASI_LDTX_P, ASI_LDTX_PL, ASI_LDTX_S, ASI_LDTX_SL, and ASI_QUEUE.

Referenced by SparcISA::TLB::translateData().

◆ asiIsUnPriv()

bool SparcISA::asiIsUnPriv ( ASI  asi)

Definition at line 282 of file asi.cc.

Referenced by SparcISA::TLB::translateData().

◆ BitUnion64()

SparcISA::BitUnion64 ( HPSTATE  )

◆ buildPstateMask()

static PSTATE SparcISA::buildPstateMask ( )
static

Definition at line 46 of file isa.cc.

References ArmISA::mask.

◆ buildRetPC()

PCState SparcISA::buildRetPC ( const PCState &  curPC,
const PCState &  callPC 
)
inline

Definition at line 45 of file utility.hh.

References GenericISA::SimplePCState< MachInst >::npc(), GenericISA::SimplePCState< MachInst >::pc(), and GenericISA::DelaySlotUPCState< MachInst >::uEnd().

◆ copyMiscRegs()

void SparcISA::copyMiscRegs ( ThreadContext *  src,
ThreadContext *  dest 
)

Definition at line 64 of file utility.cc.

References ArmISA::i, MaxTL, MISCREG_ASI, MISCREG_CWP, MISCREG_FPRS, MISCREG_FSR, MISCREG_GL, MISCREG_HINTP, MISCREG_HPSTATE, MISCREG_HSTICK_CMPR, MISCREG_HTBA, MISCREG_MMU_LSU_CTRL, MISCREG_MMU_P_CONTEXT, MISCREG_MMU_PART_ID, MISCREG_MMU_S_CONTEXT, MISCREG_PIL, MISCREG_PSTATE, MISCREG_QUEUE_CPU_MONDO_HEAD, MISCREG_QUEUE_CPU_MONDO_TAIL, MISCREG_QUEUE_DEV_MONDO_HEAD, MISCREG_QUEUE_DEV_MONDO_TAIL, MISCREG_QUEUE_NRES_ERROR_HEAD, MISCREG_QUEUE_NRES_ERROR_TAIL, MISCREG_QUEUE_RES_ERROR_HEAD, MISCREG_QUEUE_RES_ERROR_TAIL, MISCREG_SCRATCHPAD_R0, MISCREG_SCRATCHPAD_R1, MISCREG_SCRATCHPAD_R2, MISCREG_SCRATCHPAD_R3, MISCREG_SCRATCHPAD_R4, MISCREG_SCRATCHPAD_R5, MISCREG_SCRATCHPAD_R6, MISCREG_SCRATCHPAD_R7, MISCREG_SOFTINT, MISCREG_STICK, MISCREG_STICK_CMPR, MISCREG_STRAND_STS_REG, MISCREG_TBA, MISCREG_TICK, MISCREG_TICK_CMPR, MISCREG_TL, MISCREG_TNPC, MISCREG_TPC, MISCREG_TSTATE, MISCREG_TT, ThreadContext::readMiscRegNoEffect(), ThreadContext::setMiscReg(), ThreadContext::setMiscRegNoEffect(), and MipsISA::tl.

Referenced by copyRegs().

◆ copyRegs()

void SparcISA::copyRegs ( ThreadContext *  src,
ThreadContext *  dest 
)

Definition at line 200 of file utility.cc.

References copyMiscRegs(), ArmISA::i, MaxGL, MISCREG_CWP, MISCREG_GL, NumCCRegs, NumFloatArchRegs, NumIntArchRegs, NumMicroIntRegs, NWindows, ThreadContext::pcState(), ThreadContext::readFloatReg(), ThreadContext::readIntReg(), ThreadContext::readMiscRegNoEffect(), ThreadContext::setFloatReg(), ThreadContext::setIntReg(), ThreadContext::setMiscReg(), and RiscvISA::x.

Referenced by SparcLinux::archClone().

◆ doNormalFault()

void SparcISA::doNormalFault ( ThreadContext *  tc,
TrapType  tt,
bool  gotoHpriv 
)

This sets everything up for a normal trap except for actually jumping to the handler.

Definition at line 379 of file faults.cc.

References INTREG_CANSAVE, INTREG_CCR, ArmISA::mask, MaxGL, MaxPGL, MISCREG_ASI, MISCREG_CWP, MISCREG_GL, MISCREG_HPSTATE, MISCREG_HTSTATE, MISCREG_PSTATE, MISCREG_TL, MISCREG_TNPC, MISCREG_TPC, MISCREG_TSTATE, MISCREG_TT, NWindows, MipsISA::pc, ThreadContext::pcState(), ThreadContext::readIntReg(), ThreadContext::readMiscRegNoEffect(), replaceBits(), ThreadContext::setMiscReg(), and ThreadContext::setMiscRegNoEffect().

Referenced by SparcISA::SparcFaultBase::invoke(), SparcISA::SpillNNormal::invoke(), and SparcISA::FillNNormal::invoke().

◆ doREDFault()

void SparcISA::doREDFault ( ThreadContext *  tc,
TrapType  tt 
)

This sets everything up for a RED state trap except for actually jumping to the handler.

Definition at line 300 of file faults.cc.

References INTREG_CANSAVE, INTREG_CCR, ArmISA::mask, MaxGL, MISCREG_ASI, MISCREG_CWP, MISCREG_GL, MISCREG_HPSTATE, MISCREG_HTSTATE, MISCREG_PSTATE, MISCREG_TL, MISCREG_TNPC, MISCREG_TPC, MISCREG_TSTATE, MISCREG_TT, NWindows, MipsISA::pc, ThreadContext::pcState(), priv, ThreadContext::readIntReg(), ThreadContext::readMiscRegNoEffect(), replaceBits(), ThreadContext::setMiscReg(), and ThreadContext::setMiscRegNoEffect().

Referenced by SparcISA::SparcFaultBase::invoke().

◆ EndBitUnion() [1/2]

SparcISA::EndBitUnion ( HPSTATE  )

Referenced by SparcISA::SparcStaticInst::passesCondition().

◆ EndBitUnion() [2/2]

SparcISA::EndBitUnion ( PSTATE  )

◆ EndSubBitUnion() [1/2]

SparcISA::EndSubBitUnion ( icc  )

Definition at line 148 of file miscregs.hh.

◆ EndSubBitUnion() [2/2]

SparcISA::EndSubBitUnion ( xcc  )

◆ enterREDState()

void SparcISA::enterREDState ( ThreadContext *  tc)

This causes the thread context to enter RED state.

This causes the side effects which go with entering RED state because of a trap.

Definition at line 279 of file faults.cc.

References MISCREG_HPSTATE, MISCREG_PSTATE, ThreadContext::readMiscRegNoEffect(), and ThreadContext::setMiscReg().

Referenced by SparcISA::SparcFaultBase::invoke(), and SparcISA::PowerOnReset::invoke().

◆ getArgument()

uint64_t SparcISA::getArgument ( ThreadContext *  tc,
int &  number,
uint16_t  size,
bool  fp 
)

Definition at line 44 of file utility.cc.

References FullSystem, ThreadContext::getVirtProxy(), ArmISA::NumArgumentRegs, panic, PortProxy::read(), ThreadContext::readIntReg(), ArmISA::sp, and StackPointerReg.

◆ getExecutingAsid()

uint64_t SparcISA::getExecutingAsid ( ThreadContext *  tc)
inline

Definition at line 74 of file utility.hh.

References MISCREG_MMU_P_CONTEXT, and ThreadContext::readMiscRegNoEffect().

◆ getHyperVector()

void SparcISA::getHyperVector ( ThreadContext *  tc,
Addr &  PC,
Addr &  NPC,
RegVal  TT 
)

Definition at line 479 of file faults.cc.

References ArmISA::mask, MISCREG_HTBA, and ThreadContext::readMiscRegNoEffect().

Referenced by SparcISA::SparcFaultBase::invoke().

◆ getPrivVector()

void SparcISA::getPrivVector ( ThreadContext *  tc,
Addr &  PC,
Addr &  NPC,
RegVal  TT,
RegVal  TL 
)

Definition at line 487 of file faults.cc.

References ArmISA::mask, MISCREG_TBA, and ThreadContext::readMiscRegNoEffect().

Referenced by SparcISA::SparcFaultBase::invoke().

◆ getREDVector()

void SparcISA::getREDVector ( RegVal  TT,
Addr &  PC,
Addr &  NPC 
)

Definition at line 470 of file faults.cc.

References ULL.

Referenced by SparcISA::FsWorkload::getEntry(), SparcISA::SparcFaultBase::invoke(), and SparcISA::PowerOnReset::invoke().

◆ getresuidFunc()

SyscallReturn SparcISA::getresuidFunc ( SyscallDesc *  desc,
ThreadContext *  tc,
Addr  ruid,
Addr  euid,
Addr  suid 
)

Definition at line 55 of file syscalls.cc.

References BufferArg::bufferPtr(), BaseBufferArg::copyOut(), ThreadContext::getVirtProxy(), and htobe().

◆ inUserMode()

static bool SparcISA::inUserMode ( ThreadContext *  tc)
inlinestatic

Definition at line 56 of file utility.hh.

References MISCREG_HPSTATE, MISCREG_PSTATE, and ThreadContext::readMiscRegNoEffect().

◆ unameFunc()

static SyscallReturn SparcISA::unameFunc ( SyscallDesc *  desc,
ThreadContext *  tc,
VPtr< Linux::utsname >  name 
)
static

Target uname() handler.

Definition at line 40 of file syscalls.cc.

References ThreadContext::getProcessPtr(), and name().

Variable Documentation

◆ am

Bitfield<3> SparcISA::am

Definition at line 127 of file miscregs.hh.

Referenced by MultiperspectivePerceptron::GHIST::hash(), ArmISA::FsLinux::initState(), SC_MODULE(), and SparcISA::TLB::validVirtualAddress().

◆ c

Bitfield< 0 > SparcISA::c

Definition at line 141 of file miscregs.hh.

Referenced by SparcISA::SparcStaticInst::passesCondition().

◆ cle

Bitfield<9> SparcISA::cle

Definition at line 131 of file miscregs.hh.

◆ CondTestAbbrev

const char * SparcISA::CondTestAbbrev
Initial value:
=
{
[Never] = "nev",
[Equal] = "e",
[LessOrEqual] = "le",
[Less] = "l",
[LessOrEqualUnsigned] = "leu",
[CarrySet] = "c",
[Negative] = "n",
[OverflowSet] = "o",
[Always] = "a",
[NotEqual] = "ne",
[Greater] = "g",
[GreaterOrEqual] = "ge",
[GreaterUnsigned] = "gu",
[CarryClear] = "cc",
[Positive] = "p",
[OverflowClear] = "oc"
}

Definition at line 35 of file static_inst.cc.

◆ EndVAddrHole

const Addr SparcISA::EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF)

Definition at line 46 of file tlb.hh.

Referenced by SparcISA::TLB::validVirtualAddress().

◆ fillHandler32

const MachInst SparcISA::fillHandler32[numFillInsts]

Definition at line 79 of file handlers.hh.

Referenced by Sparc32Process::argsInit().

◆ fillHandler64

const MachInst SparcISA::fillHandler64[numFillInsts]

Definition at line 43 of file handlers.hh.

Referenced by Sparc64Process::argsInit().

◆ FramePointerReg

const int SparcISA::FramePointerReg = INTREG_I6

Definition at line 96 of file registers.hh.

Referenced by SparcISA::SparcStaticInst::printReg().

◆ GuestByteOrder

const ByteOrder SparcISA::GuestByteOrder = ByteOrder::big

Definition at line 37 of file isa_traits.hh.

◆ hpriv

Bitfield<2> SparcISA::hpriv

Definition at line 118 of file miscregs.hh.

Referenced by SparcISA::FastDataAccessMMUMiss::invoke(), SparcISA::TLB::translateData(), SparcISA::TLB::translateFunctional(), and SparcISA::TLB::translateInst().

◆ ibe

Bitfield<10> SparcISA::ibe

Definition at line 120 of file miscregs.hh.

◆ id

Bitfield<11> SparcISA::id

Definition at line 121 of file miscregs.hh.

◆ MaxGL

const int SparcISA::MaxGL = 3

Definition at line 37 of file sparc_traits.hh.

Referenced by copyRegs(), doNormalFault(), doREDFault(), and SparcISA::PowerOnReset::invoke().

◆ MaxPGL

const int SparcISA::MaxPGL = 2

Definition at line 38 of file sparc_traits.hh.

Referenced by doNormalFault().

◆ MaxPTL

const int SparcISA::MaxPTL = 2

Definition at line 35 of file sparc_traits.hh.

Referenced by SparcISA::SparcFaultBase::invoke().

◆ MaxTL

const int SparcISA::MaxTL = 6

Definition at line 36 of file sparc_traits.hh.

Referenced by copyMiscRegs(), SparcISA::SparcFaultBase::invoke(), SparcISA::PowerOnReset::invoke(), SparcISA::ISA::readFSReg(), SparcISA::ISA::serialize(), and SparcISA::ISA::unserialize().

◆ mm

Bitfield<7, 6> SparcISA::mm

Definition at line 129 of file miscregs.hh.

Referenced by QTIsaac< ALPHA >::isaac().

◆ n

Bitfield< 3 > SparcISA::n

Definition at line 137 of file miscregs.hh.

Referenced by SparcISA::SparcStaticInst::passesCondition().

◆ NumCCRegs

const int SparcISA::NumCCRegs = 0

Definition at line 106 of file registers.hh.

Referenced by copyRegs().

◆ numFillInsts

const int SparcISA::numFillInsts = 32

Definition at line 40 of file handlers.hh.

Referenced by SparcProcess::argsInit(), Sparc32Process::argsInit(), and Sparc64Process::argsInit().

◆ NumFloatArchRegs

const int SparcISA::NumFloatArchRegs = NumFloatRegs

Definition at line 109 of file registers.hh.

Referenced by copyRegs().

◆ NumFloatRegs

const int SparcISA::NumFloatRegs = 64

Definition at line 108 of file registers.hh.

◆ NumIntRegs

const int SparcISA::NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs

Definition at line 101 of file registers.hh.

Referenced by SparcISA::ISA::flattenIntIndex(), SparcISA::ISA::installGlobals(), and SparcISA::ISA::installWindow().

◆ NumMiscRegs

const int SparcISA::NumMiscRegs = MISCREG_NUMMISCREGS

Definition at line 170 of file miscregs.hh.

Referenced by getMiscRegName().

◆ numSpillInsts

const int SparcISA::numSpillInsts = 32

Definition at line 41 of file handlers.hh.

Referenced by Sparc32Process::argsInit(), and Sparc64Process::argsInit().

◆ NumVecElemPerVecReg

constexpr unsigned SparcISA::NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg
constexpr

Definition at line 51 of file registers.hh.

◆ NumVecPredRegs

const int SparcISA::NumVecPredRegs = 1

Definition at line 104 of file registers.hh.

◆ NumVecRegs

const int SparcISA::NumVecRegs = 1

Definition at line 102 of file registers.hh.

◆ NWindows

const int SparcISA::NWindows = 8

Definition at line 41 of file sparc_traits.hh.

Referenced by SparcLinux::archClone(), copyRegs(), doNormalFault(), doREDFault(), Sparc32Process::flushWindows(), Sparc64Process::flushWindows(), SparcProcess::initState(), SparcISA::ISA::readFSReg(), SparcISA::ISA::reloadRegMap(), and SparcISA::ISA::setMiscReg().

◆ PAddrImplMask

const Addr SparcISA::PAddrImplMask = ULL(0x000000FFFFFFFFFF)

Definition at line 48 of file tlb.hh.

Referenced by SparcISA::TLB::translateData(), and SparcISA::TLB::translateInst().

◆ PageBytes

const Addr SparcISA::PageBytes = ULL(1) << PageShift

Definition at line 40 of file isa_traits.hh.

Referenced by SparcProcess::argsInit(), Sparc32Process::Sparc32Process(), and Sparc64Process::Sparc64Process().

◆ PageShift

const Addr SparcISA::PageShift = 13

Definition at line 39 of file isa_traits.hh.

◆ pef

Bitfield<4> SparcISA::pef

Definition at line 128 of file miscregs.hh.

◆ pid0

Bitfield<10> SparcISA::pid0

Definition at line 132 of file miscregs.hh.

◆ pid1

Bitfield<11> SparcISA::pid1

Definition at line 133 of file miscregs.hh.

◆ priv

Bitfield<2> SparcISA::priv

Definition at line 126 of file miscregs.hh.

Referenced by doREDFault(), PacketFifoEntry::serialize(), SparcISA::TLB::translateData(), SparcISA::TLB::translateInst(), and PacketFifoEntry::unserialize().

◆ PstateMask

const PSTATE SparcISA::PstateMask = buildPstateMask()
static

Definition at line 60 of file isa.cc.

Referenced by SparcISA::ISA::setMiscReg(), and SparcISA::ISA::setMiscRegNoEffect().

◆ red

Bitfield<5> SparcISA::red

Definition at line 119 of file miscregs.hh.

Referenced by SparcISA::FastDataAccessMMUMiss::invoke(), TEST(), SparcISA::TLB::translateData(), and SparcISA::TLB::translateInst().

◆ ReturnAddressReg

const int SparcISA::ReturnAddressReg = INTREG_I7

Definition at line 93 of file registers.hh.

◆ ReturnValueReg

const int SparcISA::ReturnValueReg = INTREG_O0

Definition at line 94 of file registers.hh.

Referenced by GuestABI::Result< ABI, SyscallReturn, typename std::enable_if< std::is_base_of< SparcProcess::SyscallABI, ABI >::value >::type >::store().

◆ spillHandler32

const MachInst SparcISA::spillHandler32[numSpillInsts]

Definition at line 151 of file handlers.hh.

Referenced by Sparc32Process::argsInit().

◆ spillHandler64

const MachInst SparcISA::spillHandler64[numSpillInsts]

Definition at line 115 of file handlers.hh.

Referenced by Sparc64Process::argsInit().

◆ StackPointerReg

const int SparcISA::StackPointerReg = INTREG_O6

Definition at line 95 of file registers.hh.

Referenced by SparcLinux::archClone(), getArgument(), and SparcISA::SparcStaticInst::printReg().

◆ StartVAddrHole

const Addr SparcISA::StartVAddrHole = ULL(0x0000800000000000)

Definition at line 45 of file tlb.hh.

Referenced by SparcISA::TLB::validVirtualAddress().

◆ SyscallPseudoReturnReg

const int SparcISA::SyscallPseudoReturnReg = INTREG_O1

Definition at line 99 of file registers.hh.

Referenced by GuestABI::Result< ABI, SyscallReturn, typename std::enable_if< std::is_base_of< SparcProcess::SyscallABI, ABI >::value >::type >::store().

◆ tle

Bitfield<8> SparcISA::tle

Definition at line 130 of file miscregs.hh.

◆ TotalNumRegs

const int SparcISA::TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs

Definition at line 111 of file registers.hh.

◆ v

Bitfield< 1 > SparcISA::v

Definition at line 140 of file miscregs.hh.

Referenced by SparcISA::SparcStaticInst::passesCondition().

◆ VAddrAMask

const Addr SparcISA::VAddrAMask = ULL(0xFFFFFFFF)

Definition at line 47 of file tlb.hh.

Referenced by SparcISA::TLB::translateData(), SparcISA::TLB::translateFunctional(), and SparcISA::TLB::translateInst().

◆ VecPredRegHasPackedRepr

constexpr bool SparcISA::VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr
constexpr

Definition at line 59 of file registers.hh.

◆ VecPredRegSizeBits

constexpr size_t SparcISA::VecPredRegSizeBits = ::DummyVecPredRegSizeBits
constexpr

Definition at line 58 of file registers.hh.

◆ VecRegSizeBytes

constexpr size_t SparcISA::VecRegSizeBytes = ::DummyVecRegSizeBytes
constexpr

Definition at line 52 of file registers.hh.

◆ z

Bitfield< 2 > SparcISA::z

Definition at line 139 of file miscregs.hh.

Referenced by SparcISA::SparcStaticInst::passesCondition().

◆ ZeroReg

const int SparcISA::ZeroReg = 0

Definition at line 90 of file registers.hh.

SparcISA::Equal
@ Equal
Definition: static_inst.hh:47
SparcISA::CarryClear
@ CarryClear
Definition: static_inst.hh:54
SparcISA::Negative
@ Negative
Definition: static_inst.hh:57
SparcISA::LessOrEqualUnsigned
@ LessOrEqualUnsigned
Definition: static_inst.hh:53
SparcISA::Never
@ Never
Definition: static_inst.hh:45
SparcISA::GreaterUnsigned
@ GreaterUnsigned
Definition: static_inst.hh:52
SparcISA::Greater
@ Greater
Definition: static_inst.hh:48
SparcISA::OverflowClear
@ OverflowClear
Definition: static_inst.hh:58
SparcISA::GreaterOrEqual
@ GreaterOrEqual
Definition: static_inst.hh:50
SparcISA::Less
@ Less
Definition: static_inst.hh:51
SparcISA::NotEqual
@ NotEqual
Definition: static_inst.hh:46
SparcISA::CarrySet
@ CarrySet
Definition: static_inst.hh:55
SparcISA::Always
@ Always
Definition: static_inst.hh:44
SparcISA::OverflowSet
@ OverflowSet
Definition: static_inst.hh:59
SparcISA::LessOrEqual
@ LessOrEqual
Definition: static_inst.hh:49
SparcISA::Positive
@ Positive
Definition: static_inst.hh:56
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