gem5
v20.1.0.0
dev
i2c
device.hh
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2012 ARM Limited
3
* All rights reserved
4
*
5
* The license below extends only to copyright in the software and shall
6
* not be construed as granting a license to any other intellectual
7
* property including but not limited to intellectual property relating
8
* to a hardware implementation of the functionality of the software
9
* licensed hereunder. You may use the software subject to the license
10
* terms below provided that you ensure that this notice is replicated
11
* unmodified and in its entirety in all distributions of the software,
12
* modified or unmodified, in source code or in binary form.
13
*
14
* Redistribution and use in source and binary forms, with or without
15
* modification, are permitted provided that the following conditions are
16
* met: redistributions of source code must retain the above copyright
17
* notice, this list of conditions and the following disclaimer;
18
* redistributions in binary form must reproduce the above copyright
19
* notice, this list of conditions and the following disclaimer in the
20
* documentation and/or other materials provided with the distribution;
21
* neither the name of the copyright holders nor the names of its
22
* contributors may be used to endorse or promote products derived from
23
* this software without specific prior written permission.
24
*
25
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.*
36
*/
37
38
43
#ifndef __DEV_I2C_DEVICE_HH__
44
#define __DEV_I2C_DEVICE_HH__
45
46
#include "
base/types.hh
"
47
#include "params/I2CDevice.hh"
48
#include "
sim/sim_object.hh
"
49
50
class
I2CDevice
:
public
SimObject
51
{
52
53
protected
:
54
55
uint8_t
_addr
;
56
57
public
:
58
59
I2CDevice
(
const
I2CDeviceParams*
p
)
60
:
SimObject
(
p
),
_addr
(
p
->i2c_addr)
61
{ }
62
63
virtual
~I2CDevice
() { }
64
72
virtual
uint8_t
read
() = 0;
73
81
virtual
void
write
(uint8_t msg) = 0;
82
88
virtual
void
i2cStart
() = 0;
89
90
uint8_t
i2cAddr
()
const
{
return
_addr
; }
91
92
};
93
94
#endif // __DEV_I2C_DEVICE__
I2CDevice
Definition:
device.hh:50
I2CDevice::i2cAddr
uint8_t i2cAddr() const
Definition:
device.hh:90
I2CDevice::read
virtual uint8_t read()=0
Return the next message that the device expects to send.
I2CDevice::write
virtual void write(uint8_t msg)=0
Perform any actions triggered by an i2c write (save msg in a register, perform an interrupt,...
sim_object.hh
I2CDevice::~I2CDevice
virtual ~I2CDevice()
Definition:
device.hh:63
types.hh
MipsISA::p
Bitfield< 0 > p
Definition:
pra_constants.hh:323
I2CDevice::I2CDevice
I2CDevice(const I2CDeviceParams *p)
Definition:
device.hh:59
I2CDevice::i2cStart
virtual void i2cStart()=0
Perform any initialization necessary for the device when it received a start signal from the bus mast...
I2CDevice::_addr
uint8_t _addr
Definition:
device.hh:55
SimObject
Abstract superclass for simulation objects.
Definition:
sim_object.hh:92
Generated on Wed Sep 30 2020 14:02:08 for gem5 by
doxygen
1.8.17