registers.hh File Reference

#include <array>
#include <cstdint>
#include <string>
#include "arch/generic/vec_reg.hh"
#include "base/intmath.hh"
#include "base/logging.hh"

Go to the source code of this file.

Classes
struct	Gcn3ISA::StatusReg

Namespaces
	Gcn3ISA
	classes that represnt vector/scalar operands in GCN3 ISA.

Typedefs
typedef uint8_t	Gcn3ISA::ScalarRegU8
typedef int8_t	Gcn3ISA::ScalarRegI8
typedef uint16_t	Gcn3ISA::ScalarRegU16
typedef int16_t	Gcn3ISA::ScalarRegI16
typedef uint32_t	Gcn3ISA::ScalarRegU32
typedef int32_t	Gcn3ISA::ScalarRegI32
typedef float	Gcn3ISA::ScalarRegF32
typedef uint64_t	Gcn3ISA::ScalarRegU64
typedef int64_t	Gcn3ISA::ScalarRegI64
typedef double	Gcn3ISA::ScalarRegF64
typedef uint8_t	Gcn3ISA::VecElemU8
typedef int8_t	Gcn3ISA::VecElemI8
typedef uint16_t	Gcn3ISA::VecElemU16
typedef int16_t	Gcn3ISA::VecElemI16
typedef uint32_t	Gcn3ISA::VecElemU32
typedef int32_t	Gcn3ISA::VecElemI32
typedef float	Gcn3ISA::VecElemF32
typedef uint64_t	Gcn3ISA::VecElemU64
typedef int64_t	Gcn3ISA::VecElemI64
typedef double	Gcn3ISA::VecElemF64
using	Gcn3ISA::VecRegU8 = ::VecRegT< VecElemU8, NumVecElemPerVecReg, false >
using	Gcn3ISA::VecRegI8 = ::VecRegT< VecElemI8, NumVecElemPerVecReg, false >
using	Gcn3ISA::VecRegU16 = ::VecRegT< VecElemU16, NumVecElemPerVecReg, false >
using	Gcn3ISA::VecRegI16 = ::VecRegT< VecElemI16, NumVecElemPerVecReg, false >
using	Gcn3ISA::VecRegU32 = ::VecRegT< VecElemU32, NumVecElemPerVecReg, false >
using	Gcn3ISA::VecRegI32 = ::VecRegT< VecElemI32, NumVecElemPerVecReg, false >
using	Gcn3ISA::VecRegF32 = ::VecRegT< VecElemF32, NumVecElemPerVecReg, false >
using	Gcn3ISA::VecRegU64 = ::VecRegT< VecElemU64, NumVecElemPerVecReg, false >
using	Gcn3ISA::VecRegI64 = ::VecRegT< VecElemI64, NumVecElemPerVecReg, false >
using	Gcn3ISA::VecRegF64 = ::VecRegT< VecElemF64, NumVecElemPerVecReg, false >
using	Gcn3ISA::ConstVecRegU8 = ::VecRegT< VecElemU8, NumVecElemPerVecReg, true >
using	Gcn3ISA::ConstVecRegI8 = ::VecRegT< VecElemI8, NumVecElemPerVecReg, true >
using	Gcn3ISA::ConstVecRegU16 = ::VecRegT< VecElemU16, NumVecElemPerVecReg, true >
using	Gcn3ISA::ConstVecRegI16 = ::VecRegT< VecElemI16, NumVecElemPerVecReg, true >
using	Gcn3ISA::ConstVecRegU32 = ::VecRegT< VecElemU32, NumVecElemPerVecReg, true >
using	Gcn3ISA::ConstVecRegI32 = ::VecRegT< VecElemI32, NumVecElemPerVecReg, true >
using	Gcn3ISA::ConstVecRegF32 = ::VecRegT< VecElemF32, NumVecElemPerVecReg, true >
using	Gcn3ISA::ConstVecRegU64 = ::VecRegT< VecElemU64, NumVecElemPerVecReg, true >
using	Gcn3ISA::ConstVecRegI64 = ::VecRegT< VecElemI64, NumVecElemPerVecReg, true >
using	Gcn3ISA::ConstVecRegF64 = ::VecRegT< VecElemF64, NumVecElemPerVecReg, true >
using	Gcn3ISA::VecRegContainerU8 = VecRegU8::Container
using	Gcn3ISA::VecRegContainerU16 = VecRegU16::Container
using	Gcn3ISA::VecRegContainerU32 = VecRegU32::Container
using	Gcn3ISA::VecRegContainerU64 = VecRegU64::Container

Enumerations
enum	Gcn3ISA::OpSelector : int {   Gcn3ISA::REG_SGPR_MIN = 0, Gcn3ISA::REG_SGPR_MAX = 101, Gcn3ISA::REG_FLAT_SCRATCH_LO = 102, Gcn3ISA::REG_FLAT_SCRATCH_HI = 103,   Gcn3ISA::REG_XNACK_MASK_LO = 104, Gcn3ISA::REG_XNACK_MASK_HI = 105, Gcn3ISA::REG_VCC_LO = 106, Gcn3ISA::REG_VCC_HI = 107,   Gcn3ISA::REG_TBA_LO = 108, Gcn3ISA::REG_TBA_HI = 109, Gcn3ISA::REG_TMA_LO = 110, Gcn3ISA::REG_TMA_HI = 111,   Gcn3ISA::REG_TTMP_0 = 112, Gcn3ISA::REG_TTMP_1 = 113, Gcn3ISA::REG_TTMP_2 = 114, Gcn3ISA::REG_TTMP_3 = 115,   Gcn3ISA::REG_TTMP_4 = 116, Gcn3ISA::REG_TTMP_5 = 117, Gcn3ISA::REG_TTMP_6 = 118, Gcn3ISA::REG_TTMP_7 = 119,   Gcn3ISA::REG_TTMP_8 = 120, Gcn3ISA::REG_TTMP_9 = 121, Gcn3ISA::REG_TTMP_10 = 122, Gcn3ISA::REG_TTMP_11 = 123,   Gcn3ISA::REG_M0 = 124, Gcn3ISA::REG_RESERVED_1 = 125, Gcn3ISA::REG_EXEC_LO = 126, Gcn3ISA::REG_EXEC_HI = 127,   Gcn3ISA::REG_ZERO = 128, Gcn3ISA::REG_INT_CONST_POS_MIN = 129, Gcn3ISA::REG_INT_CONST_POS_MAX = 192, Gcn3ISA::REG_INT_CONST_NEG_MIN = 193,   Gcn3ISA::REG_INT_CONST_NEG_MAX = 208, Gcn3ISA::REG_RESERVED_2 = 209, Gcn3ISA::REG_RESERVED_3 = 210, Gcn3ISA::REG_RESERVED_4 = 211,   Gcn3ISA::REG_RESERVED_5 = 212, Gcn3ISA::REG_RESERVED_6 = 213, Gcn3ISA::REG_RESERVED_7 = 214, Gcn3ISA::REG_RESERVED_8 = 215,   Gcn3ISA::REG_RESERVED_9 = 216, Gcn3ISA::REG_RESERVED_10 = 217, Gcn3ISA::REG_RESERVED_11 = 218, Gcn3ISA::REG_RESERVED_12 = 219,   Gcn3ISA::REG_RESERVED_13 = 220, Gcn3ISA::REG_RESERVED_14 = 221, Gcn3ISA::REG_RESERVED_15 = 222, Gcn3ISA::REG_RESERVED_16 = 223,   Gcn3ISA::REG_RESERVED_17 = 224, Gcn3ISA::REG_RESERVED_18 = 225, Gcn3ISA::REG_RESERVED_19 = 226, Gcn3ISA::REG_RESERVED_20 = 227,   Gcn3ISA::REG_RESERVED_21 = 228, Gcn3ISA::REG_RESERVED_22 = 229, Gcn3ISA::REG_RESERVED_23 = 230, Gcn3ISA::REG_RESERVED_24 = 231,   Gcn3ISA::REG_RESERVED_25 = 232, Gcn3ISA::REG_RESERVED_26 = 233, Gcn3ISA::REG_RESERVED_27 = 234, Gcn3ISA::REG_RESERVED_28 = 235,   Gcn3ISA::REG_RESERVED_29 = 236, Gcn3ISA::REG_RESERVED_30 = 237, Gcn3ISA::REG_RESERVED_31 = 238, Gcn3ISA::REG_RESERVED_32 = 239,   Gcn3ISA::REG_POS_HALF = 240, Gcn3ISA::REG_NEG_HALF = 241, Gcn3ISA::REG_POS_ONE = 242, Gcn3ISA::REG_NEG_ONE = 243,   Gcn3ISA::REG_POS_TWO = 244, Gcn3ISA::REG_NEG_TWO = 245, Gcn3ISA::REG_POS_FOUR = 246, Gcn3ISA::REG_NEG_FOUR = 247,   Gcn3ISA::REG_PI = 248, Gcn3ISA::REG_SRC_SWDA = 249, Gcn3ISA::REG_SRC_DPP = 250, Gcn3ISA::REG_VCCZ = 251,   Gcn3ISA::REG_EXECZ = 252, Gcn3ISA::REG_SCC = 253, Gcn3ISA::REG_LDS_DIRECT = 254, Gcn3ISA::REG_SRC_LITERAL = 255,   Gcn3ISA::REG_VGPR_MIN = 256, Gcn3ISA::REG_VGPR_MAX = 511 }

Functions
constexpr size_t	Gcn3ISA::MaxOperandDwords (16)
const int	Gcn3ISA::NumVecElemPerVecReg (64)
std::string	Gcn3ISA::opSelectorToRegSym (int idx, int numRegs)
int	Gcn3ISA::opSelectorToRegIdx (int idx, int numScalarRegs)
bool	Gcn3ISA::isPosConstVal (int opIdx)
bool	Gcn3ISA::isNegConstVal (int opIdx)
bool	Gcn3ISA::isConstVal (int opIdx)
bool	Gcn3ISA::isLiteral (int opIdx)
bool	Gcn3ISA::isScalarReg (int opIdx)
bool	Gcn3ISA::isVectorReg (int opIdx)
bool	Gcn3ISA::isFlatScratchReg (int opIdx)
bool	Gcn3ISA::isExecMask (int opIdx)
bool	Gcn3ISA::isVccReg (int opIdx)

Variables
const int	Gcn3ISA::NumPosConstRegs
const int	Gcn3ISA::NumNegConstRegs
const int	Gcn3ISA::BITS_PER_BYTE = 8
const int	Gcn3ISA::BITS_PER_WORD = 16
const int	Gcn3ISA::MSB_PER_BYTE = (BITS_PER_BYTE - 1)
const int	Gcn3ISA::MSB_PER_WORD = (BITS_PER_WORD - 1)