gem5  v20.1.0.0
registers.hh
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35 
36 #ifndef __ARCH_GCN3_REGISTERS_HH__
37 #define __ARCH_GCN3_REGISTERS_HH__
38 
39 #include <array>
40 #include <cstdint>
41 #include <string>
42 
43 #include "arch/generic/vec_reg.hh"
44 #include "base/intmath.hh"
45 #include "base/logging.hh"
46 
47 namespace Gcn3ISA
48 {
49  enum OpSelector : int
50  {
52  REG_SGPR_MAX = 101,
57  REG_VCC_LO = 106,
58  REG_VCC_HI = 107,
59  REG_TBA_LO = 108,
60  REG_TBA_HI = 109,
61  REG_TMA_LO = 110,
62  REG_TMA_HI = 111,
63  REG_TTMP_0 = 112,
64  REG_TTMP_1 = 113,
65  REG_TTMP_2 = 114,
66  REG_TTMP_3 = 115,
67  REG_TTMP_4 = 116,
68  REG_TTMP_5 = 117,
69  REG_TTMP_6 = 118,
70  REG_TTMP_7 = 119,
71  REG_TTMP_8 = 120,
72  REG_TTMP_9 = 121,
73  REG_TTMP_10 = 122,
74  REG_TTMP_11 = 123,
75  REG_M0 = 124,
77  REG_EXEC_LO = 126,
78  REG_EXEC_HI = 127,
79  REG_ZERO = 128,
117  REG_POS_ONE = 242,
118  REG_NEG_ONE = 243,
119  REG_POS_TWO = 244,
120  REG_NEG_TWO = 245,
123  REG_PI = 248,
124  /* NOTE: SDWA and SWDA both refer to sub d-word addressing */
126  REG_SRC_DPP = 250,
127  REG_VCCZ = 251,
128  REG_EXECZ = 252,
129  REG_SCC = 253,
134  };
135 
136  constexpr size_t MaxOperandDwords(16);
137  const int NumVecElemPerVecReg(64);
138  // op selector values 129 - 192 correspond to const values 1 - 64
140  - REG_INT_CONST_POS_MIN + 1;
141  // op selector values 193 - 208 correspond to const values -1 - 16
143  - REG_INT_CONST_NEG_MIN + 1;
144  const int BITS_PER_BYTE = 8;
145  const int BITS_PER_WORD = 16;
146  const int MSB_PER_BYTE = (BITS_PER_BYTE - 1);
147  const int MSB_PER_WORD = (BITS_PER_WORD - 1);
148 
149  // typedefs for the various sizes/types of scalar regs
150  typedef uint8_t ScalarRegU8;
151  typedef int8_t ScalarRegI8;
152  typedef uint16_t ScalarRegU16;
153  typedef int16_t ScalarRegI16;
154  typedef uint32_t ScalarRegU32;
155  typedef int32_t ScalarRegI32;
156  typedef float ScalarRegF32;
157  typedef uint64_t ScalarRegU64;
158  typedef int64_t ScalarRegI64;
159  typedef double ScalarRegF64;
160 
161  // typedefs for the various sizes/types of vector reg elements
162  typedef uint8_t VecElemU8;
163  typedef int8_t VecElemI8;
164  typedef uint16_t VecElemU16;
165  typedef int16_t VecElemI16;
166  typedef uint32_t VecElemU32;
167  typedef int32_t VecElemI32;
168  typedef float VecElemF32;
169  typedef uint64_t VecElemU64;
170  typedef int64_t VecElemI64;
171  typedef double VecElemF64;
172 
173  // typedefs for the various sizes/types of vector regs
184  // non-writeable versions of vector regs
195 
200 
201  struct StatusReg
202  {
203  StatusReg() : SCC(0), SPI_PRIO(0), USER_PRIO(0), PRIV(0), TRAP_EN(0),
204  TTRACE_EN(0), EXPORT_RDY(0), EXECZ(0), VCCZ(0), IN_TG(0),
205  IN_BARRIER(0), HALT(0), TRAP(0), TTRACE_CU_EN(0), VALID(0),
206  ECC_ERR(0), SKIP_EXPORT(0), PERF_EN(0), COND_DBG_USER(0),
208  MUST_EXPORT(0), RESERVED_1(0)
209  {
210  }
211 
212  uint32_t SCC : 1;
213  uint32_t SPI_PRIO : 2;
214  uint32_t USER_PRIO : 2;
215  uint32_t PRIV : 1;
216  uint32_t TRAP_EN : 1;
217  uint32_t TTRACE_EN : 1;
218  uint32_t EXPORT_RDY : 1;
219  uint32_t EXECZ : 1;
220  uint32_t VCCZ : 1;
221  uint32_t IN_TG : 1;
222  uint32_t IN_BARRIER : 1;
223  uint32_t HALT : 1;
224  uint32_t TRAP : 1;
225  uint32_t TTRACE_CU_EN : 1;
226  uint32_t VALID : 1;
227  uint32_t ECC_ERR : 1;
228  uint32_t SKIP_EXPORT : 1;
229  uint32_t PERF_EN : 1;
230  uint32_t COND_DBG_USER : 1;
231  uint32_t COND_DBG_SYS : 1;
232  uint32_t ALLOW_REPLAY : 1;
233  uint32_t INSTRUCTION_ATC : 1;
234  uint32_t RESERVED : 3;
235  uint32_t MUST_EXPORT : 1;
236  uint32_t RESERVED_1 : 4;
237  };
238 
239  std::string opSelectorToRegSym(int opIdx, int numRegs=0);
240  int opSelectorToRegIdx(int opIdx, int numScalarRegs);
241  bool isPosConstVal(int opIdx);
242  bool isNegConstVal(int opIdx);
243  bool isConstVal(int opIdx);
244  bool isLiteral(int opIdx);
245  bool isScalarReg(int opIdx);
246  bool isVectorReg(int opIdx);
247  bool isFlatScratchReg(int opIdx);
248  bool isExecMask(int opIdx);
249  bool isVccReg(int opIdx);
250 } // namespace Gcn3ISA
251 
252 #endif // __ARCH_GCN3_REGISTERS_HH__
Gcn3ISA::REG_EXECZ
@ REG_EXECZ
Definition: registers.hh:128
Gcn3ISA::VecElemU16
uint16_t VecElemU16
Definition: registers.hh:164
Gcn3ISA::REG_SRC_DPP
@ REG_SRC_DPP
Definition: registers.hh:126
Gcn3ISA::NumVecElemPerVecReg
const int NumVecElemPerVecReg(64)
Gcn3ISA::REG_TMA_LO
@ REG_TMA_LO
Definition: registers.hh:61
Gcn3ISA::REG_POS_FOUR
@ REG_POS_FOUR
Definition: registers.hh:121
Gcn3ISA::REG_VCC_HI
@ REG_VCC_HI
Definition: registers.hh:58
Gcn3ISA::OpSelector
OpSelector
Definition: registers.hh:49
Gcn3ISA::StatusReg::SKIP_EXPORT
uint32_t SKIP_EXPORT
Definition: registers.hh:228
Gcn3ISA::REG_RESERVED_32
@ REG_RESERVED_32
Definition: registers.hh:114
Gcn3ISA::REG_TTMP_10
@ REG_TTMP_10
Definition: registers.hh:73
Gcn3ISA::StatusReg::MUST_EXPORT
uint32_t MUST_EXPORT
Definition: registers.hh:235
Gcn3ISA::StatusReg::EXECZ
uint32_t EXECZ
Definition: registers.hh:219
Gcn3ISA::REG_TMA_HI
@ REG_TMA_HI
Definition: registers.hh:62
Gcn3ISA::REG_TBA_HI
@ REG_TBA_HI
Definition: registers.hh:60
Gcn3ISA::isFlatScratchReg
bool isFlatScratchReg(int opIdx)
Definition: registers.cc:211
Gcn3ISA::REG_RESERVED_16
@ REG_RESERVED_16
Definition: registers.hh:98
Gcn3ISA::ScalarRegF64
double ScalarRegF64
Definition: registers.hh:159
Gcn3ISA::REG_INT_CONST_POS_MIN
@ REG_INT_CONST_POS_MIN
Definition: registers.hh:80
Gcn3ISA::ScalarRegI64
int64_t ScalarRegI64
Definition: registers.hh:158
Gcn3ISA::StatusReg::SPI_PRIO
uint32_t SPI_PRIO
Definition: registers.hh:213
Gcn3ISA::isScalarReg
bool isScalarReg(int opIdx)
Definition: registers.cc:217
Gcn3ISA::BITS_PER_BYTE
const int BITS_PER_BYTE
Definition: registers.hh:144
Gcn3ISA::REG_VCCZ
@ REG_VCCZ
Definition: registers.hh:127
Gcn3ISA::ScalarRegU8
uint8_t ScalarRegU8
Definition: registers.hh:150
Gcn3ISA::StatusReg::VALID
uint32_t VALID
Definition: registers.hh:226
Gcn3ISA::REG_VGPR_MAX
@ REG_VGPR_MAX
Definition: registers.hh:133
Gcn3ISA::REG_RESERVED_30
@ REG_RESERVED_30
Definition: registers.hh:112
Gcn3ISA::REG_RESERVED_1
@ REG_RESERVED_1
Definition: registers.hh:76
Gcn3ISA::REG_RESERVED_24
@ REG_RESERVED_24
Definition: registers.hh:106
Gcn3ISA::REG_TTMP_11
@ REG_TTMP_11
Definition: registers.hh:74
Gcn3ISA::REG_FLAT_SCRATCH_LO
@ REG_FLAT_SCRATCH_LO
Definition: registers.hh:53
Gcn3ISA::REG_POS_HALF
@ REG_POS_HALF
Definition: registers.hh:115
Gcn3ISA::ScalarRegF32
float ScalarRegF32
Definition: registers.hh:156
Gcn3ISA::ScalarRegU64
uint64_t ScalarRegU64
Definition: registers.hh:157
Gcn3ISA::REG_RESERVED_20
@ REG_RESERVED_20
Definition: registers.hh:102
Gcn3ISA::REG_RESERVED_27
@ REG_RESERVED_27
Definition: registers.hh:109
Gcn3ISA::ScalarRegI16
int16_t ScalarRegI16
Definition: registers.hh:153
Gcn3ISA::StatusReg::HALT
uint32_t HALT
Definition: registers.hh:223
Gcn3ISA::REG_RESERVED_25
@ REG_RESERVED_25
Definition: registers.hh:107
Gcn3ISA::VecElemI8
int8_t VecElemI8
Definition: registers.hh:163
Gcn3ISA::StatusReg::PRIV
uint32_t PRIV
Definition: registers.hh:215
Gcn3ISA::REG_RESERVED_29
@ REG_RESERVED_29
Definition: registers.hh:111
Gcn3ISA::REG_VCC_LO
@ REG_VCC_LO
Definition: registers.hh:57
Gcn3ISA::REG_EXEC_LO
@ REG_EXEC_LO
Definition: registers.hh:77
Gcn3ISA::NumNegConstRegs
const int NumNegConstRegs
Definition: registers.hh:142
Gcn3ISA::isExecMask
bool isExecMask(int opIdx)
Definition: registers.cc:199
Gcn3ISA::VecElemU32
uint32_t VecElemU32
Definition: registers.hh:166
Gcn3ISA::REG_TTMP_7
@ REG_TTMP_7
Definition: registers.hh:70
Gcn3ISA::isVectorReg
bool isVectorReg(int opIdx)
Definition: registers.cc:230
Gcn3ISA::REG_RESERVED_11
@ REG_RESERVED_11
Definition: registers.hh:93
VecRegT::Container
typename std::conditional< Const, const VecRegContainer< size()>, VecRegContainer< size()> >::type Container
Container type alias.
Definition: vec_reg.hh:182
Gcn3ISA::StatusReg::RESERVED
uint32_t RESERVED
Definition: registers.hh:234
Gcn3ISA::REG_VGPR_MIN
@ REG_VGPR_MIN
Definition: registers.hh:132
Gcn3ISA::REG_RESERVED_5
@ REG_RESERVED_5
Definition: registers.hh:87
Gcn3ISA::REG_INT_CONST_NEG_MIN
@ REG_INT_CONST_NEG_MIN
Definition: registers.hh:82
Gcn3ISA::REG_TTMP_1
@ REG_TTMP_1
Definition: registers.hh:64
Gcn3ISA::REG_RESERVED_23
@ REG_RESERVED_23
Definition: registers.hh:105
Gcn3ISA::REG_RESERVED_28
@ REG_RESERVED_28
Definition: registers.hh:110
Gcn3ISA::REG_SRC_LITERAL
@ REG_SRC_LITERAL
Definition: registers.hh:131
Gcn3ISA::REG_TTMP_8
@ REG_TTMP_8
Definition: registers.hh:71
Gcn3ISA::StatusReg
Definition: registers.hh:201
Gcn3ISA::REG_RESERVED_3
@ REG_RESERVED_3
Definition: registers.hh:85
Gcn3ISA::VecElemF64
double VecElemF64
Definition: registers.hh:171
Gcn3ISA::REG_ZERO
@ REG_ZERO
Definition: registers.hh:79
Gcn3ISA::ScalarRegI32
int32_t ScalarRegI32
Definition: registers.hh:155
Gcn3ISA::REG_TTMP_4
@ REG_TTMP_4
Definition: registers.hh:67
Gcn3ISA
classes that represnt vector/scalar operands in GCN3 ISA.
Definition: decoder.cc:44
Gcn3ISA::REG_RESERVED_21
@ REG_RESERVED_21
Definition: registers.hh:103
Gcn3ISA::REG_RESERVED_8
@ REG_RESERVED_8
Definition: registers.hh:90
Gcn3ISA::MSB_PER_WORD
const int MSB_PER_WORD
Definition: registers.hh:147
Gcn3ISA::REG_SCC
@ REG_SCC
Definition: registers.hh:129
Gcn3ISA::opSelectorToRegIdx
int opSelectorToRegIdx(int idx, int numScalarRegs)
Definition: registers.cc:123
Gcn3ISA::REG_LDS_DIRECT
@ REG_LDS_DIRECT
Definition: registers.hh:130
Gcn3ISA::isPosConstVal
bool isPosConstVal(int opIdx)
Definition: registers.cc:168
Gcn3ISA::VecRegContainerU16
VecRegU16::Container VecRegContainerU16
Definition: registers.hh:197
Gcn3ISA::ScalarRegI8
int8_t ScalarRegI8
Definition: registers.hh:151
Gcn3ISA::isVccReg
bool isVccReg(int opIdx)
Definition: registers.cc:205
Gcn3ISA::REG_TTMP_9
@ REG_TTMP_9
Definition: registers.hh:72
Gcn3ISA::StatusReg::RESERVED_1
uint32_t RESERVED_1
Definition: registers.hh:236
Gcn3ISA::VecRegContainerU64
VecRegU64::Container VecRegContainerU64
Definition: registers.hh:199
Gcn3ISA::VecElemI64
int64_t VecElemI64
Definition: registers.hh:170
Gcn3ISA::REG_M0
@ REG_M0
Definition: registers.hh:75
Gcn3ISA::REG_XNACK_MASK_HI
@ REG_XNACK_MASK_HI
Definition: registers.hh:56
Gcn3ISA::REG_FLAT_SCRATCH_HI
@ REG_FLAT_SCRATCH_HI
Definition: registers.hh:54
Gcn3ISA::REG_XNACK_MASK_LO
@ REG_XNACK_MASK_LO
Definition: registers.hh:55
Gcn3ISA::StatusReg::TTRACE_EN
uint32_t TTRACE_EN
Definition: registers.hh:217
Gcn3ISA::REG_RESERVED_4
@ REG_RESERVED_4
Definition: registers.hh:86
Gcn3ISA::REG_RESERVED_13
@ REG_RESERVED_13
Definition: registers.hh:95
Gcn3ISA::StatusReg::COND_DBG_SYS
uint32_t COND_DBG_SYS
Definition: registers.hh:231
Gcn3ISA::REG_SGPR_MAX
@ REG_SGPR_MAX
Definition: registers.hh:52
Gcn3ISA::StatusReg::INSTRUCTION_ATC
uint32_t INSTRUCTION_ATC
Definition: registers.hh:233
Gcn3ISA::REG_POS_TWO
@ REG_POS_TWO
Definition: registers.hh:119
Gcn3ISA::REG_RESERVED_2
@ REG_RESERVED_2
Definition: registers.hh:84
Gcn3ISA::StatusReg::PERF_EN
uint32_t PERF_EN
Definition: registers.hh:229
Gcn3ISA::StatusReg::IN_BARRIER
uint32_t IN_BARRIER
Definition: registers.hh:222
Gcn3ISA::REG_TTMP_5
@ REG_TTMP_5
Definition: registers.hh:68
Gcn3ISA::REG_RESERVED_9
@ REG_RESERVED_9
Definition: registers.hh:91
Gcn3ISA::REG_RESERVED_18
@ REG_RESERVED_18
Definition: registers.hh:100
Gcn3ISA::ScalarRegU16
uint16_t ScalarRegU16
Definition: registers.hh:152
Gcn3ISA::StatusReg::TRAP
uint32_t TRAP
Definition: registers.hh:224
Gcn3ISA::BITS_PER_WORD
const int BITS_PER_WORD
Definition: registers.hh:145
Gcn3ISA::REG_TTMP_6
@ REG_TTMP_6
Definition: registers.hh:69
Gcn3ISA::REG_INT_CONST_NEG_MAX
@ REG_INT_CONST_NEG_MAX
Definition: registers.hh:83
Gcn3ISA::REG_NEG_ONE
@ REG_NEG_ONE
Definition: registers.hh:118
Gcn3ISA::StatusReg::USER_PRIO
uint32_t USER_PRIO
Definition: registers.hh:214
Gcn3ISA::REG_TTMP_0
@ REG_TTMP_0
Definition: registers.hh:63
vec_reg.hh
Gcn3ISA::REG_TBA_LO
@ REG_TBA_LO
Definition: registers.hh:59
Gcn3ISA::StatusReg::VCCZ
uint32_t VCCZ
Definition: registers.hh:220
Gcn3ISA::isNegConstVal
bool isNegConstVal(int opIdx)
Definition: registers.cc:177
Gcn3ISA::REG_POS_ONE
@ REG_POS_ONE
Definition: registers.hh:117
Gcn3ISA::VecElemI16
int16_t VecElemI16
Definition: registers.hh:165
Gcn3ISA::StatusReg::StatusReg
StatusReg()
Definition: registers.hh:203
Gcn3ISA::REG_RESERVED_7
@ REG_RESERVED_7
Definition: registers.hh:89
Gcn3ISA::REG_RESERVED_6
@ REG_RESERVED_6
Definition: registers.hh:88
Gcn3ISA::REG_INT_CONST_POS_MAX
@ REG_INT_CONST_POS_MAX
Definition: registers.hh:81
Gcn3ISA::StatusReg::IN_TG
uint32_t IN_TG
Definition: registers.hh:221
Gcn3ISA::StatusReg::COND_DBG_USER
uint32_t COND_DBG_USER
Definition: registers.hh:230
Gcn3ISA::opSelectorToRegSym
std::string opSelectorToRegSym(int idx, int numRegs)
Definition: registers.cc:41
Gcn3ISA::isLiteral
bool isLiteral(int opIdx)
Definition: registers.cc:193
Gcn3ISA::REG_TTMP_2
@ REG_TTMP_2
Definition: registers.hh:65
Gcn3ISA::REG_RESERVED_12
@ REG_RESERVED_12
Definition: registers.hh:94
logging.hh
Gcn3ISA::REG_TTMP_3
@ REG_TTMP_3
Definition: registers.hh:66
Gcn3ISA::ScalarRegU32
uint32_t ScalarRegU32
Definition: registers.hh:154
Gcn3ISA::REG_NEG_TWO
@ REG_NEG_TWO
Definition: registers.hh:120
Gcn3ISA::REG_RESERVED_22
@ REG_RESERVED_22
Definition: registers.hh:104
Gcn3ISA::StatusReg::ECC_ERR
uint32_t ECC_ERR
Definition: registers.hh:227
Gcn3ISA::VecElemU8
uint8_t VecElemU8
Definition: registers.hh:162
Gcn3ISA::StatusReg::EXPORT_RDY
uint32_t EXPORT_RDY
Definition: registers.hh:218
Gcn3ISA::VecElemI32
int32_t VecElemI32
Definition: registers.hh:167
Gcn3ISA::REG_SGPR_MIN
@ REG_SGPR_MIN
Definition: registers.hh:51
Gcn3ISA::StatusReg::TRAP_EN
uint32_t TRAP_EN
Definition: registers.hh:216
Gcn3ISA::REG_NEG_HALF
@ REG_NEG_HALF
Definition: registers.hh:116
Gcn3ISA::VecRegContainerU32
VecRegU32::Container VecRegContainerU32
Definition: registers.hh:198
Gcn3ISA::REG_RESERVED_14
@ REG_RESERVED_14
Definition: registers.hh:96
Gcn3ISA::NumPosConstRegs
const int NumPosConstRegs
Definition: registers.hh:139
Gcn3ISA::REG_SRC_SWDA
@ REG_SRC_SWDA
Definition: registers.hh:125
Gcn3ISA::REG_NEG_FOUR
@ REG_NEG_FOUR
Definition: registers.hh:122
Gcn3ISA::REG_RESERVED_19
@ REG_RESERVED_19
Definition: registers.hh:101
Gcn3ISA::VecElemU64
uint64_t VecElemU64
Definition: registers.hh:169
Gcn3ISA::StatusReg::SCC
uint32_t SCC
Definition: registers.hh:212
intmath.hh
Gcn3ISA::MSB_PER_BYTE
const int MSB_PER_BYTE
Definition: registers.hh:146
Gcn3ISA::StatusReg::ALLOW_REPLAY
uint32_t ALLOW_REPLAY
Definition: registers.hh:232
Gcn3ISA::REG_PI
@ REG_PI
Definition: registers.hh:123
Gcn3ISA::VecElemF32
float VecElemF32
Definition: registers.hh:168
Gcn3ISA::REG_RESERVED_15
@ REG_RESERVED_15
Definition: registers.hh:97
Gcn3ISA::REG_EXEC_HI
@ REG_EXEC_HI
Definition: registers.hh:78
Gcn3ISA::MaxOperandDwords
constexpr size_t MaxOperandDwords(16)
Gcn3ISA::REG_RESERVED_17
@ REG_RESERVED_17
Definition: registers.hh:99
Gcn3ISA::VecRegContainerU8
VecRegU8::Container VecRegContainerU8
Definition: registers.hh:196
Gcn3ISA::REG_RESERVED_26
@ REG_RESERVED_26
Definition: registers.hh:108
Gcn3ISA::isConstVal
bool isConstVal(int opIdx)
Definition: registers.cc:186
Gcn3ISA::REG_RESERVED_10
@ REG_RESERVED_10
Definition: registers.hh:92
Gcn3ISA::StatusReg::TTRACE_CU_EN
uint32_t TTRACE_CU_EN
Definition: registers.hh:225
VecRegT
Vector Register Abstraction This generic class is a view in a particularization of MVC,...
Definition: vec_reg.hh:170
Gcn3ISA::REG_RESERVED_31
@ REG_RESERVED_31
Definition: registers.hh:113

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