gem5  v20.1.0.0
gpu_command_processor.hh File Reference
#include "dev/hsa/hsa_device.hh"
#include "gpu-compute/hsa_queue_entry.hh"

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class  GPUCommandProcessor
class  GPUCommandProcessor::ReadDispIdOffsetDmaEvent
 Perform a DMA read of the read_dispatch_id_field_base_byte_offset field, which follows directly after the read_dispatch_id (the read pointer) in the amd_hsa_queue_t struct (aka memory queue descriptor (MQD)), to find the base address of the MQD. More...
class  GPUCommandProcessor::MQDDmaEvent
 Perform a DMA read of the MQD that corresponds to a hardware queue descriptor (HQD). More...

Detailed Description

The GPUCommandProcessor (CP) is responsible for accepting commands, in the form of HSA AQL packets, from the HSA packet processor (HSAPP). The CP works with several components, including the HSAPP and the dispatcher. When the HSAPP sends a ready task to the CP, it will perform the necessary operations to extract relevant data structures from memory, such as the AQL queue descriptor and AQL packet, and initializes register state for the task's wavefronts.

Definition in file gpu_command_processor.hh.

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