gem5  v20.1.0.0
hsa_queue.hh
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35 
36 #ifndef __DEV_HSA_HSA_QUEUE_HH__
37 #define __DEV_HSA_HSA_QUEUE_HH__
38 
39 #include <cstdint>
40 
41 typedef enum
42 {
46 
47 typedef struct _hsa_signal_s
48 {
49  uint64_t handle;
51 
52 typedef struct _hsa_queue_s
53 {
55  uint32_t features;
56  void *base_address;
58  uint32_t size;
59  uint32_t reserved1;
60  uint64_t id;
61 } _hsa_queue_t;
62 
63 typedef uint32_t _amd_queue_properties32_t;
64 
65 typedef struct _amd_queue_s
66 {
68  uint32_t reserved1[4];
69  volatile uint64_t write_dispatch_id;
72  uint32_t max_cu_id;
73  uint32_t max_wave_id;
75  volatile uint32_t legacy_doorbell_lock;
76  uint32_t reserved2[9];
77  volatile uint64_t read_dispatch_id;
87  uint32_t reserved3[2];
89  uint32_t reserved4[14];
90 } _amd_queue_t;
91 
92 #endif // __DEV_HSA_HSA_QUEUE_HH__
_amd_queue_s::scratch_resource_descriptor
uint32_t scratch_resource_descriptor[4]
Definition: hsa_queue.hh:82
_amd_queue_s::private_segment_aperture_base_hi
uint32_t private_segment_aperture_base_hi
Definition: hsa_queue.hh:71
_hsa_queue_s
Definition: hsa_queue.hh:52
_amd_queue_s::scratch_workitem_byte_size
uint32_t scratch_workitem_byte_size
Definition: hsa_queue.hh:85
_amd_queue_s::hsa_queue
_hsa_queue_t hsa_queue
Definition: hsa_queue.hh:67
_amd_queue_s::reserved4
uint32_t reserved4[14]
Definition: hsa_queue.hh:89
_amd_queue_properties32_t
uint32_t _amd_queue_properties32_t
Definition: hsa_queue.hh:63
_amd_queue_s::reserved3
uint32_t reserved3[2]
Definition: hsa_queue.hh:87
_hsa_queue_s::size
uint32_t size
Definition: hsa_queue.hh:58
_amd_queue_s::max_cu_id
uint32_t max_cu_id
Definition: hsa_queue.hh:72
_amd_queue_s::max_legacy_doorbell_dispatch_id_plus_1
volatile uint64_t max_legacy_doorbell_dispatch_id_plus_1
Definition: hsa_queue.hh:74
_hsa_signal_s::handle
uint64_t handle
Definition: hsa_queue.hh:49
_amd_queue_s::queue_inactive_signal
_hsa_signal_t queue_inactive_signal
Definition: hsa_queue.hh:88
_hsa_queue_type_t
_hsa_queue_type_t
Definition: hsa_queue.hh:41
_hsa_queue_s::doorbell_signal
_hsa_signal_t doorbell_signal
Definition: hsa_queue.hh:57
_amd_queue_s::compute_tmpring_size_pad
uint32_t compute_tmpring_size_pad
Definition: hsa_queue.hh:81
_amd_queue_s::queue_properties
_amd_queue_properties32_t queue_properties
Definition: hsa_queue.hh:86
_amd_queue_s::read_dispatch_id
volatile uint64_t read_dispatch_id
Definition: hsa_queue.hh:77
_amd_queue_s::write_dispatch_id
volatile uint64_t write_dispatch_id
Definition: hsa_queue.hh:69
_HSA_QUEUE_TYPE_MULTI
@ _HSA_QUEUE_TYPE_MULTI
Definition: hsa_queue.hh:43
_amd_queue_s::read_dispatch_id_field_base_byte_offset
uint32_t read_dispatch_id_field_base_byte_offset
Definition: hsa_queue.hh:78
_amd_queue_s::max_wave_id
uint32_t max_wave_id
Definition: hsa_queue.hh:73
_amd_queue_s::scratch_backing_memory_byte_size
uint64_t scratch_backing_memory_byte_size
Definition: hsa_queue.hh:84
_amd_queue_s::group_segment_aperture_base_hi
uint32_t group_segment_aperture_base_hi
Definition: hsa_queue.hh:70
_hsa_queue_s::reserved1
uint32_t reserved1
Definition: hsa_queue.hh:59
_amd_queue_s
Definition: hsa_queue.hh:65
_amd_queue_s::scratch_backing_memory_location
uint64_t scratch_backing_memory_location
Definition: hsa_queue.hh:83
_amd_queue_s::compute_tmpring_size_waves
uint32_t compute_tmpring_size_waves
Definition: hsa_queue.hh:79
_amd_queue_s::reserved2
uint32_t reserved2[9]
Definition: hsa_queue.hh:76
_hsa_queue_s::base_address
void * base_address
Definition: hsa_queue.hh:56
_HSA_QUEUE_TYPE_SINGLE
@ _HSA_QUEUE_TYPE_SINGLE
Definition: hsa_queue.hh:44
_amd_queue_s::compute_tmpring_size_wavesize
uint32_t compute_tmpring_size_wavesize
Definition: hsa_queue.hh:80
_amd_queue_t
struct _amd_queue_s _amd_queue_t
_amd_queue_s::legacy_doorbell_lock
volatile uint32_t legacy_doorbell_lock
Definition: hsa_queue.hh:75
_amd_queue_s::reserved1
uint32_t reserved1[4]
Definition: hsa_queue.hh:68
_hsa_queue_s::type
_hsa_queue_type_t type
Definition: hsa_queue.hh:54
_hsa_queue_t
struct _hsa_queue_s _hsa_queue_t
_hsa_signal_t
struct _hsa_signal_s _hsa_signal_t
_hsa_queue_s::features
uint32_t features
Definition: hsa_queue.hh:55
_hsa_signal_s
Definition: hsa_queue.hh:47
_hsa_queue_s::id
uint64_t id
Definition: hsa_queue.hh:60

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