Macros
#define	ALPHA_K0SEG_BASE ULL(0xfffffc0000000000)

#define	TSDEV_CC_CSR 0x00

#define	TSDEV_CC_MTR 0x01

#define	TSDEV_CC_MISC 0x02

#define	TSDEV_CC_AAR0 0x04

#define	TSDEV_CC_AAR1 0x05

#define	TSDEV_CC_AAR2 0x06

#define	TSDEV_CC_AAR3 0x07

#define	TSDEV_CC_DIM0 0x08

#define	TSDEV_CC_DIM1 0x09

#define	TSDEV_CC_DIR0 0x0A

#define	TSDEV_CC_DIR1 0x0B

#define	TSDEV_CC_DRIR 0x0C

#define	TSDEV_CC_PRBEN 0x0D

#define	TSDEV_CC_IIC0 0x0E

#define	TSDEV_CC_IIC1 0x0F

#define	TSDEV_CC_MPR0 0x10

#define	TSDEV_CC_MPR1 0x11

#define	TSDEV_CC_MPR2 0x12

#define	TSDEV_CC_MPR3 0x13

#define	TSDEV_CC_DIM2 0x18

#define	TSDEV_CC_DIM3 0x19

#define	TSDEV_CC_DIR2 0x1A

#define	TSDEV_CC_DIR3 0x1B

#define	TSDEV_CC_IIC2 0x1C

#define	TSDEV_CC_IIC3 0x1D

#define	TSDEV_CC_BDIMS 0x1000000

#define	TSDEV_CC_BDIRS 0x2000000

#define	TSDEV_CC_IPIQ 0x20

#define	TSDEV_CC_IPIR 0x21

#define	TSDEV_CC_ITIR 0x22

#define	TSDEV_PC_WSBA0 0x00

#define	TSDEV_PC_WSBA1 0x01

#define	TSDEV_PC_WSBA2 0x02

#define	TSDEV_PC_WSBA3 0x03

#define	TSDEV_PC_WSM0 0x04

#define	TSDEV_PC_WSM1 0x05

#define	TSDEV_PC_WSM2 0x06

#define	TSDEV_PC_WSM3 0x07

#define	TSDEV_PC_TBA0 0x08

#define	TSDEV_PC_TBA1 0x09

#define	TSDEV_PC_TBA2 0x0A

#define	TSDEV_PC_TBA3 0x0B

#define	TSDEV_PC_PCTL 0x0C

#define	TSDEV_PC_PLAT 0x0D

#define	TSDEV_PC_RES 0x0E

#define	TSDEV_PC_PERROR 0x0F

#define	TSDEV_PC_PERRMASK 0x10

#define	TSDEV_PC_PERRSET 0x11

#define	TSDEV_PC_TLBIV 0x12

#define	TSDEV_PC_TLBIA 0x13

#define	TSDEV_PC_PMONCTL 0x14

#define	TSDEV_PC_PMONCNT 0x15

#define	TSDEV_PC_SPST 0x20

#define	TSDEV_DC_DSC 0x20

#define	TSDEV_DC_STR 0x21

#define	TSDEV_DC_DREV 0x22

#define	TSDEV_DC_DSC2 0x23

#define	TSDEV_PIC1_MASK 0x21

#define	TSDEV_PIC2_MASK 0xA1

#define	TSDEV_PIC1_ISR 0x20

#define	TSDEV_PIC2_ISR 0xA0

#define	TSDEV_PIC1_ACK 0x20

#define	TSDEV_PIC2_ACK 0xA0

#define	TSDEV_DMA1_RESET 0x0D

#define	TSDEV_DMA2_RESET 0xDA

#define	TSDEV_DMA1_MODE 0x0B

#define	TSDEV_DMA2_MODE 0xD6

#define	TSDEV_DMA1_MASK 0x0A

#define	TSDEV_DMA2_MASK 0xD4

#define	TSDEV_CTRL_PORTB 0x61

#define	TSDEV_TMR0_DATA 0x40

#define	TSDEV_TMR1_DATA 0x41

#define	TSDEV_TMR2_DATA 0x42

#define	TSDEV_TMR_CTRL 0x43

#define	TSDEV_KBD 0x64

#define	TSDEV_DMA1_CMND 0x08

#define	TSDEV_DMA1_STAT TSDEV_DMA1_CMND

#define	TSDEV_DMA2_CMND 0xD0

#define	TSDEV_DMA2_STAT TSDEV_DMA2_CMND

#define	TSDEV_DMA1_MMASK 0x0F

#define	TSDEV_DMA2_MMASK 0xDE

#define	TSDEV_KBD 0x64

#define	ATA_PCI_DMA 0x00

#define	ATA_PCI_DMA2 0x02

#define	ATA_PCI_DMA3 0x16

#define	ATA_PCI_DMA4 0x17

#define	ATA_PCI_DMA5 0x1a

#define	ATA_PCI_DMA6 0x11

#define	ATA_PCI_DMA7 0x14

#define	TSDEV_RTC_ADDR 0x70

#define	TSDEV_RTC_DATA 0x71

#define	PCHIP_PCI0_MEMORY ULL(0x00000000000)

#define	PCHIP_PCI0_IO ULL(0x001FC000000)

#define	TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000)

#define	TSUNAMI_PCI0_MEMORY TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY

#define	TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO

#define	UART_IER_RDI 0x01

#define	UART_IER_THRI 0x02

#define	UART_IER_RLSI 0x04

#define	UART_LSR_TEMT 0x40

#define	UART_LSR_THRE 0x20

#define	UART_LSR_DR 0x01

#define	UART_MCR_LOOP 0x10

#define	PORTB_SPKR_HIGH 0x20

Detailed Description

List of Tsunami CSRs

Definition in file maltareg.h.

Macro Definition Documentation

◆ ALPHA_K0SEG_BASE

#define ALPHA_K0SEG_BASE ULL(0xfffffc0000000000)

Definition at line 38 of file maltareg.h.

◆ ATA_PCI_DMA

#define ATA_PCI_DMA 0x00

Definition at line 140 of file maltareg.h.

◆ ATA_PCI_DMA2

#define ATA_PCI_DMA2 0x02

Definition at line 141 of file maltareg.h.

◆ ATA_PCI_DMA3

#define ATA_PCI_DMA3 0x16

Definition at line 142 of file maltareg.h.

◆ ATA_PCI_DMA4

#define ATA_PCI_DMA4 0x17

Definition at line 143 of file maltareg.h.

◆ ATA_PCI_DMA5

#define ATA_PCI_DMA5 0x1a

Definition at line 144 of file maltareg.h.

◆ ATA_PCI_DMA6

#define ATA_PCI_DMA6 0x11

Definition at line 145 of file maltareg.h.

◆ ATA_PCI_DMA7

#define ATA_PCI_DMA7 0x14

Definition at line 146 of file maltareg.h.

◆ PCHIP_PCI0_IO

#define PCHIP_PCI0_IO ULL(0x001FC000000)

Definition at line 152 of file maltareg.h.

◆ PCHIP_PCI0_MEMORY

#define PCHIP_PCI0_MEMORY ULL(0x00000000000)

Definition at line 151 of file maltareg.h.

◆ PORTB_SPKR_HIGH

#define PORTB_SPKR_HIGH 0x20

Definition at line 172 of file maltareg.h.

◆ TSDEV_CC_AAR0

#define TSDEV_CC_AAR0 0x04

Definition at line 45 of file maltareg.h.

◆ TSDEV_CC_AAR1

#define TSDEV_CC_AAR1 0x05

Definition at line 46 of file maltareg.h.

◆ TSDEV_CC_AAR2

#define TSDEV_CC_AAR2 0x06

Definition at line 47 of file maltareg.h.

◆ TSDEV_CC_AAR3

#define TSDEV_CC_AAR3 0x07

Definition at line 48 of file maltareg.h.

◆ TSDEV_CC_BDIMS

#define TSDEV_CC_BDIMS 0x1000000

Definition at line 70 of file maltareg.h.

◆ TSDEV_CC_BDIRS

#define TSDEV_CC_BDIRS 0x2000000

Definition at line 71 of file maltareg.h.

◆ TSDEV_CC_CSR

#define TSDEV_CC_CSR 0x00

Definition at line 41 of file maltareg.h.

◆ TSDEV_CC_DIM0

#define TSDEV_CC_DIM0 0x08

Definition at line 49 of file maltareg.h.

◆ TSDEV_CC_DIM1

#define TSDEV_CC_DIM1 0x09

Definition at line 50 of file maltareg.h.

◆ TSDEV_CC_DIM2

#define TSDEV_CC_DIM2 0x18

Definition at line 62 of file maltareg.h.

◆ TSDEV_CC_DIM3

#define TSDEV_CC_DIM3 0x19

Definition at line 63 of file maltareg.h.

◆ TSDEV_CC_DIR0

#define TSDEV_CC_DIR0 0x0A

Definition at line 51 of file maltareg.h.

◆ TSDEV_CC_DIR1

#define TSDEV_CC_DIR1 0x0B

Definition at line 52 of file maltareg.h.

◆ TSDEV_CC_DIR2

#define TSDEV_CC_DIR2 0x1A

Definition at line 64 of file maltareg.h.

◆ TSDEV_CC_DIR3

#define TSDEV_CC_DIR3 0x1B

Definition at line 65 of file maltareg.h.

◆ TSDEV_CC_DRIR

#define TSDEV_CC_DRIR 0x0C

Definition at line 53 of file maltareg.h.

◆ TSDEV_CC_IIC0

#define TSDEV_CC_IIC0 0x0E

Definition at line 55 of file maltareg.h.

◆ TSDEV_CC_IIC1

#define TSDEV_CC_IIC1 0x0F

Definition at line 56 of file maltareg.h.

◆ TSDEV_CC_IIC2

#define TSDEV_CC_IIC2 0x1C

Definition at line 66 of file maltareg.h.

◆ TSDEV_CC_IIC3

#define TSDEV_CC_IIC3 0x1D

Definition at line 67 of file maltareg.h.

◆ TSDEV_CC_IPIQ

#define TSDEV_CC_IPIQ 0x20

Definition at line 72 of file maltareg.h.

◆ TSDEV_CC_IPIR

#define TSDEV_CC_IPIR 0x21

Definition at line 73 of file maltareg.h.

◆ TSDEV_CC_ITIR

#define TSDEV_CC_ITIR 0x22

Definition at line 74 of file maltareg.h.

◆ TSDEV_CC_MISC

#define TSDEV_CC_MISC 0x02

Definition at line 43 of file maltareg.h.

◆ TSDEV_CC_MPR0

#define TSDEV_CC_MPR0 0x10

Definition at line 57 of file maltareg.h.

◆ TSDEV_CC_MPR1

#define TSDEV_CC_MPR1 0x11

Definition at line 58 of file maltareg.h.

◆ TSDEV_CC_MPR2

#define TSDEV_CC_MPR2 0x12

Definition at line 59 of file maltareg.h.

◆ TSDEV_CC_MPR3

#define TSDEV_CC_MPR3 0x13

Definition at line 60 of file maltareg.h.

◆ TSDEV_CC_MTR

#define TSDEV_CC_MTR 0x01

Definition at line 42 of file maltareg.h.

◆ TSDEV_CC_PRBEN

#define TSDEV_CC_PRBEN 0x0D

Definition at line 54 of file maltareg.h.

◆ TSDEV_CTRL_PORTB

#define TSDEV_CTRL_PORTB 0x61

Definition at line 123 of file maltareg.h.

◆ TSDEV_DC_DREV

#define TSDEV_DC_DREV 0x22

Definition at line 107 of file maltareg.h.

◆ TSDEV_DC_DSC

#define TSDEV_DC_DSC 0x20

Definition at line 105 of file maltareg.h.

◆ TSDEV_DC_DSC2

#define TSDEV_DC_DSC2 0x23

Definition at line 108 of file maltareg.h.

◆ TSDEV_DC_STR

#define TSDEV_DC_STR 0x21

Definition at line 106 of file maltareg.h.

◆ TSDEV_DMA1_CMND

#define TSDEV_DMA1_CMND 0x08

Definition at line 129 of file maltareg.h.

◆ TSDEV_DMA1_MASK

#define TSDEV_DMA1_MASK 0x0A

Definition at line 121 of file maltareg.h.

◆ TSDEV_DMA1_MMASK

#define TSDEV_DMA1_MMASK 0x0F

Definition at line 133 of file maltareg.h.

◆ TSDEV_DMA1_MODE

#define TSDEV_DMA1_MODE 0x0B

Definition at line 119 of file maltareg.h.

◆ TSDEV_DMA1_RESET

#define TSDEV_DMA1_RESET 0x0D

Definition at line 117 of file maltareg.h.

◆ TSDEV_DMA1_STAT

#define TSDEV_DMA1_STAT TSDEV_DMA1_CMND

Definition at line 130 of file maltareg.h.

◆ TSDEV_DMA2_CMND

#define TSDEV_DMA2_CMND 0xD0

Definition at line 131 of file maltareg.h.

◆ TSDEV_DMA2_MASK

#define TSDEV_DMA2_MASK 0xD4

Definition at line 122 of file maltareg.h.

◆ TSDEV_DMA2_MMASK

#define TSDEV_DMA2_MMASK 0xDE

Definition at line 134 of file maltareg.h.

◆ TSDEV_DMA2_MODE

#define TSDEV_DMA2_MODE 0xD6

Definition at line 120 of file maltareg.h.

◆ TSDEV_DMA2_RESET

#define TSDEV_DMA2_RESET 0xDA

Definition at line 118 of file maltareg.h.

◆ TSDEV_DMA2_STAT

#define TSDEV_DMA2_STAT TSDEV_DMA2_CMND

Definition at line 132 of file maltareg.h.

◆ TSDEV_KBD [1/2]

#define TSDEV_KBD 0x64

Definition at line 137 of file maltareg.h.

◆ TSDEV_KBD [2/2]

#define TSDEV_KBD 0x64

Definition at line 137 of file maltareg.h.

◆ TSDEV_PC_PCTL

#define TSDEV_PC_PCTL 0x0C

Definition at line 90 of file maltareg.h.

◆ TSDEV_PC_PERRMASK

#define TSDEV_PC_PERRMASK 0x10

Definition at line 94 of file maltareg.h.

◆ TSDEV_PC_PERROR

#define TSDEV_PC_PERROR 0x0F

Definition at line 93 of file maltareg.h.

◆ TSDEV_PC_PERRSET

#define TSDEV_PC_PERRSET 0x11

Definition at line 95 of file maltareg.h.

◆ TSDEV_PC_PLAT

#define TSDEV_PC_PLAT 0x0D

Definition at line 91 of file maltareg.h.

◆ TSDEV_PC_PMONCNT

#define TSDEV_PC_PMONCNT 0x15

Definition at line 99 of file maltareg.h.

◆ TSDEV_PC_PMONCTL

#define TSDEV_PC_PMONCTL 0x14

Definition at line 98 of file maltareg.h.

◆ TSDEV_PC_RES

#define TSDEV_PC_RES 0x0E

Definition at line 92 of file maltareg.h.

◆ TSDEV_PC_SPST

#define TSDEV_PC_SPST 0x20

Definition at line 101 of file maltareg.h.

◆ TSDEV_PC_TBA0

#define TSDEV_PC_TBA0 0x08

Definition at line 86 of file maltareg.h.

◆ TSDEV_PC_TBA1

#define TSDEV_PC_TBA1 0x09

Definition at line 87 of file maltareg.h.

◆ TSDEV_PC_TBA2

#define TSDEV_PC_TBA2 0x0A

Definition at line 88 of file maltareg.h.

◆ TSDEV_PC_TBA3

#define TSDEV_PC_TBA3 0x0B

Definition at line 89 of file maltareg.h.

◆ TSDEV_PC_TLBIA

#define TSDEV_PC_TLBIA 0x13

Definition at line 97 of file maltareg.h.

◆ TSDEV_PC_TLBIV

#define TSDEV_PC_TLBIV 0x12

Definition at line 96 of file maltareg.h.

◆ TSDEV_PC_WSBA0

#define TSDEV_PC_WSBA0 0x00

Definition at line 78 of file maltareg.h.

◆ TSDEV_PC_WSBA1

#define TSDEV_PC_WSBA1 0x01

Definition at line 79 of file maltareg.h.

◆ TSDEV_PC_WSBA2

#define TSDEV_PC_WSBA2 0x02

Definition at line 80 of file maltareg.h.

◆ TSDEV_PC_WSBA3

#define TSDEV_PC_WSBA3 0x03

Definition at line 81 of file maltareg.h.

◆ TSDEV_PC_WSM0

#define TSDEV_PC_WSM0 0x04

Definition at line 82 of file maltareg.h.

◆ TSDEV_PC_WSM1

#define TSDEV_PC_WSM1 0x05

Definition at line 83 of file maltareg.h.

◆ TSDEV_PC_WSM2

#define TSDEV_PC_WSM2 0x06

Definition at line 84 of file maltareg.h.

◆ TSDEV_PC_WSM3

#define TSDEV_PC_WSM3 0x07

Definition at line 85 of file maltareg.h.

◆ TSDEV_PIC1_ACK

#define TSDEV_PIC1_ACK 0x20

Definition at line 115 of file maltareg.h.

◆ TSDEV_PIC1_ISR

#define TSDEV_PIC1_ISR 0x20

Definition at line 113 of file maltareg.h.

◆ TSDEV_PIC1_MASK

#define TSDEV_PIC1_MASK 0x21

Definition at line 111 of file maltareg.h.

◆ TSDEV_PIC2_ACK

#define TSDEV_PIC2_ACK 0xA0

Definition at line 116 of file maltareg.h.

◆ TSDEV_PIC2_ISR

#define TSDEV_PIC2_ISR 0xA0

Definition at line 114 of file maltareg.h.

◆ TSDEV_PIC2_MASK

#define TSDEV_PIC2_MASK 0xA1

Definition at line 112 of file maltareg.h.

◆ TSDEV_RTC_ADDR

#define TSDEV_RTC_ADDR 0x70

Definition at line 148 of file maltareg.h.

◆ TSDEV_RTC_DATA

#define TSDEV_RTC_DATA 0x71

Definition at line 149 of file maltareg.h.

◆ TSDEV_TMR0_DATA

#define TSDEV_TMR0_DATA 0x40

Definition at line 124 of file maltareg.h.

◆ TSDEV_TMR1_DATA

#define TSDEV_TMR1_DATA 0x41

Definition at line 125 of file maltareg.h.

◆ TSDEV_TMR2_DATA

#define TSDEV_TMR2_DATA 0x42

Definition at line 126 of file maltareg.h.

◆ TSDEV_TMR_CTRL

#define TSDEV_TMR_CTRL 0x43

Definition at line 127 of file maltareg.h.

◆ TSUNAMI_PCI0_IO

#define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO

Definition at line 155 of file maltareg.h.

◆ TSUNAMI_PCI0_MEMORY

#define TSUNAMI_PCI0_MEMORY TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY

Definition at line 154 of file maltareg.h.

◆ TSUNAMI_UNCACHABLE_BIT

#define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000)

Definition at line 153 of file maltareg.h.

◆ UART_IER_RDI

#define UART_IER_RDI 0x01

Definition at line 160 of file maltareg.h.

◆ UART_IER_RLSI

#define UART_IER_RLSI 0x04

Definition at line 162 of file maltareg.h.

◆ UART_IER_THRI

#define UART_IER_THRI 0x02

Definition at line 161 of file maltareg.h.

◆ UART_LSR_DR

#define UART_LSR_DR 0x01

Definition at line 167 of file maltareg.h.

◆ UART_LSR_TEMT

#define UART_LSR_TEMT 0x40

Definition at line 165 of file maltareg.h.

◆ UART_LSR_THRE

#define UART_LSR_THRE 0x20

Definition at line 166 of file maltareg.h.

◆ UART_MCR_LOOP

#define UART_MCR_LOOP 0x10

Definition at line 169 of file maltareg.h.

Macros