gem5  v20.1.0.0
test.h
Go to the documentation of this file.
1 /*****************************************************************************
2 
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements. See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License. You may obtain a copy of the License at
9 
10  http://www.apache.org/licenses/LICENSE-2.0
11 
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied. See the License for the specific language governing
16  permissions and limitations under the License.
17 
18  *****************************************************************************/
19 
20 /*****************************************************************************
21 
22  test.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 /* Common interface file for test cases
39  Author: PRP
40  */
41 
43 {
44  SC_HAS_PROCESS( t );
45 
46  sc_in_clk clk;
47 
48  // Input Reset Port
49  const sc_signal<bool>& reset_sig;
50 
51  // Input Data Ports
52  const sc_signal<int>& i1;
53  const sc_signal<int>& i2;
54  const sc_signal<int>& i3;
55  const sc_signal<int>& i4;
56  const sc_signal<int>& i5;
57 
58  // Input Control Ports
59  const sc_signal<bool>& cont1;
60  const sc_signal<bool>& cont2;
61  const sc_signal<bool>& cont3;
62 
63  // Output Data Ports
64  sc_signal<int>& o1;
65  sc_signal<int>& o2;
66  sc_signal<int>& o3;
67  sc_signal<int>& o4;
68  sc_signal<int>& o5;
69 
70  // Constructor
71  t (
72  sc_module_name NAME,
73  sc_clock& CLK,
74 
75  const sc_signal<bool>& RESET_SIG,
76 
77  const sc_signal<int>& I1,
78  const sc_signal<int>& I2,
79  const sc_signal<int>& I3,
80  const sc_signal<int>& I4,
81  const sc_signal<int>& I5,
82 
83  const sc_signal<bool>& CONT1,
84  const sc_signal<bool>& CONT2,
85  const sc_signal<bool>& CONT3,
86 
87  sc_signal<int>& O1,
88  sc_signal<int>& O2,
89  sc_signal<int>& O3,
90  sc_signal<int>& O4,
91  sc_signal<int>& O5)
92  : reset_sig(RESET_SIG), i1(I1), i2(I2),
93  i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
94  cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
95  {
96  clk(CLK);
97  SC_CTHREAD( entry, clk );
98  reset_signal_is(reset_sig,true);
99  }
100 
101  void entry();
102 };
SC_MODULE
SC_MODULE(test)
Definition: test.h:44
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
ArmISA::t
Bitfield< 5 > t
Definition: miscregs_types.hh:67
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:319

Generated on Wed Sep 30 2020 14:02:17 for gem5 by doxygen 1.8.17