gem5  v20.1.0.0
Classes | Typedefs | Enumerations | Functions | Variables
ArmISA Namespace Reference

Classes

class  AbortFault
 
class  ArmFault
 
class  ArmFaultVals
 
class  ArmSev
 
class  ArmStaticInst
 
class  BaseISADevice
 Base class for devices that use the MiscReg interfaces. More...
 
class  BigFpMemImmOp
 
class  BigFpMemLitOp
 
class  BigFpMemPostOp
 
class  BigFpMemPreOp
 
class  BigFpMemRegOp
 
class  BranchEret64
 
class  BranchEretA64
 
class  BranchImm
 
class  BranchImm64
 
class  BranchImmCond
 
class  BranchImmCond64
 
class  BranchImmImmReg64
 
class  BranchImmReg
 
class  BranchImmReg64
 
class  BranchReg
 
class  BranchReg64
 
class  BranchRegCond
 
class  BranchRegReg
 
class  BranchRegReg64
 
class  BranchRet64
 
class  BranchRetA64
 
class  BrkPoint
 
class  Crypto
 
class  DataAbort
 
class  DataImmOp
 
class  DataRegOp
 
class  DataRegRegOp
 
class  DataX1Reg2ImmOp
 
class  DataX1RegImmOp
 
class  DataX1RegOp
 
class  DataX2RegImmOp
 
class  DataX2RegOp
 
class  DataX3RegOp
 
class  DataXCondCompImmOp
 
class  DataXCondCompRegOp
 
class  DataXCondSelOp
 
class  DataXERegOp
 
class  DataXImmOnlyOp
 
class  DataXImmOp
 
class  DataXSRegOp
 
class  Decoder
 
class  DTLBIALL
 Data TLB Invalidate All. More...
 
class  DTLBIASID
 Data TLB Invalidate by ASID match. More...
 
class  DTLBIMVA
 Data TLB Invalidate by VA. More...
 
class  DummyISADevice
 Dummy device that prints a warning when it is accessed. More...
 
class  DumpStats
 
class  DumpStats64
 
class  FastInterrupt
 
class  FpCondCompRegOp
 
class  FpCondSelOp
 
class  FpOp
 
class  FpRegImmOp
 
class  FpRegRegImmOp
 
class  FpRegRegOp
 
class  FpRegRegRegCondOp
 
class  FpRegRegRegImmOp
 
class  FpRegRegRegOp
 
class  FpRegRegRegRegOp
 
class  FsFreebsd
 
class  FsLinux
 
class  FsWorkload
 
class  HardwareBreakpoint
 
class  HTMCheckpoint
 
class  HypervisorCall
 
class  HypervisorTrap
 
class  IllegalInstSetStateFault
 Illegal Instruction Set State fault (AArch64 only) More...
 
class  Interrupt
 
class  Interrupts
 
class  ISA
 
class  ITLBIALL
 Instruction TLB Invalidate All. More...
 
class  ITLBIASID
 Instruction TLB Invalidate by ASID match. More...
 
class  ITLBIMVA
 Instruction TLB Invalidate by VA. More...
 
class  MacroMemOp
 Base class for microcoded integer memory instructions. More...
 
class  MacroVFPMemOp
 Base class for microcoded floating point memory instructions. More...
 
class  Memory
 
class  Memory64
 
class  MemoryDImm
 
class  MemoryDImm64
 
class  MemoryDImmEx64
 
class  MemoryDReg
 
class  MemoryEx64
 
class  MemoryExDImm
 
class  MemoryExImm
 
class  MemoryImm
 
class  MemoryImm64
 
class  MemoryLiteral64
 
class  MemoryOffset
 
class  MemoryPostIndex
 
class  MemoryPostIndex64
 
class  MemoryPreIndex
 
class  MemoryPreIndex64
 
class  MemoryRaw64
 
class  MemoryReg
 
class  MemoryReg64
 
class  MicroIntImmOp
 Microops of the form IntRegA = IntRegB op Imm. More...
 
class  MicroIntImmXOp
 
class  MicroIntMov
 Microops of the form IntRegA = IntRegB. More...
 
class  MicroIntOp
 Microops of the form IntRegA = IntRegB op IntRegC. More...
 
class  MicroIntRegOp
 Microops of the form IntRegA = IntRegB op shifted IntRegC. More...
 
class  MicroIntRegXOp
 
class  MicroMemOp
 Memory microops which use IntReg + Imm addressing. More...
 
class  MicroMemPairOp
 
class  MicroNeonMemOp
 Microops for Neon loads/stores. More...
 
class  MicroNeonMixLaneOp
 
class  MicroNeonMixLaneOp64
 
class  MicroNeonMixOp
 Microops for Neon load/store (de)interleaving. More...
 
class  MicroNeonMixOp64
 Microops for AArch64 NEON load/store (de)interleaving. More...
 
class  MicroOp
 Base class for Memory microops. More...
 
class  MicroOpX
 
class  MicroSetPCCPSR
 Microops of the form PC = IntRegA CPSR = IntRegB. More...
 
class  MightBeMicro
 
class  MightBeMicro64
 
class  Mult3
 Base class for multipy instructions using three registers. More...
 
class  Mult4
 Base class for multipy instructions using four registers. More...
 
class  PairMemOp
 Base class for pair load/store instructions. More...
 
class  PCAlignmentFault
 PC alignment fault (AArch64 only) More...
 
class  PMU
 Model of an ARM PMU version 3. More...
 
class  PredImmOp
 Base class for predicated immediate operations. More...
 
class  PredIntOp
 Base class for predicated integer operations. More...
 
class  PredMacroOp
 Base class for predicated macro-operations. More...
 
class  PredMicroop
 Base class for predicated micro-operations. More...
 
class  PredOp
 Base class for predicated integer operations. More...
 
class  PrefetchAbort
 
struct  PTE
 
class  RemoteGDB
 
class  Reset
 
class  RfeOp
 
class  SecureMonitorCall
 
class  SecureMonitorTrap
 
class  SelfDebug
 
class  SkipFunc
 
class  SkipFuncLinux32
 
class  SkipFuncLinux64
 
class  SoftwareBreakpoint
 System error (AArch64 only) More...
 
class  SoftwareStep
 
class  SoftwareStepFault
 
class  SPAlignmentFault
 Stack pointer alignment fault (AArch64 only) More...
 
class  SrsOp
 
class  StackTrace
 
class  Stage2LookUp
 
class  Stage2MMU
 
class  SupervisorCall
 
class  SupervisorTrap
 
class  SveAdrOp
 ADR. More...
 
class  SveBinConstrPredOp
 Binary, constructive, predicated SVE instruction. More...
 
class  SveBinDestrPredOp
 Binary, destructive, predicated (merging) SVE instruction. More...
 
class  SveBinIdxUnpredOp
 Binary, unpredicated SVE instruction. More...
 
class  SveBinImmIdxUnpredOp
 Binary with immediate index, destructive, unpredicated SVE instruction. More...
 
class  SveBinImmPredOp
 Binary with immediate, destructive, predicated (merging) SVE instruction. More...
 
class  SveBinImmUnpredConstrOp
 Binary with immediate, destructive, unpredicated SVE instruction. More...
 
class  SveBinImmUnpredDestrOp
 SVE vector - immediate binary operation. More...
 
class  SveBinUnpredOp
 Binary, unpredicated SVE instruction with indexed operand. More...
 
class  SveBinWideImmUnpredOp
 Binary with wide immediate, destructive, unpredicated SVE instruction. More...
 
class  SveCmpImmOp
 SVE compare-with-immediate instructions, predicated (zeroing). More...
 
class  SveCmpOp
 SVE compare instructions, predicated (zeroing). More...
 
class  SveComplexIdxOp
 SVE Complex Instructions (indexed) More...
 
class  SveComplexOp
 SVE Complex Instructions (vectors) More...
 
class  SveCompTermOp
 Compare and terminate loop SVE instruction. More...
 
class  SveContigMemSI
 
class  SveContigMemSS
 
class  SveDotProdIdxOp
 SVE dot product instruction (indexed) More...
 
class  SveDotProdOp
 SVE dot product instruction (vectors) More...
 
class  SveElemCountOp
 Element count SVE instruction. More...
 
class  SveIndexedMemSV
 
class  SveIndexedMemVI
 
class  SveIndexIIOp
 Index generation instruction, immediate operands. More...
 
class  SveIndexIROp
 
class  SveIndexRIOp
 
class  SveIndexRROp
 
class  SveIntCmpImmOp
 Integer compare with immediate SVE instruction. More...
 
class  SveIntCmpOp
 Integer compare SVE instruction. More...
 
class  SveLdStructSI
 
class  SveLdStructSS
 
class  SveMemPredFillSpill
 
class  SveMemVecFillSpill
 
class  SveOrdReducOp
 SVE ordered reductions. More...
 
class  SvePartBrkOp
 Partition break SVE instruction. More...
 
class  SvePartBrkPropOp
 Partition break with propagation SVE instruction. More...
 
class  SvePredBinPermOp
 Predicate binary permute instruction. More...
 
class  SvePredCountOp
 
class  SvePredCountPredOp
 
class  SvePredLogicalOp
 Predicate logical instruction. More...
 
class  SvePredTestOp
 SVE predicate test. More...
 
class  SvePredUnaryWImplicitDstOp
 SVE unary predicate instructions with implicit destination operand. More...
 
class  SvePredUnaryWImplicitSrcOp
 SVE unary predicate instructions with implicit source operand. More...
 
class  SvePredUnaryWImplicitSrcPredOp
 SVE unary predicate instructions, predicated, with implicit source operand. More...
 
class  SvePtrueOp
 PTRUE, PTRUES. More...
 
class  SveReducOp
 SVE reductions. More...
 
class  SveSelectOp
 Scalar element select SVE instruction. More...
 
class  SveStStructSI
 
class  SveStStructSS
 
class  SveTblOp
 SVE table lookup/permute using vector of element indices (TBL) More...
 
class  SveTerImmUnpredOp
 Ternary with immediate, destructive, unpredicated SVE instruction. More...
 
class  SveTerPredOp
 Ternary, destructive, predicated (merging) SVE instruction. More...
 
class  SveUnaryPredOp
 Unary, constructive, predicated (merging) SVE instruction. More...
 
class  SveUnaryPredPredOp
 SVE unary operation on predicate (predicated) More...
 
class  SveUnarySca2VecUnpredOp
 Unary unpredicated scalar to vector instruction. More...
 
class  SveUnaryUnpredOp
 Unary, constructive, unpredicated SVE instruction. More...
 
class  SveUnaryWideImmPredOp
 Unary with wide immediate, constructive, predicated SVE instruction. More...
 
class  SveUnaryWideImmUnpredOp
 Unary with wide immediate, constructive, unpredicated SVE instruction. More...
 
class  SveUnpackOp
 SVE unpack and widen predicate. More...
 
class  SveWhileOp
 While predicate generation SVE instruction. More...
 
class  SveWImplicitSrcDstOp
 SVE unary predicate instructions with implicit destination operand. More...
 
class  SysDC64
 
class  SystemError
 System error (AArch64 only) More...
 
class  TableWalker
 
class  TLB
 
struct  TlbEntry
 
class  TLBIALL
 TLB Invalidate All. More...
 
class  TLBIALLN
 TLB Invalidate All, Non-Secure. More...
 
class  TLBIASID
 TLB Invalidate by ASID match. More...
 
class  TLBIIPA
 TLB Invalidate by Intermediate Physical Address. More...
 
class  TLBIMVA
 TLB Invalidate by VA. More...
 
class  TLBIMVAA
 TLB Invalidate by VA, All ASID. More...
 
class  TLBIOp
 
class  TlbTestInterface
 
class  UndefinedInstruction
 
class  VectorCatch
 
class  VfpMacroOp
 
class  VirtualDataAbort
 
class  VirtualFastInterrupt
 
class  VirtualInterrupt
 
class  VldMultOp
 Base classes for microcoded integer memory instructions. More...
 
class  VldMultOp64
 Base classes for microcoded AArch64 NEON memory instructions. More...
 
class  VldSingleOp
 
class  VldSingleOp64
 
struct  VReg
 128-bit NEON vector register. More...
 
class  VstMultOp
 Base class for microcoded integer memory instructions. More...
 
class  VstMultOp64
 
class  VstSingleOp
 
class  VstSingleOp64
 
class  WatchPoint
 
class  Watchpoint
 

Typedefs

typedef Addr FaultOffset
 
typedef uint64_t XReg
 
typedef int VfpSavedState
 
typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS]
 
using VecElem = uint32_t
 
using VecReg = ::VecRegT< VecElem, NumVecElemPerVecReg, false >
 
using ConstVecReg = ::VecRegT< VecElem, NumVecElemPerVecReg, true >
 
using VecRegContainer = VecReg::Container
 
using VecPredReg = ::VecPredRegT< VecElem, NumVecElemPerVecReg, VecPredRegHasPackedRepr, false >
 
using ConstVecPredReg = ::VecPredRegT< VecElem, NumVecElemPerVecReg, VecPredRegHasPackedRepr, true >
 
using VecPredRegContainer = VecPredReg::Container
 
typedef uint32_t MachInst
 
typedef int RegContextParam
 
typedef int RegContextVal
 

Enumerations

enum  ccRegIndex {
  CCREG_NZ, CCREG_C, CCREG_V, CCREG_GE,
  CCREG_FP, CCREG_ZERO, NUM_CCREGS
}
 
enum  ConditionCode {
  COND_EQ = 0, COND_NE, COND_CS, COND_CC,
  COND_MI, COND_PL, COND_VS, COND_VC,
  COND_HI, COND_LS, COND_GE, COND_LT,
  COND_GT, COND_LE, COND_AL, COND_UC
}
 
enum  FPRounding {
  FPRounding_TIEEVEN = 0, FPRounding_POSINF = 1, FPRounding_NEGINF = 2, FPRounding_ZERO = 3,
  FPRounding_TIEAWAY = 4, FPRounding_ODD = 5
}
 
enum  FpDataType { FpDataType::Fp16, FpDataType::Fp32, FpDataType::Fp64 }
 Floating point data types. More...
 
enum  SvePredType { SvePredType::NONE, SvePredType::MERGE, SvePredType::ZERO, SvePredType::SELECT }
 
enum  VfpMicroMode { VfpNotAMicroop, VfpMicroop, VfpFirstMicroop, VfpLastMicroop }
 
enum  FeExceptionBit {
  FeDivByZero = FE_DIVBYZERO, FeInexact = FE_INEXACT, FeInvalid = FE_INVALID, FeOverflow = FE_OVERFLOW,
  FeUnderflow = FE_UNDERFLOW, FeAllExceptions = FE_ALL_EXCEPT
}
 
enum  FeRoundingMode { FeRoundDown = FE_DOWNWARD, FeRoundNearest = FE_TONEAREST, FeRoundZero = FE_TOWARDZERO, FeRoundUpward = FE_UPWARD }
 
enum  VfpRoundingMode {
  VfpRoundNearest = 0, VfpRoundUpward = 1, VfpRoundDown = 2, VfpRoundZero = 3,
  VfpRoundAway = 4
}
 
enum  InterruptTypes {
  INT_RST, INT_ABT, INT_IRQ, INT_FIQ,
  INT_SEV, INT_VIRT_IRQ, INT_VIRT_FIQ, NumInterruptTypes
}
 
enum  IntRegIndex {
  INTREG_R0, INTREG_R1, INTREG_R2, INTREG_R3,
  INTREG_R4, INTREG_R5, INTREG_R6, INTREG_R7,
  INTREG_R8, INTREG_R9, INTREG_R10, INTREG_R11,
  INTREG_R12, INTREG_R13, INTREG_SP = INTREG_R13, INTREG_R14,
  INTREG_LR = INTREG_R14, INTREG_R15, INTREG_PC = INTREG_R15, INTREG_R13_SVC,
  INTREG_SP_SVC = INTREG_R13_SVC, INTREG_R14_SVC, INTREG_LR_SVC = INTREG_R14_SVC, INTREG_R13_MON,
  INTREG_SP_MON = INTREG_R13_MON, INTREG_R14_MON, INTREG_LR_MON = INTREG_R14_MON, INTREG_R13_HYP,
  INTREG_SP_HYP = INTREG_R13_HYP, INTREG_R13_ABT, INTREG_SP_ABT = INTREG_R13_ABT, INTREG_R14_ABT,
  INTREG_LR_ABT = INTREG_R14_ABT, INTREG_R13_UND, INTREG_SP_UND = INTREG_R13_UND, INTREG_R14_UND,
  INTREG_LR_UND = INTREG_R14_UND, INTREG_R13_IRQ, INTREG_SP_IRQ = INTREG_R13_IRQ, INTREG_R14_IRQ,
  INTREG_LR_IRQ = INTREG_R14_IRQ, INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ,
  INTREG_R11_FIQ, INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_SP_FIQ = INTREG_R13_FIQ,
  INTREG_R14_FIQ, INTREG_LR_FIQ = INTREG_R14_FIQ, INTREG_ZERO, INTREG_UREG0,
  INTREG_UREG1, INTREG_UREG2, INTREG_DUMMY, INTREG_SP0,
  INTREG_SP1, INTREG_SP2, INTREG_SP3, NUM_INTREGS,
  NUM_ARCH_INTREGS = 32, INTREG_X0 = 0, INTREG_X1, INTREG_X2,
  INTREG_X3, INTREG_X4, INTREG_X5, INTREG_X6,
  INTREG_X7, INTREG_X8, INTREG_X9, INTREG_X10,
  INTREG_X11, INTREG_X12, INTREG_X13, INTREG_X14,
  INTREG_X15, INTREG_X16, INTREG_X17, INTREG_X18,
  INTREG_X19, INTREG_X20, INTREG_X21, INTREG_X22,
  INTREG_X23, INTREG_X24, INTREG_X25, INTREG_X26,
  INTREG_X27, INTREG_X28, INTREG_X29, INTREG_X30,
  INTREG_X31, INTREG_SPX = NUM_INTREGS, INTREG_R0_USR = INTREG_R0, INTREG_R1_USR = INTREG_R1,
  INTREG_R2_USR = INTREG_R2, INTREG_R3_USR = INTREG_R3, INTREG_R4_USR = INTREG_R4, INTREG_R5_USR = INTREG_R5,
  INTREG_R6_USR = INTREG_R6, INTREG_R7_USR = INTREG_R7, INTREG_R8_USR = INTREG_R8, INTREG_R9_USR = INTREG_R9,
  INTREG_R10_USR = INTREG_R10, INTREG_R11_USR = INTREG_R11, INTREG_R12_USR = INTREG_R12, INTREG_R13_USR = INTREG_R13,
  INTREG_SP_USR = INTREG_SP, INTREG_R14_USR = INTREG_R14, INTREG_LR_USR = INTREG_LR, INTREG_R15_USR = INTREG_R15,
  INTREG_PC_USR = INTREG_PC, INTREG_R0_SVC = INTREG_R0, INTREG_R1_SVC = INTREG_R1, INTREG_R2_SVC = INTREG_R2,
  INTREG_R3_SVC = INTREG_R3, INTREG_R4_SVC = INTREG_R4, INTREG_R5_SVC = INTREG_R5, INTREG_R6_SVC = INTREG_R6,
  INTREG_R7_SVC = INTREG_R7, INTREG_R8_SVC = INTREG_R8, INTREG_R9_SVC = INTREG_R9, INTREG_R10_SVC = INTREG_R10,
  INTREG_R11_SVC = INTREG_R11, INTREG_R12_SVC = INTREG_R12, INTREG_PC_SVC = INTREG_PC, INTREG_R15_SVC = INTREG_R15,
  INTREG_R0_MON = INTREG_R0, INTREG_R1_MON = INTREG_R1, INTREG_R2_MON = INTREG_R2, INTREG_R3_MON = INTREG_R3,
  INTREG_R4_MON = INTREG_R4, INTREG_R5_MON = INTREG_R5, INTREG_R6_MON = INTREG_R6, INTREG_R7_MON = INTREG_R7,
  INTREG_R8_MON = INTREG_R8, INTREG_R9_MON = INTREG_R9, INTREG_R10_MON = INTREG_R10, INTREG_R11_MON = INTREG_R11,
  INTREG_R12_MON = INTREG_R12, INTREG_PC_MON = INTREG_PC, INTREG_R15_MON = INTREG_R15, INTREG_R0_ABT = INTREG_R0,
  INTREG_R1_ABT = INTREG_R1, INTREG_R2_ABT = INTREG_R2, INTREG_R3_ABT = INTREG_R3, INTREG_R4_ABT = INTREG_R4,
  INTREG_R5_ABT = INTREG_R5, INTREG_R6_ABT = INTREG_R6, INTREG_R7_ABT = INTREG_R7, INTREG_R8_ABT = INTREG_R8,
  INTREG_R9_ABT = INTREG_R9, INTREG_R10_ABT = INTREG_R10, INTREG_R11_ABT = INTREG_R11, INTREG_R12_ABT = INTREG_R12,
  INTREG_PC_ABT = INTREG_PC, INTREG_R15_ABT = INTREG_R15, INTREG_R0_HYP = INTREG_R0, INTREG_R1_HYP = INTREG_R1,
  INTREG_R2_HYP = INTREG_R2, INTREG_R3_HYP = INTREG_R3, INTREG_R4_HYP = INTREG_R4, INTREG_R5_HYP = INTREG_R5,
  INTREG_R6_HYP = INTREG_R6, INTREG_R7_HYP = INTREG_R7, INTREG_R8_HYP = INTREG_R8, INTREG_R9_HYP = INTREG_R9,
  INTREG_R10_HYP = INTREG_R10, INTREG_R11_HYP = INTREG_R11, INTREG_R12_HYP = INTREG_R12, INTREG_LR_HYP = INTREG_LR,
  INTREG_R14_HYP = INTREG_R14, INTREG_PC_HYP = INTREG_PC, INTREG_R15_HYP = INTREG_R15, INTREG_R0_UND = INTREG_R0,
  INTREG_R1_UND = INTREG_R1, INTREG_R2_UND = INTREG_R2, INTREG_R3_UND = INTREG_R3, INTREG_R4_UND = INTREG_R4,
  INTREG_R5_UND = INTREG_R5, INTREG_R6_UND = INTREG_R6, INTREG_R7_UND = INTREG_R7, INTREG_R8_UND = INTREG_R8,
  INTREG_R9_UND = INTREG_R9, INTREG_R10_UND = INTREG_R10, INTREG_R11_UND = INTREG_R11, INTREG_R12_UND = INTREG_R12,
  INTREG_PC_UND = INTREG_PC, INTREG_R15_UND = INTREG_R15, INTREG_R0_IRQ = INTREG_R0, INTREG_R1_IRQ = INTREG_R1,
  INTREG_R2_IRQ = INTREG_R2, INTREG_R3_IRQ = INTREG_R3, INTREG_R4_IRQ = INTREG_R4, INTREG_R5_IRQ = INTREG_R5,
  INTREG_R6_IRQ = INTREG_R6, INTREG_R7_IRQ = INTREG_R7, INTREG_R8_IRQ = INTREG_R8, INTREG_R9_IRQ = INTREG_R9,
  INTREG_R10_IRQ = INTREG_R10, INTREG_R11_IRQ = INTREG_R11, INTREG_R12_IRQ = INTREG_R12, INTREG_PC_IRQ = INTREG_PC,
  INTREG_R15_IRQ = INTREG_R15, INTREG_R0_FIQ = INTREG_R0, INTREG_R1_FIQ = INTREG_R1, INTREG_R2_FIQ = INTREG_R2,
  INTREG_R3_FIQ = INTREG_R3, INTREG_R4_FIQ = INTREG_R4, INTREG_R5_FIQ = INTREG_R5, INTREG_R6_FIQ = INTREG_R6,
  INTREG_R7_FIQ = INTREG_R7, INTREG_PC_FIQ = INTREG_PC, INTREG_R15_FIQ = INTREG_R15
}
 
enum  MiscRegIndex {
  MISCREG_CPSR = 0, MISCREG_SPSR, MISCREG_SPSR_FIQ, MISCREG_SPSR_IRQ,
  MISCREG_SPSR_SVC, MISCREG_SPSR_MON, MISCREG_SPSR_ABT, MISCREG_SPSR_HYP,
  MISCREG_SPSR_UND, MISCREG_ELR_HYP, MISCREG_FPSID, MISCREG_FPSCR,
  MISCREG_MVFR1, MISCREG_MVFR0, MISCREG_FPEXC, MISCREG_CPSR_MODE,
  MISCREG_CPSR_Q, MISCREG_FPSCR_EXC, MISCREG_FPSCR_QC, MISCREG_LOCKADDR,
  MISCREG_LOCKFLAG, MISCREG_PRRR_MAIR0, MISCREG_PRRR_MAIR0_NS, MISCREG_PRRR_MAIR0_S,
  MISCREG_NMRR_MAIR1, MISCREG_NMRR_MAIR1_NS, MISCREG_NMRR_MAIR1_S, MISCREG_PMXEVTYPER_PMCCFILTR,
  MISCREG_SCTLR_RST, MISCREG_SEV_MAILBOX, MISCREG_DBGDIDR, MISCREG_DBGDSCRint,
  MISCREG_DBGDCCINT, MISCREG_DBGDTRTXint, MISCREG_DBGDTRRXint, MISCREG_DBGWFAR,
  MISCREG_DBGVCR, MISCREG_DBGDTRRXext, MISCREG_DBGDSCRext, MISCREG_DBGDTRTXext,
  MISCREG_DBGOSECCR, MISCREG_DBGBVR0, MISCREG_DBGBVR1, MISCREG_DBGBVR2,
  MISCREG_DBGBVR3, MISCREG_DBGBVR4, MISCREG_DBGBVR5, MISCREG_DBGBVR6,
  MISCREG_DBGBVR7, MISCREG_DBGBVR8, MISCREG_DBGBVR9, MISCREG_DBGBVR10,
  MISCREG_DBGBVR11, MISCREG_DBGBVR12, MISCREG_DBGBVR13, MISCREG_DBGBVR14,
  MISCREG_DBGBVR15, MISCREG_DBGBCR0, MISCREG_DBGBCR1, MISCREG_DBGBCR2,
  MISCREG_DBGBCR3, MISCREG_DBGBCR4, MISCREG_DBGBCR5, MISCREG_DBGBCR6,
  MISCREG_DBGBCR7, MISCREG_DBGBCR8, MISCREG_DBGBCR9, MISCREG_DBGBCR10,
  MISCREG_DBGBCR11, MISCREG_DBGBCR12, MISCREG_DBGBCR13, MISCREG_DBGBCR14,
  MISCREG_DBGBCR15, MISCREG_DBGWVR0, MISCREG_DBGWVR1, MISCREG_DBGWVR2,
  MISCREG_DBGWVR3, MISCREG_DBGWVR4, MISCREG_DBGWVR5, MISCREG_DBGWVR6,
  MISCREG_DBGWVR7, MISCREG_DBGWVR8, MISCREG_DBGWVR9, MISCREG_DBGWVR10,
  MISCREG_DBGWVR11, MISCREG_DBGWVR12, MISCREG_DBGWVR13, MISCREG_DBGWVR14,
  MISCREG_DBGWVR15, MISCREG_DBGWCR0, MISCREG_DBGWCR1, MISCREG_DBGWCR2,
  MISCREG_DBGWCR3, MISCREG_DBGWCR4, MISCREG_DBGWCR5, MISCREG_DBGWCR6,
  MISCREG_DBGWCR7, MISCREG_DBGWCR8, MISCREG_DBGWCR9, MISCREG_DBGWCR10,
  MISCREG_DBGWCR11, MISCREG_DBGWCR12, MISCREG_DBGWCR13, MISCREG_DBGWCR14,
  MISCREG_DBGWCR15, MISCREG_DBGDRAR, MISCREG_DBGBXVR0, MISCREG_DBGBXVR1,
  MISCREG_DBGBXVR2, MISCREG_DBGBXVR3, MISCREG_DBGBXVR4, MISCREG_DBGBXVR5,
  MISCREG_DBGBXVR6, MISCREG_DBGBXVR7, MISCREG_DBGBXVR8, MISCREG_DBGBXVR9,
  MISCREG_DBGBXVR10, MISCREG_DBGBXVR11, MISCREG_DBGBXVR12, MISCREG_DBGBXVR13,
  MISCREG_DBGBXVR14, MISCREG_DBGBXVR15, MISCREG_DBGOSLAR, MISCREG_DBGOSLSR,
  MISCREG_DBGOSDLR, MISCREG_DBGPRCR, MISCREG_DBGDSAR, MISCREG_DBGCLAIMSET,
  MISCREG_DBGCLAIMCLR, MISCREG_DBGAUTHSTATUS, MISCREG_DBGDEVID2, MISCREG_DBGDEVID1,
  MISCREG_DBGDEVID0, MISCREG_TEECR, MISCREG_JIDR, MISCREG_TEEHBR,
  MISCREG_JOSCR, MISCREG_JMCR, MISCREG_MIDR, MISCREG_CTR,
  MISCREG_TCMTR, MISCREG_TLBTR, MISCREG_MPIDR, MISCREG_REVIDR,
  MISCREG_ID_PFR0, MISCREG_ID_PFR1, MISCREG_ID_DFR0, MISCREG_ID_AFR0,
  MISCREG_ID_MMFR0, MISCREG_ID_MMFR1, MISCREG_ID_MMFR2, MISCREG_ID_MMFR3,
  MISCREG_ID_ISAR0, MISCREG_ID_ISAR1, MISCREG_ID_ISAR2, MISCREG_ID_ISAR3,
  MISCREG_ID_ISAR4, MISCREG_ID_ISAR5, MISCREG_CCSIDR, MISCREG_CLIDR,
  MISCREG_AIDR, MISCREG_CSSELR, MISCREG_CSSELR_NS, MISCREG_CSSELR_S,
  MISCREG_VPIDR, MISCREG_VMPIDR, MISCREG_SCTLR, MISCREG_SCTLR_NS,
  MISCREG_SCTLR_S, MISCREG_ACTLR, MISCREG_ACTLR_NS, MISCREG_ACTLR_S,
  MISCREG_CPACR, MISCREG_SDCR, MISCREG_SCR, MISCREG_SDER,
  MISCREG_NSACR, MISCREG_HSCTLR, MISCREG_HACTLR, MISCREG_HCR,
  MISCREG_HCR2, MISCREG_HDCR, MISCREG_HCPTR, MISCREG_HSTR,
  MISCREG_HACR, MISCREG_TTBR0, MISCREG_TTBR0_NS, MISCREG_TTBR0_S,
  MISCREG_TTBR1, MISCREG_TTBR1_NS, MISCREG_TTBR1_S, MISCREG_TTBCR,
  MISCREG_TTBCR_NS, MISCREG_TTBCR_S, MISCREG_HTCR, MISCREG_VTCR,
  MISCREG_DACR, MISCREG_DACR_NS, MISCREG_DACR_S, MISCREG_DFSR,
  MISCREG_DFSR_NS, MISCREG_DFSR_S, MISCREG_IFSR, MISCREG_IFSR_NS,
  MISCREG_IFSR_S, MISCREG_ADFSR, MISCREG_ADFSR_NS, MISCREG_ADFSR_S,
  MISCREG_AIFSR, MISCREG_AIFSR_NS, MISCREG_AIFSR_S, MISCREG_HADFSR,
  MISCREG_HAIFSR, MISCREG_HSR, MISCREG_DFAR, MISCREG_DFAR_NS,
  MISCREG_DFAR_S, MISCREG_IFAR, MISCREG_IFAR_NS, MISCREG_IFAR_S,
  MISCREG_HDFAR, MISCREG_HIFAR, MISCREG_HPFAR, MISCREG_ICIALLUIS,
  MISCREG_BPIALLIS, MISCREG_PAR, MISCREG_PAR_NS, MISCREG_PAR_S,
  MISCREG_ICIALLU, MISCREG_ICIMVAU, MISCREG_CP15ISB, MISCREG_BPIALL,
  MISCREG_BPIMVA, MISCREG_DCIMVAC, MISCREG_DCISW, MISCREG_ATS1CPR,
  MISCREG_ATS1CPW, MISCREG_ATS1CUR, MISCREG_ATS1CUW, MISCREG_ATS12NSOPR,
  MISCREG_ATS12NSOPW, MISCREG_ATS12NSOUR, MISCREG_ATS12NSOUW, MISCREG_DCCMVAC,
  MISCREG_DCCSW, MISCREG_CP15DSB, MISCREG_CP15DMB, MISCREG_DCCMVAU,
  MISCREG_DCCIMVAC, MISCREG_DCCISW, MISCREG_ATS1HR, MISCREG_ATS1HW,
  MISCREG_TLBIALLIS, MISCREG_TLBIMVAIS, MISCREG_TLBIASIDIS, MISCREG_TLBIMVAAIS,
  MISCREG_TLBIMVALIS, MISCREG_TLBIMVAALIS, MISCREG_ITLBIALL, MISCREG_ITLBIMVA,
  MISCREG_ITLBIASID, MISCREG_DTLBIALL, MISCREG_DTLBIMVA, MISCREG_DTLBIASID,
  MISCREG_TLBIALL, MISCREG_TLBIMVA, MISCREG_TLBIASID, MISCREG_TLBIMVAA,
  MISCREG_TLBIMVAL, MISCREG_TLBIMVAAL, MISCREG_TLBIIPAS2IS, MISCREG_TLBIIPAS2LIS,
  MISCREG_TLBIALLHIS, MISCREG_TLBIMVAHIS, MISCREG_TLBIALLNSNHIS, MISCREG_TLBIMVALHIS,
  MISCREG_TLBIIPAS2, MISCREG_TLBIIPAS2L, MISCREG_TLBIALLH, MISCREG_TLBIMVAH,
  MISCREG_TLBIALLNSNH, MISCREG_TLBIMVALH, MISCREG_PMCR, MISCREG_PMCNTENSET,
  MISCREG_PMCNTENCLR, MISCREG_PMOVSR, MISCREG_PMSWINC, MISCREG_PMSELR,
  MISCREG_PMCEID0, MISCREG_PMCEID1, MISCREG_PMCCNTR, MISCREG_PMXEVTYPER,
  MISCREG_PMCCFILTR, MISCREG_PMXEVCNTR, MISCREG_PMUSERENR, MISCREG_PMINTENSET,
  MISCREG_PMINTENCLR, MISCREG_PMOVSSET, MISCREG_L2CTLR, MISCREG_L2ECTLR,
  MISCREG_PRRR, MISCREG_PRRR_NS, MISCREG_PRRR_S, MISCREG_MAIR0,
  MISCREG_MAIR0_NS, MISCREG_MAIR0_S, MISCREG_NMRR, MISCREG_NMRR_NS,
  MISCREG_NMRR_S, MISCREG_MAIR1, MISCREG_MAIR1_NS, MISCREG_MAIR1_S,
  MISCREG_AMAIR0, MISCREG_AMAIR0_NS, MISCREG_AMAIR0_S, MISCREG_AMAIR1,
  MISCREG_AMAIR1_NS, MISCREG_AMAIR1_S, MISCREG_HMAIR0, MISCREG_HMAIR1,
  MISCREG_HAMAIR0, MISCREG_HAMAIR1, MISCREG_VBAR, MISCREG_VBAR_NS,
  MISCREG_VBAR_S, MISCREG_MVBAR, MISCREG_RMR, MISCREG_ISR,
  MISCREG_HVBAR, MISCREG_FCSEIDR, MISCREG_CONTEXTIDR, MISCREG_CONTEXTIDR_NS,
  MISCREG_CONTEXTIDR_S, MISCREG_TPIDRURW, MISCREG_TPIDRURW_NS, MISCREG_TPIDRURW_S,
  MISCREG_TPIDRURO, MISCREG_TPIDRURO_NS, MISCREG_TPIDRURO_S, MISCREG_TPIDRPRW,
  MISCREG_TPIDRPRW_NS, MISCREG_TPIDRPRW_S, MISCREG_HTPIDR, MISCREG_CNTFRQ,
  MISCREG_CNTPCT, MISCREG_CNTVCT, MISCREG_CNTP_CTL, MISCREG_CNTP_CTL_NS,
  MISCREG_CNTP_CTL_S, MISCREG_CNTP_CVAL, MISCREG_CNTP_CVAL_NS, MISCREG_CNTP_CVAL_S,
  MISCREG_CNTP_TVAL, MISCREG_CNTP_TVAL_NS, MISCREG_CNTP_TVAL_S, MISCREG_CNTV_CTL,
  MISCREG_CNTV_CVAL, MISCREG_CNTV_TVAL, MISCREG_CNTKCTL, MISCREG_CNTHCTL,
  MISCREG_CNTHP_CTL, MISCREG_CNTHP_CVAL, MISCREG_CNTHP_TVAL, MISCREG_CNTVOFF,
  MISCREG_IL1DATA0, MISCREG_IL1DATA1, MISCREG_IL1DATA2, MISCREG_IL1DATA3,
  MISCREG_DL1DATA0, MISCREG_DL1DATA1, MISCREG_DL1DATA2, MISCREG_DL1DATA3,
  MISCREG_DL1DATA4, MISCREG_RAMINDEX, MISCREG_L2ACTLR, MISCREG_CBAR,
  MISCREG_HTTBR, MISCREG_VTTBR, MISCREG_CPUMERRSR, MISCREG_L2MERRSR,
  MISCREG_MDCCINT_EL1, MISCREG_OSDTRRX_EL1, MISCREG_MDSCR_EL1, MISCREG_OSDTRTX_EL1,
  MISCREG_OSECCR_EL1, MISCREG_DBGBVR0_EL1, MISCREG_DBGBVR1_EL1, MISCREG_DBGBVR2_EL1,
  MISCREG_DBGBVR3_EL1, MISCREG_DBGBVR4_EL1, MISCREG_DBGBVR5_EL1, MISCREG_DBGBVR6_EL1,
  MISCREG_DBGBVR7_EL1, MISCREG_DBGBVR8_EL1, MISCREG_DBGBVR9_EL1, MISCREG_DBGBVR10_EL1,
  MISCREG_DBGBVR11_EL1, MISCREG_DBGBVR12_EL1, MISCREG_DBGBVR13_EL1, MISCREG_DBGBVR14_EL1,
  MISCREG_DBGBVR15_EL1, MISCREG_DBGBCR0_EL1, MISCREG_DBGBCR1_EL1, MISCREG_DBGBCR2_EL1,
  MISCREG_DBGBCR3_EL1, MISCREG_DBGBCR4_EL1, MISCREG_DBGBCR5_EL1, MISCREG_DBGBCR6_EL1,
  MISCREG_DBGBCR7_EL1, MISCREG_DBGBCR8_EL1, MISCREG_DBGBCR9_EL1, MISCREG_DBGBCR10_EL1,
  MISCREG_DBGBCR11_EL1, MISCREG_DBGBCR12_EL1, MISCREG_DBGBCR13_EL1, MISCREG_DBGBCR14_EL1,
  MISCREG_DBGBCR15_EL1, MISCREG_DBGWVR0_EL1, MISCREG_DBGWVR1_EL1, MISCREG_DBGWVR2_EL1,
  MISCREG_DBGWVR3_EL1, MISCREG_DBGWVR4_EL1, MISCREG_DBGWVR5_EL1, MISCREG_DBGWVR6_EL1,
  MISCREG_DBGWVR7_EL1, MISCREG_DBGWVR8_EL1, MISCREG_DBGWVR9_EL1, MISCREG_DBGWVR10_EL1,
  MISCREG_DBGWVR11_EL1, MISCREG_DBGWVR12_EL1, MISCREG_DBGWVR13_EL1, MISCREG_DBGWVR14_EL1,
  MISCREG_DBGWVR15_EL1, MISCREG_DBGWCR0_EL1, MISCREG_DBGWCR1_EL1, MISCREG_DBGWCR2_EL1,
  MISCREG_DBGWCR3_EL1, MISCREG_DBGWCR4_EL1, MISCREG_DBGWCR5_EL1, MISCREG_DBGWCR6_EL1,
  MISCREG_DBGWCR7_EL1, MISCREG_DBGWCR8_EL1, MISCREG_DBGWCR9_EL1, MISCREG_DBGWCR10_EL1,
  MISCREG_DBGWCR11_EL1, MISCREG_DBGWCR12_EL1, MISCREG_DBGWCR13_EL1, MISCREG_DBGWCR14_EL1,
  MISCREG_DBGWCR15_EL1, MISCREG_MDCCSR_EL0, MISCREG_MDDTR_EL0, MISCREG_MDDTRTX_EL0,
  MISCREG_MDDTRRX_EL0, MISCREG_DBGVCR32_EL2, MISCREG_MDRAR_EL1, MISCREG_OSLAR_EL1,
  MISCREG_OSLSR_EL1, MISCREG_OSDLR_EL1, MISCREG_DBGPRCR_EL1, MISCREG_DBGCLAIMSET_EL1,
  MISCREG_DBGCLAIMCLR_EL1, MISCREG_DBGAUTHSTATUS_EL1, MISCREG_TEECR32_EL1, MISCREG_TEEHBR32_EL1,
  MISCREG_MIDR_EL1, MISCREG_MPIDR_EL1, MISCREG_REVIDR_EL1, MISCREG_ID_PFR0_EL1,
  MISCREG_ID_PFR1_EL1, MISCREG_ID_DFR0_EL1, MISCREG_ID_AFR0_EL1, MISCREG_ID_MMFR0_EL1,
  MISCREG_ID_MMFR1_EL1, MISCREG_ID_MMFR2_EL1, MISCREG_ID_MMFR3_EL1, MISCREG_ID_ISAR0_EL1,
  MISCREG_ID_ISAR1_EL1, MISCREG_ID_ISAR2_EL1, MISCREG_ID_ISAR3_EL1, MISCREG_ID_ISAR4_EL1,
  MISCREG_ID_ISAR5_EL1, MISCREG_MVFR0_EL1, MISCREG_MVFR1_EL1, MISCREG_MVFR2_EL1,
  MISCREG_ID_AA64PFR0_EL1, MISCREG_ID_AA64PFR1_EL1, MISCREG_ID_AA64DFR0_EL1, MISCREG_ID_AA64DFR1_EL1,
  MISCREG_ID_AA64AFR0_EL1, MISCREG_ID_AA64AFR1_EL1, MISCREG_ID_AA64ISAR0_EL1, MISCREG_ID_AA64ISAR1_EL1,
  MISCREG_ID_AA64MMFR0_EL1, MISCREG_ID_AA64MMFR1_EL1, MISCREG_CCSIDR_EL1, MISCREG_CLIDR_EL1,
  MISCREG_AIDR_EL1, MISCREG_CSSELR_EL1, MISCREG_CTR_EL0, MISCREG_DCZID_EL0,
  MISCREG_VPIDR_EL2, MISCREG_VMPIDR_EL2, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL12,
  MISCREG_ACTLR_EL1, MISCREG_CPACR_EL1, MISCREG_CPACR_EL12, MISCREG_SCTLR_EL2,
  MISCREG_ACTLR_EL2, MISCREG_HCR_EL2, MISCREG_MDCR_EL2, MISCREG_CPTR_EL2,
  MISCREG_HSTR_EL2, MISCREG_HACR_EL2, MISCREG_SCTLR_EL3, MISCREG_ACTLR_EL3,
  MISCREG_SCR_EL3, MISCREG_SDER32_EL3, MISCREG_CPTR_EL3, MISCREG_MDCR_EL3,
  MISCREG_TTBR0_EL1, MISCREG_TTBR0_EL12, MISCREG_TTBR1_EL1, MISCREG_TTBR1_EL12,
  MISCREG_TCR_EL1, MISCREG_TCR_EL12, MISCREG_TTBR0_EL2, MISCREG_TCR_EL2,
  MISCREG_VTTBR_EL2, MISCREG_VTCR_EL2, MISCREG_VSTTBR_EL2, MISCREG_VSTCR_EL2,
  MISCREG_TTBR0_EL3, MISCREG_TCR_EL3, MISCREG_DACR32_EL2, MISCREG_SPSR_EL1,
  MISCREG_SPSR_EL12, MISCREG_ELR_EL1, MISCREG_ELR_EL12, MISCREG_SP_EL0,
  MISCREG_SPSEL, MISCREG_CURRENTEL, MISCREG_NZCV, MISCREG_DAIF,
  MISCREG_FPCR, MISCREG_FPSR, MISCREG_DSPSR_EL0, MISCREG_DLR_EL0,
  MISCREG_SPSR_EL2, MISCREG_ELR_EL2, MISCREG_SP_EL1, MISCREG_SPSR_IRQ_AA64,
  MISCREG_SPSR_ABT_AA64, MISCREG_SPSR_UND_AA64, MISCREG_SPSR_FIQ_AA64, MISCREG_SPSR_EL3,
  MISCREG_ELR_EL3, MISCREG_SP_EL2, MISCREG_AFSR0_EL1, MISCREG_AFSR0_EL12,
  MISCREG_AFSR1_EL1, MISCREG_AFSR1_EL12, MISCREG_ESR_EL1, MISCREG_ESR_EL12,
  MISCREG_IFSR32_EL2, MISCREG_AFSR0_EL2, MISCREG_AFSR1_EL2, MISCREG_ESR_EL2,
  MISCREG_FPEXC32_EL2, MISCREG_AFSR0_EL3, MISCREG_AFSR1_EL3, MISCREG_ESR_EL3,
  MISCREG_FAR_EL1, MISCREG_FAR_EL12, MISCREG_FAR_EL2, MISCREG_HPFAR_EL2,
  MISCREG_FAR_EL3, MISCREG_IC_IALLUIS, MISCREG_PAR_EL1, MISCREG_IC_IALLU,
  MISCREG_DC_IVAC_Xt, MISCREG_DC_ISW_Xt, MISCREG_AT_S1E1R_Xt, MISCREG_AT_S1E1W_Xt,
  MISCREG_AT_S1E0R_Xt, MISCREG_AT_S1E0W_Xt, MISCREG_DC_CSW_Xt, MISCREG_DC_CISW_Xt,
  MISCREG_DC_ZVA_Xt, MISCREG_IC_IVAU_Xt, MISCREG_DC_CVAC_Xt, MISCREG_DC_CVAU_Xt,
  MISCREG_DC_CIVAC_Xt, MISCREG_AT_S1E2R_Xt, MISCREG_AT_S1E2W_Xt, MISCREG_AT_S12E1R_Xt,
  MISCREG_AT_S12E1W_Xt, MISCREG_AT_S12E0R_Xt, MISCREG_AT_S12E0W_Xt, MISCREG_AT_S1E3R_Xt,
  MISCREG_AT_S1E3W_Xt, MISCREG_TLBI_VMALLE1IS, MISCREG_TLBI_VAE1IS_Xt, MISCREG_TLBI_ASIDE1IS_Xt,
  MISCREG_TLBI_VAAE1IS_Xt, MISCREG_TLBI_VALE1IS_Xt, MISCREG_TLBI_VAALE1IS_Xt, MISCREG_TLBI_VMALLE1,
  MISCREG_TLBI_VAE1_Xt, MISCREG_TLBI_ASIDE1_Xt, MISCREG_TLBI_VAAE1_Xt, MISCREG_TLBI_VALE1_Xt,
  MISCREG_TLBI_VAALE1_Xt, MISCREG_TLBI_IPAS2E1IS_Xt, MISCREG_TLBI_IPAS2LE1IS_Xt, MISCREG_TLBI_ALLE2IS,
  MISCREG_TLBI_VAE2IS_Xt, MISCREG_TLBI_ALLE1IS, MISCREG_TLBI_VALE2IS_Xt, MISCREG_TLBI_VMALLS12E1IS,
  MISCREG_TLBI_IPAS2E1_Xt, MISCREG_TLBI_IPAS2LE1_Xt, MISCREG_TLBI_ALLE2, MISCREG_TLBI_VAE2_Xt,
  MISCREG_TLBI_ALLE1, MISCREG_TLBI_VALE2_Xt, MISCREG_TLBI_VMALLS12E1, MISCREG_TLBI_ALLE3IS,
  MISCREG_TLBI_VAE3IS_Xt, MISCREG_TLBI_VALE3IS_Xt, MISCREG_TLBI_ALLE3, MISCREG_TLBI_VAE3_Xt,
  MISCREG_TLBI_VALE3_Xt, MISCREG_PMINTENSET_EL1, MISCREG_PMINTENCLR_EL1, MISCREG_PMCR_EL0,
  MISCREG_PMCNTENSET_EL0, MISCREG_PMCNTENCLR_EL0, MISCREG_PMOVSCLR_EL0, MISCREG_PMSWINC_EL0,
  MISCREG_PMSELR_EL0, MISCREG_PMCEID0_EL0, MISCREG_PMCEID1_EL0, MISCREG_PMCCNTR_EL0,
  MISCREG_PMXEVTYPER_EL0, MISCREG_PMCCFILTR_EL0, MISCREG_PMXEVCNTR_EL0, MISCREG_PMUSERENR_EL0,
  MISCREG_PMOVSSET_EL0, MISCREG_MAIR_EL1, MISCREG_MAIR_EL12, MISCREG_AMAIR_EL1,
  MISCREG_AMAIR_EL12, MISCREG_MAIR_EL2, MISCREG_AMAIR_EL2, MISCREG_MAIR_EL3,
  MISCREG_AMAIR_EL3, MISCREG_L2CTLR_EL1, MISCREG_L2ECTLR_EL1, MISCREG_VBAR_EL1,
  MISCREG_VBAR_EL12, MISCREG_RVBAR_EL1, MISCREG_ISR_EL1, MISCREG_VBAR_EL2,
  MISCREG_RVBAR_EL2, MISCREG_VBAR_EL3, MISCREG_RVBAR_EL3, MISCREG_RMR_EL3,
  MISCREG_CONTEXTIDR_EL1, MISCREG_CONTEXTIDR_EL12, MISCREG_TPIDR_EL1, MISCREG_TPIDR_EL0,
  MISCREG_TPIDRRO_EL0, MISCREG_TPIDR_EL2, MISCREG_TPIDR_EL3, MISCREG_CNTFRQ_EL0,
  MISCREG_CNTPCT_EL0, MISCREG_CNTVCT_EL0, MISCREG_CNTP_CTL_EL0, MISCREG_CNTP_CVAL_EL0,
  MISCREG_CNTP_TVAL_EL0, MISCREG_CNTV_CTL_EL0, MISCREG_CNTV_CVAL_EL0, MISCREG_CNTV_TVAL_EL0,
  MISCREG_CNTP_CTL_EL02, MISCREG_CNTP_CVAL_EL02, MISCREG_CNTP_TVAL_EL02, MISCREG_CNTV_CTL_EL02,
  MISCREG_CNTV_CVAL_EL02, MISCREG_CNTV_TVAL_EL02, MISCREG_CNTKCTL_EL1, MISCREG_CNTKCTL_EL12,
  MISCREG_CNTPS_CTL_EL1, MISCREG_CNTPS_CVAL_EL1, MISCREG_CNTPS_TVAL_EL1, MISCREG_CNTHCTL_EL2,
  MISCREG_CNTHP_CTL_EL2, MISCREG_CNTHP_CVAL_EL2, MISCREG_CNTHP_TVAL_EL2, MISCREG_CNTHPS_CTL_EL2,
  MISCREG_CNTHPS_CVAL_EL2, MISCREG_CNTHPS_TVAL_EL2, MISCREG_CNTHV_CTL_EL2, MISCREG_CNTHV_CVAL_EL2,
  MISCREG_CNTHV_TVAL_EL2, MISCREG_CNTHVS_CTL_EL2, MISCREG_CNTHVS_CVAL_EL2, MISCREG_CNTHVS_TVAL_EL2,
  MISCREG_CNTVOFF_EL2, MISCREG_PMEVCNTR0_EL0, MISCREG_PMEVCNTR1_EL0, MISCREG_PMEVCNTR2_EL0,
  MISCREG_PMEVCNTR3_EL0, MISCREG_PMEVCNTR4_EL0, MISCREG_PMEVCNTR5_EL0, MISCREG_PMEVTYPER0_EL0,
  MISCREG_PMEVTYPER1_EL0, MISCREG_PMEVTYPER2_EL0, MISCREG_PMEVTYPER3_EL0, MISCREG_PMEVTYPER4_EL0,
  MISCREG_PMEVTYPER5_EL0, MISCREG_IL1DATA0_EL1, MISCREG_IL1DATA1_EL1, MISCREG_IL1DATA2_EL1,
  MISCREG_IL1DATA3_EL1, MISCREG_DL1DATA0_EL1, MISCREG_DL1DATA1_EL1, MISCREG_DL1DATA2_EL1,
  MISCREG_DL1DATA3_EL1, MISCREG_DL1DATA4_EL1, MISCREG_L2ACTLR_EL1, MISCREG_CPUACTLR_EL1,
  MISCREG_CPUECTLR_EL1, MISCREG_CPUMERRSR_EL1, MISCREG_L2MERRSR_EL1, MISCREG_CBAR_EL1,
  MISCREG_CONTEXTIDR_EL2, MISCREG_TTBR1_EL2, MISCREG_ID_AA64MMFR2_EL1, MISCREG_APDAKeyHi_EL1,
  MISCREG_APDAKeyLo_EL1, MISCREG_APDBKeyHi_EL1, MISCREG_APDBKeyLo_EL1, MISCREG_APGAKeyHi_EL1,
  MISCREG_APGAKeyLo_EL1, MISCREG_APIAKeyHi_EL1, MISCREG_APIAKeyLo_EL1, MISCREG_APIBKeyHi_EL1,
  MISCREG_APIBKeyLo_EL1, MISCREG_ICC_PMR_EL1, MISCREG_ICC_IAR0_EL1, MISCREG_ICC_EOIR0_EL1,
  MISCREG_ICC_HPPIR0_EL1, MISCREG_ICC_BPR0_EL1, MISCREG_ICC_AP0R0_EL1, MISCREG_ICC_AP0R1_EL1,
  MISCREG_ICC_AP0R2_EL1, MISCREG_ICC_AP0R3_EL1, MISCREG_ICC_AP1R0_EL1, MISCREG_ICC_AP1R0_EL1_NS,
  MISCREG_ICC_AP1R0_EL1_S, MISCREG_ICC_AP1R1_EL1, MISCREG_ICC_AP1R1_EL1_NS, MISCREG_ICC_AP1R1_EL1_S,
  MISCREG_ICC_AP1R2_EL1, MISCREG_ICC_AP1R2_EL1_NS, MISCREG_ICC_AP1R2_EL1_S, MISCREG_ICC_AP1R3_EL1,
  MISCREG_ICC_AP1R3_EL1_NS, MISCREG_ICC_AP1R3_EL1_S, MISCREG_ICC_DIR_EL1, MISCREG_ICC_RPR_EL1,
  MISCREG_ICC_SGI1R_EL1, MISCREG_ICC_ASGI1R_EL1, MISCREG_ICC_SGI0R_EL1, MISCREG_ICC_IAR1_EL1,
  MISCREG_ICC_EOIR1_EL1, MISCREG_ICC_HPPIR1_EL1, MISCREG_ICC_BPR1_EL1, MISCREG_ICC_BPR1_EL1_NS,
  MISCREG_ICC_BPR1_EL1_S, MISCREG_ICC_CTLR_EL1, MISCREG_ICC_CTLR_EL1_NS, MISCREG_ICC_CTLR_EL1_S,
  MISCREG_ICC_SRE_EL1, MISCREG_ICC_SRE_EL1_NS, MISCREG_ICC_SRE_EL1_S, MISCREG_ICC_IGRPEN0_EL1,
  MISCREG_ICC_IGRPEN1_EL1, MISCREG_ICC_IGRPEN1_EL1_NS, MISCREG_ICC_IGRPEN1_EL1_S, MISCREG_ICC_SRE_EL2,
  MISCREG_ICC_CTLR_EL3, MISCREG_ICC_SRE_EL3, MISCREG_ICC_IGRPEN1_EL3, MISCREG_ICH_AP0R0_EL2,
  MISCREG_ICH_AP0R1_EL2, MISCREG_ICH_AP0R2_EL2, MISCREG_ICH_AP0R3_EL2, MISCREG_ICH_AP1R0_EL2,
  MISCREG_ICH_AP1R1_EL2, MISCREG_ICH_AP1R2_EL2, MISCREG_ICH_AP1R3_EL2, MISCREG_ICH_HCR_EL2,
  MISCREG_ICH_VTR_EL2, MISCREG_ICH_MISR_EL2, MISCREG_ICH_EISR_EL2, MISCREG_ICH_ELRSR_EL2,
  MISCREG_ICH_VMCR_EL2, MISCREG_ICH_LR0_EL2, MISCREG_ICH_LR1_EL2, MISCREG_ICH_LR2_EL2,
  MISCREG_ICH_LR3_EL2, MISCREG_ICH_LR4_EL2, MISCREG_ICH_LR5_EL2, MISCREG_ICH_LR6_EL2,
  MISCREG_ICH_LR7_EL2, MISCREG_ICH_LR8_EL2, MISCREG_ICH_LR9_EL2, MISCREG_ICH_LR10_EL2,
  MISCREG_ICH_LR11_EL2, MISCREG_ICH_LR12_EL2, MISCREG_ICH_LR13_EL2, MISCREG_ICH_LR14_EL2,
  MISCREG_ICH_LR15_EL2, MISCREG_ICV_PMR_EL1, MISCREG_ICV_IAR0_EL1, MISCREG_ICV_EOIR0_EL1,
  MISCREG_ICV_HPPIR0_EL1, MISCREG_ICV_BPR0_EL1, MISCREG_ICV_AP0R0_EL1, MISCREG_ICV_AP0R1_EL1,
  MISCREG_ICV_AP0R2_EL1, MISCREG_ICV_AP0R3_EL1, MISCREG_ICV_AP1R0_EL1, MISCREG_ICV_AP1R0_EL1_NS,
  MISCREG_ICV_AP1R0_EL1_S, MISCREG_ICV_AP1R1_EL1, MISCREG_ICV_AP1R1_EL1_NS, MISCREG_ICV_AP1R1_EL1_S,
  MISCREG_ICV_AP1R2_EL1, MISCREG_ICV_AP1R2_EL1_NS, MISCREG_ICV_AP1R2_EL1_S, MISCREG_ICV_AP1R3_EL1,
  MISCREG_ICV_AP1R3_EL1_NS, MISCREG_ICV_AP1R3_EL1_S, MISCREG_ICV_DIR_EL1, MISCREG_ICV_RPR_EL1,
  MISCREG_ICV_SGI1R_EL1, MISCREG_ICV_ASGI1R_EL1, MISCREG_ICV_SGI0R_EL1, MISCREG_ICV_IAR1_EL1,
  MISCREG_ICV_EOIR1_EL1, MISCREG_ICV_HPPIR1_EL1, MISCREG_ICV_BPR1_EL1, MISCREG_ICV_BPR1_EL1_NS,
  MISCREG_ICV_BPR1_EL1_S, MISCREG_ICV_CTLR_EL1, MISCREG_ICV_CTLR_EL1_NS, MISCREG_ICV_CTLR_EL1_S,
  MISCREG_ICV_SRE_EL1, MISCREG_ICV_SRE_EL1_NS, MISCREG_ICV_SRE_EL1_S, MISCREG_ICV_IGRPEN0_EL1,
  MISCREG_ICV_IGRPEN1_EL1, MISCREG_ICV_IGRPEN1_EL1_NS, MISCREG_ICV_IGRPEN1_EL1_S, MISCREG_ICC_AP0R0,
  MISCREG_ICC_AP0R1, MISCREG_ICC_AP0R2, MISCREG_ICC_AP0R3, MISCREG_ICC_AP1R0,
  MISCREG_ICC_AP1R0_NS, MISCREG_ICC_AP1R0_S, MISCREG_ICC_AP1R1, MISCREG_ICC_AP1R1_NS,
  MISCREG_ICC_AP1R1_S, MISCREG_ICC_AP1R2, MISCREG_ICC_AP1R2_NS, MISCREG_ICC_AP1R2_S,
  MISCREG_ICC_AP1R3, MISCREG_ICC_AP1R3_NS, MISCREG_ICC_AP1R3_S, MISCREG_ICC_ASGI1R,
  MISCREG_ICC_BPR0, MISCREG_ICC_BPR1, MISCREG_ICC_BPR1_NS, MISCREG_ICC_BPR1_S,
  MISCREG_ICC_CTLR, MISCREG_ICC_CTLR_NS, MISCREG_ICC_CTLR_S, MISCREG_ICC_DIR,
  MISCREG_ICC_EOIR0, MISCREG_ICC_EOIR1, MISCREG_ICC_HPPIR0, MISCREG_ICC_HPPIR1,
  MISCREG_ICC_HSRE, MISCREG_ICC_IAR0, MISCREG_ICC_IAR1, MISCREG_ICC_IGRPEN0,
  MISCREG_ICC_IGRPEN1, MISCREG_ICC_IGRPEN1_NS, MISCREG_ICC_IGRPEN1_S, MISCREG_ICC_MCTLR,
  MISCREG_ICC_MGRPEN1, MISCREG_ICC_MSRE, MISCREG_ICC_PMR, MISCREG_ICC_RPR,
  MISCREG_ICC_SGI0R, MISCREG_ICC_SGI1R, MISCREG_ICC_SRE, MISCREG_ICC_SRE_NS,
  MISCREG_ICC_SRE_S, MISCREG_ICH_AP0R0, MISCREG_ICH_AP0R1, MISCREG_ICH_AP0R2,
  MISCREG_ICH_AP0R3, MISCREG_ICH_AP1R0, MISCREG_ICH_AP1R1, MISCREG_ICH_AP1R2,
  MISCREG_ICH_AP1R3, MISCREG_ICH_HCR, MISCREG_ICH_VTR, MISCREG_ICH_MISR,
  MISCREG_ICH_EISR, MISCREG_ICH_ELRSR, MISCREG_ICH_VMCR, MISCREG_ICH_LR0,
  MISCREG_ICH_LR1, MISCREG_ICH_LR2, MISCREG_ICH_LR3, MISCREG_ICH_LR4,
  MISCREG_ICH_LR5, MISCREG_ICH_LR6, MISCREG_ICH_LR7, MISCREG_ICH_LR8,
  MISCREG_ICH_LR9, MISCREG_ICH_LR10, MISCREG_ICH_LR11, MISCREG_ICH_LR12,
  MISCREG_ICH_LR13, MISCREG_ICH_LR14, MISCREG_ICH_LR15, MISCREG_ICH_LRC0,
  MISCREG_ICH_LRC1, MISCREG_ICH_LRC2, MISCREG_ICH_LRC3, MISCREG_ICH_LRC4,
  MISCREG_ICH_LRC5, MISCREG_ICH_LRC6, MISCREG_ICH_LRC7, MISCREG_ICH_LRC8,
  MISCREG_ICH_LRC9, MISCREG_ICH_LRC10, MISCREG_ICH_LRC11, MISCREG_ICH_LRC12,
  MISCREG_ICH_LRC13, MISCREG_ICH_LRC14, MISCREG_ICH_LRC15, MISCREG_ID_AA64ZFR0_EL1,
  MISCREG_ZCR_EL3, MISCREG_ZCR_EL2, MISCREG_ZCR_EL12, MISCREG_ZCR_EL1,
  NUM_PHYS_MISCREGS, MISCREG_NOP, MISCREG_RAZ, MISCREG_CP14_UNIMPL,
  MISCREG_CP15_UNIMPL, MISCREG_UNKNOWN, MISCREG_IMPDEF_UNIMPL, MISCREG_ERRIDR_EL1,
  MISCREG_ERRSELR_EL1, MISCREG_ERXFR_EL1, MISCREG_ERXCTLR_EL1, MISCREG_ERXSTATUS_EL1,
  MISCREG_ERXADDR_EL1, MISCREG_ERXMISC0_EL1, MISCREG_ERXMISC1_EL1, MISCREG_DISR_EL1,
  MISCREG_VSESR_EL2, MISCREG_VDISR_EL2, MISCREG_PAN, NUM_MISCREGS
}
 
enum  MiscRegInfo {
  MISCREG_IMPLEMENTED, MISCREG_UNVERIFIABLE, MISCREG_WARN_NOT_FAIL, MISCREG_MUTEX,
  MISCREG_BANKED, MISCREG_BANKED64, MISCREG_BANKED_CHILD, MISCREG_USR_NS_RD,
  MISCREG_USR_NS_WR, MISCREG_USR_S_RD, MISCREG_USR_S_WR, MISCREG_PRI_NS_RD,
  MISCREG_PRI_NS_WR, MISCREG_PRI_S_RD, MISCREG_PRI_S_WR, MISCREG_HYP_RD,
  MISCREG_HYP_WR, MISCREG_HYP_E2H_RD, MISCREG_HYP_E2H_WR, MISCREG_MON_NS0_RD,
  MISCREG_MON_NS0_WR, MISCREG_MON_NS1_RD, MISCREG_MON_NS1_WR, MISCREG_MON_E2H_RD,
  MISCREG_MON_E2H_WR, NUM_MISCREG_INFOS
}
 
enum  LookupLevel {
  L0 = 0, L1, L2, L3,
  MAX_LOOKUP_LEVELS
}
 
enum  ArmShiftType { LSL = 0, LSR, ASR, ROR }
 
enum  ArmExtendType {
  UXTB = 0, UXTH = 1, UXTW = 2, UXTX = 3,
  SXTB = 4, SXTH = 5, SXTW = 6, SXTX = 7
}
 
enum  ConvertType {
  SINGLE_TO_DOUBLE, SINGLE_TO_WORD, SINGLE_TO_LONG, DOUBLE_TO_SINGLE,
  DOUBLE_TO_WORD, DOUBLE_TO_LONG, LONG_TO_SINGLE, LONG_TO_DOUBLE,
  LONG_TO_WORD, LONG_TO_PS, WORD_TO_SINGLE, WORD_TO_DOUBLE,
  WORD_TO_LONG, WORD_TO_PS, PL_TO_SINGLE, PU_TO_SINGLE
}
 
enum  RoundMode { RND_ZERO, RND_DOWN, RND_UP, RND_NEAREST }
 
enum  ExceptionLevel { EL0 = 0, EL1, EL2, EL3 }
 
enum  OperatingMode {
  MODE_EL0T = 0x0, MODE_EL1T = 0x4, MODE_EL1H = 0x5, MODE_EL2T = 0x8,
  MODE_EL2H = 0x9, MODE_EL3T = 0xC, MODE_EL3H = 0xD, MODE_USER = 16,
  MODE_FIQ = 17, MODE_IRQ = 18, MODE_SVC = 19, MODE_MON = 22,
  MODE_ABORT = 23, MODE_HYP = 26, MODE_UNDEFINED = 27, MODE_SYSTEM = 31,
  MODE_MAXMODE = MODE_SYSTEM
}
 
enum  ExceptionClass {
  EC_INVALID = -1, EC_UNKNOWN = 0x0, EC_TRAPPED_WFI_WFE = 0x1, EC_TRAPPED_CP15_MCR_MRC = 0x3,
  EC_TRAPPED_CP15_MCRR_MRRC = 0x4, EC_TRAPPED_CP14_MCR_MRC = 0x5, EC_TRAPPED_CP14_LDC_STC = 0x6, EC_TRAPPED_HCPTR = 0x7,
  EC_TRAPPED_SIMD_FP = 0x7, EC_TRAPPED_CP10_MRC_VMRS = 0x8, EC_TRAPPED_PAC = 0x9, EC_TRAPPED_BXJ = 0xA,
  EC_TRAPPED_CP14_MCRR_MRRC = 0xC, EC_ILLEGAL_INST = 0xE, EC_SVC_TO_HYP = 0x11, EC_SVC = 0x11,
  EC_HVC = 0x12, EC_SMC_TO_HYP = 0x13, EC_SMC = 0x13, EC_SVC_64 = 0x15,
  EC_HVC_64 = 0x16, EC_SMC_64 = 0x17, EC_TRAPPED_MSR_MRS_64 = 0x18, EC_TRAPPED_SVE = 0x19,
  EC_PREFETCH_ABORT_TO_HYP = 0x20, EC_PREFETCH_ABORT_LOWER_EL = 0x20, EC_PREFETCH_ABORT_FROM_HYP = 0x21, EC_PREFETCH_ABORT_CURR_EL = 0x21,
  EC_PC_ALIGNMENT = 0x22, EC_DATA_ABORT_TO_HYP = 0x24, EC_DATA_ABORT_LOWER_EL = 0x24, EC_DATA_ABORT_FROM_HYP = 0x25,
  EC_DATA_ABORT_CURR_EL = 0x25, EC_STACK_PTR_ALIGNMENT = 0x26, EC_FP_EXCEPTION = 0x28, EC_FP_EXCEPTION_64 = 0x2C,
  EC_SERROR = 0x2F, EC_HW_BREAKPOINT = 0x30, EC_HW_BREAKPOINT_LOWER_EL = 0x30, EC_HW_BREAKPOINT_CURR_EL = 0x31,
  EC_SOFTWARE_STEP = 0x32, EC_SOFTWARE_STEP_LOWER_EL = 0x32, EC_SOFTWARE_STEP_CURR_EL = 0x33, EC_WATCHPOINT = 0x34,
  EC_WATCHPOINT_LOWER_EL = 0x34, EC_WATCHPOINT_CURR_EL = 0x35, EC_SOFTWARE_BREAKPOINT = 0x38, EC_VECTOR_CATCH = 0x3A,
  EC_SOFTWARE_BREAKPOINT_64 = 0x3C
}
 
enum  DecoderFault : std::uint8_t { OK = 0x0, UNALIGNED = 0x1, PANIC = 0x3 }
 Instruction decoder fault codes in ExtMachInst. More...
 

Functions

bool getFaultVAddr (Fault fault, Addr &va)
 Returns true if the fault passed as a first argument was triggered by a memory access, false otherwise. More...
 
static uint16_t lsl16 (uint16_t x, uint32_t shift)
 
static uint16_t lsr16 (uint16_t x, uint32_t shift)
 
static uint32_t lsl32 (uint32_t x, uint32_t shift)
 
static uint32_t lsr32 (uint32_t x, uint32_t shift)
 
static uint64_t lsl64 (uint64_t x, uint32_t shift)
 
static uint64_t lsr64 (uint64_t x, uint32_t shift)
 
static void lsl128 (uint64_t *r0, uint64_t *r1, uint64_t x0, uint64_t x1, uint32_t shift)
 
static void lsr128 (uint64_t *r0, uint64_t *r1, uint64_t x0, uint64_t x1, uint32_t shift)
 
static void mul62x62 (uint64_t *x0, uint64_t *x1, uint64_t a, uint64_t b)
 
static void mul64x32 (uint64_t *x0, uint64_t *x1, uint64_t a, uint32_t b)
 
static void add128 (uint64_t *x0, uint64_t *x1, uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1)
 
static void sub128 (uint64_t *x0, uint64_t *x1, uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1)
 
static int cmp128 (uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1)
 
static uint16_t fp16_normalise (uint16_t mnt, int *exp)
 
static uint32_t fp32_normalise (uint32_t mnt, int *exp)
 
static uint64_t fp64_normalise (uint64_t mnt, int *exp)
 
static void fp128_normalise (uint64_t *mnt0, uint64_t *mnt1, int *exp)
 
static uint16_t fp16_pack (uint16_t sgn, uint16_t exp, uint16_t mnt)
 
static uint32_t fp32_pack (uint32_t sgn, uint32_t exp, uint32_t mnt)
 
static uint64_t fp64_pack (uint64_t sgn, uint64_t exp, uint64_t mnt)
 
static uint16_t fp16_zero (int sgn)
 
static uint32_t fp32_zero (int sgn)
 
static uint64_t fp64_zero (int sgn)
 
static uint16_t fp16_max_normal (int sgn)
 
static uint32_t fp32_max_normal (int sgn)
 
static uint64_t fp64_max_normal (int sgn)
 
static uint16_t fp16_infinity (int sgn)
 
static uint32_t fp32_infinity (int sgn)
 
static uint64_t fp64_infinity (int sgn)
 
static uint16_t fp16_defaultNaN ()
 
static uint32_t fp32_defaultNaN ()
 
static uint64_t fp64_defaultNaN ()
 
static void fp16_unpack (int *sgn, int *exp, uint16_t *mnt, uint16_t x, int mode, int *flags)
 
static void fp32_unpack (int *sgn, int *exp, uint32_t *mnt, uint32_t x, int mode, int *flags)
 
static void fp64_unpack (int *sgn, int *exp, uint64_t *mnt, uint64_t x, int mode, int *flags)
 
static int fp16_is_NaN (int exp, uint16_t mnt)
 
static int fp32_is_NaN (int exp, uint32_t mnt)
 
static int fp64_is_NaN (int exp, uint64_t mnt)
 
static int fp16_is_signalling_NaN (int exp, uint16_t mnt)
 
static int fp32_is_signalling_NaN (int exp, uint32_t mnt)
 
static int fp64_is_signalling_NaN (int exp, uint64_t mnt)
 
static int fp16_is_quiet_NaN (int exp, uint16_t mnt)
 
static int fp32_is_quiet_NaN (int exp, uint32_t mnt)
 
static int fp64_is_quiet_NaN (int exp, uint64_t mnt)
 
static int fp16_is_infinity (int exp, uint16_t mnt)
 
static int fp32_is_infinity (int exp, uint32_t mnt)
 
static int fp64_is_infinity (int exp, uint64_t mnt)
 
static uint16_t fp16_process_NaN (uint16_t a, int mode, int *flags)
 
static uint32_t fp32_process_NaN (uint32_t a, int mode, int *flags)
 
static uint64_t fp64_process_NaN (uint64_t a, int mode, int *flags)
 
static uint16_t fp16_process_NaNs (uint16_t a, uint16_t b, int mode, int *flags)
 
static uint32_t fp32_process_NaNs (uint32_t a, uint32_t b, int mode, int *flags)
 
static uint64_t fp64_process_NaNs (uint64_t a, uint64_t b, int mode, int *flags)
 
static uint16_t fp16_process_NaNs3 (uint16_t a, uint16_t b, uint16_t c, int mode, int *flags)
 
static uint32_t fp32_process_NaNs3 (uint32_t a, uint32_t b, uint32_t c, int mode, int *flags)
 
static uint64_t fp64_process_NaNs3 (uint64_t a, uint64_t b, uint64_t c, int mode, int *flags)
 
static uint16_t fp16_round_ (int sgn, int exp, uint16_t mnt, int rm, int mode, int *flags)
 
static uint16_t fp16_round (int sgn, int exp, uint16_t mnt, int mode, int *flags)
 
static uint32_t fp32_round_ (int sgn, int exp, uint32_t mnt, int rm, int mode, int *flags)
 
static uint32_t fp32_round (int sgn, int exp, uint32_t mnt, int mode, int *flags)
 
static uint64_t fp64_round_ (int sgn, int exp, uint64_t mnt, int rm, int mode, int *flags)
 
static uint64_t fp64_round (int sgn, int exp, uint64_t mnt, int mode, int *flags)
 
static int fp16_compare_eq (uint16_t a, uint16_t b, int mode, int *flags)
 
static int fp16_compare_ge (uint16_t a, uint16_t b, int mode, int *flags)
 
static int fp16_compare_gt (uint16_t a, uint16_t b, int mode, int *flags)
 
static int fp16_compare_un (uint16_t a, uint16_t b, int mode, int *flags)
 
static int fp32_compare_eq (uint32_t a, uint32_t b, int mode, int *flags)
 
static int fp32_compare_ge (uint32_t a, uint32_t b, int mode, int *flags)
 
static int fp32_compare_gt (uint32_t a, uint32_t b, int mode, int *flags)
 
static int fp32_compare_un (uint32_t a, uint32_t b, int mode, int *flags)
 
static int fp64_compare_eq (uint64_t a, uint64_t b, int mode, int *flags)
 
static int fp64_compare_ge (uint64_t a, uint64_t b, int mode, int *flags)
 
static int fp64_compare_gt (uint64_t a, uint64_t b, int mode, int *flags)
 
static int fp64_compare_un (uint64_t a, uint64_t b, int mode, int *flags)
 
static uint16_t fp16_add (uint16_t a, uint16_t b, int neg, int mode, int *flags)
 
static uint32_t fp32_add (uint32_t a, uint32_t b, int neg, int mode, int *flags)
 
static uint64_t fp64_add (uint64_t a, uint64_t b, int neg, int mode, int *flags)
 
static uint16_t fp16_mul (uint16_t a, uint16_t b, int mode, int *flags)
 
static uint32_t fp32_mul (uint32_t a, uint32_t b, int mode, int *flags)
 
static uint64_t fp64_mul (uint64_t a, uint64_t b, int mode, int *flags)
 
static uint16_t fp16_muladd (uint16_t a, uint16_t b, uint16_t c, int scale, int mode, int *flags)
 
static uint32_t fp32_muladd (uint32_t a, uint32_t b, uint32_t c, int scale, int mode, int *flags)
 
static uint64_t fp64_muladd (uint64_t a, uint64_t b, uint64_t c, int scale, int mode, int *flags)
 
static uint16_t fp16_div (uint16_t a, uint16_t b, int mode, int *flags)
 
static uint32_t fp32_div (uint32_t a, uint32_t b, int mode, int *flags)
 
static uint64_t fp64_div (uint64_t a, uint64_t b, int mode, int *flags)
 
static void set_fpscr0 (FPSCR &fpscr, int flags)
 
static uint16_t fp16_scale (uint16_t a, int16_t b, int mode, int *flags)
 
static uint32_t fp32_scale (uint32_t a, int32_t b, int mode, int *flags)
 
static uint64_t fp64_scale (uint64_t a, int64_t b, int mode, int *flags)
 
static uint16_t fp16_sqrt (uint16_t a, int mode, int *flags)
 
static uint32_t fp32_sqrt (uint32_t a, int mode, int *flags)
 
static uint64_t fp64_sqrt (uint64_t a, int mode, int *flags)
 
static int modeConv (FPSCR fpscr)
 
static void set_fpscr (FPSCR &fpscr, int flags)
 
template<>
bool fplibCompareEQ (uint16_t a, uint16_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGE (uint16_t a, uint16_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGT (uint16_t a, uint16_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareUN (uint16_t a, uint16_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareEQ (uint32_t a, uint32_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGE (uint32_t a, uint32_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGT (uint32_t a, uint32_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareUN (uint32_t a, uint32_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareEQ (uint64_t a, uint64_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGE (uint64_t a, uint64_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGT (uint64_t a, uint64_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareUN (uint64_t a, uint64_t b, FPSCR &fpscr)
 
template<>
uint16_t fplibAbs (uint16_t op)
 
template<>
uint32_t fplibAbs (uint32_t op)
 
template<>
uint64_t fplibAbs (uint64_t op)
 
template<>
uint16_t fplibAdd (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibAdd (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibAdd (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
int fplibCompare (uint16_t op1, uint16_t op2, bool signal_nans, FPSCR &fpscr)
 
template<>
int fplibCompare (uint32_t op1, uint32_t op2, bool signal_nans, FPSCR &fpscr)
 
template<>
int fplibCompare (uint64_t op1, uint64_t op2, bool signal_nans, FPSCR &fpscr)
 
static uint16_t fp16_FPConvertNaN_32 (uint32_t op)
 
static uint16_t fp16_FPConvertNaN_64 (uint64_t op)
 
static uint32_t fp32_FPConvertNaN_16 (uint16_t op)
 
static uint32_t fp32_FPConvertNaN_64 (uint64_t op)
 
static uint64_t fp64_FPConvertNaN_16 (uint16_t op)
 
static uint64_t fp64_FPConvertNaN_32 (uint32_t op)
 
static uint16_t fp16_FPOnePointFive (int sgn)
 
static uint32_t fp32_FPOnePointFive (int sgn)
 
static uint64_t fp64_FPOnePointFive (int sgn)
 
static uint16_t fp16_FPThree (int sgn)
 
static uint32_t fp32_FPThree (int sgn)
 
static uint64_t fp64_FPThree (int sgn)
 
static uint16_t fp16_FPTwo (int sgn)
 
static uint32_t fp32_FPTwo (int sgn)
 
static uint64_t fp64_FPTwo (int sgn)
 
template<>
uint16_t fplibConvert (uint32_t op, FPRounding rounding, FPSCR &fpscr)
 
template<>
uint16_t fplibConvert (uint64_t op, FPRounding rounding, FPSCR &fpscr)
 
template<>
uint32_t fplibConvert (uint16_t op, FPRounding rounding, FPSCR &fpscr)
 
template<>
uint16_t fplibMulAdd (uint16_t addend, uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMulAdd (uint32_t addend, uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMulAdd (uint64_t addend, uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibDiv (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibDiv (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibDiv (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibExpA (uint16_t op)
 
template<>
uint32_t fplibExpA (uint32_t op)
 
template<>
uint64_t fplibExpA (uint64_t op)
 
static uint16_t fp16_repack (int sgn, int exp, uint16_t mnt)
 
static uint32_t fp32_repack (int sgn, int exp, uint32_t mnt)
 
static uint64_t fp64_repack (int sgn, int exp, uint64_t mnt)
 
static void fp16_minmaxnum (uint16_t *op1, uint16_t *op2, int sgn)
 
static void fp32_minmaxnum (uint32_t *op1, uint32_t *op2, int sgn)
 
static void fp64_minmaxnum (uint64_t *op1, uint64_t *op2, int sgn)
 
template<>
uint16_t fplibMax (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMax (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMax (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibMaxNum (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMaxNum (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMaxNum (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibMin (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMin (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMin (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibMinNum (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMinNum (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMinNum (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibMul (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMul (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMul (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibMulX (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMulX (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMulX (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibNeg (uint16_t op)
 
template<>
uint32_t fplibNeg (uint32_t op)
 
template<>
uint64_t fplibNeg (uint64_t op)
 
template<>
uint16_t fplibRSqrtEstimate (uint16_t op, FPSCR &fpscr)
 
template<>
uint32_t fplibRSqrtEstimate (uint32_t op, FPSCR &fpscr)
 
template<>
uint64_t fplibRSqrtEstimate (uint64_t op, FPSCR &fpscr)
 
template<>
uint16_t fplibRSqrtStepFused (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibRSqrtStepFused (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibRSqrtStepFused (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibRecipEstimate (uint16_t op, FPSCR &fpscr)
 
template<>
uint32_t fplibRecipEstimate (uint32_t op, FPSCR &fpscr)
 
template<>
uint64_t fplibRecipEstimate (uint64_t op, FPSCR &fpscr)
 
template<>
uint16_t fplibRecipStepFused (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibRecipStepFused (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibRecipStepFused (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibRecpX (uint16_t op, FPSCR &fpscr)
 
template<>
uint32_t fplibRecpX (uint32_t op, FPSCR &fpscr)
 
template<>
uint64_t fplibRecpX (uint64_t op, FPSCR &fpscr)
 
template<>
uint16_t fplibRoundInt (uint16_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
 
template<>
uint32_t fplibRoundInt (uint32_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
 
template<>
uint64_t fplibRoundInt (uint64_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
 
template<>
uint16_t fplibScale (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibScale (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibScale (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibSqrt (uint16_t op, FPSCR &fpscr)
 
template<>
uint32_t fplibSqrt (uint32_t op, FPSCR &fpscr)
 
template<>
uint64_t fplibSqrt (uint64_t op, FPSCR &fpscr)
 
template<>
uint16_t fplibSub (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibSub (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibSub (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibTrigMulAdd (uint8_t coeff_index, uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibTrigMulAdd (uint8_t coeff_index, uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibTrigMulAdd (uint8_t coeff_index, uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibTrigSMul (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibTrigSMul (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibTrigSMul (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibTrigSSel (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibTrigSSel (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibTrigSSel (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
static uint64_t FPToFixed_64 (int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int *flags)
 
static uint32_t FPToFixed_32 (int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int *flags)
 
static uint16_t FPToFixed_16 (int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int *flags)
 
template<>
uint16_t fplibFPToFixed (uint16_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
 
template<>
uint32_t fplibFPToFixed (uint32_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
 
template<>
uint32_t fplibFPToFixed (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
 
uint32_t fplibFPToFixedJS (uint64_t op, FPSCR &fpscr, bool Is64, uint8_t &nz)
 Floating-point JS convert to a signed integer, with rounding to zero. More...
 
static uint16_t fp16_cvtf (uint64_t a, int fbits, int u, int mode, int *flags)
 
static uint32_t fp32_cvtf (uint64_t a, int fbits, int u, int mode, int *flags)
 
static uint64_t fp64_cvtf (uint64_t a, int fbits, int u, int mode, int *flags)
 
template<>
uint16_t fplibFixedToFP (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
 Floating-point convert from fixed-point. More...
 
template<>
uint16_t fplibInfinity (int sgn)
 Floating-point value for +/- infinity. More...
 
template<>
uint16_t fplibDefaultNaN ()
 Foating-point value for default NaN. More...
 
static FPRounding FPCRRounding (FPSCR &fpscr)
 
template<class T >
fplibAbs (T op)
 Floating-point absolute value. More...
 
template<class T >
fplibAdd (T op1, T op2, FPSCR &fpscr)
 Floating-point add. More...
 
template<class T >
int fplibCompare (T op1, T op2, bool signal_nans, FPSCR &fpscr)
 Floating-point compare (quiet and signaling). More...
 
template<class T >
bool fplibCompareEQ (T op1, T op2, FPSCR &fpscr)
 Floating-point compare equal. More...
 
template<class T >
bool fplibCompareGE (T op1, T op2, FPSCR &fpscr)
 Floating-point compare greater than or equal. More...
 
template<class T >
bool fplibCompareGT (T op1, T op2, FPSCR &fpscr)
 Floating-point compare greater than. More...
 
template<class T >
bool fplibCompareUN (T op1, T op2, FPSCR &fpscr)
 Floating-point compare unordered. More...
 
template<class T1 , class T2 >
T2 fplibConvert (T1 op, FPRounding rounding, FPSCR &fpscr)
 Floating-point convert precision. More...
 
template<class T >
fplibDiv (T op1, T op2, FPSCR &fpscr)
 Floating-point division. More...
 
template<class T >
fplibExpA (T op)
 Floating-point exponential accelerator. More...
 
template<class T >
fplibMax (T op1, T op2, FPSCR &fpscr)
 Floating-point maximum. More...
 
template<class T >
fplibMaxNum (T op1, T op2, FPSCR &fpscr)
 Floating-point maximum number. More...
 
template<class T >
fplibMin (T op1, T op2, FPSCR &fpscr)
 Floating-point minimum. More...
 
template<class T >
fplibMinNum (T op1, T op2, FPSCR &fpscr)
 Floating-point minimum number. More...
 
template<class T >
fplibMul (T op1, T op2, FPSCR &fpscr)
 Floating-point multiply. More...
 
template<class T >
fplibMulAdd (T addend, T op1, T op2, FPSCR &fpscr)
 Floating-point multiply-add. More...
 
template<class T >
fplibMulX (T op1, T op2, FPSCR &fpscr)
 Floating-point multiply extended. More...
 
template<class T >
fplibNeg (T op)
 Floating-point negate. More...
 
template<class T >
fplibRSqrtEstimate (T op, FPSCR &fpscr)
 Floating-point reciprocal square root estimate. More...
 
template<class T >
fplibRSqrtStepFused (T op1, T op2, FPSCR &fpscr)
 Floating-point reciprocal square root step. More...
 
template<class T >
fplibRecipEstimate (T op, FPSCR &fpscr)
 Floating-point reciprocal estimate. More...
 
template<class T >
fplibRecipStepFused (T op1, T op2, FPSCR &fpscr)
 Floating-point reciprocal step. More...
 
template<class T >
fplibRecpX (T op, FPSCR &fpscr)
 Floating-point reciprocal exponent. More...
 
template<class T >
fplibRoundInt (T op, FPRounding rounding, bool exact, FPSCR &fpscr)
 Floating-point convert to integer. More...
 
template<class T >
fplibScale (T op1, T op2, FPSCR &fpscr)
 Floating-point adjust exponent. More...
 
template<class T >
fplibSqrt (T op, FPSCR &fpscr)
 Floating-point square root. More...
 
template<class T >
fplibSub (T op1, T op2, FPSCR &fpscr)
 Floating-point subtract. More...
 
template<class T >
fplibTrigMulAdd (uint8_t coeff_index, T op1, T op2, FPSCR &fpscr)
 Floating-point trigonometric multiply-add coefficient. More...
 
template<class T >
fplibTrigSMul (T op1, T op2, FPSCR &fpscr)
 Floating-point trigonometric starting value. More...
 
template<class T >
fplibTrigSSel (T op1, T op2, FPSCR &fpscr)
 Floating-point trigonometric select coefficient. More...
 
template<class T1 , class T2 >
T2 fplibFPToFixed (T1 op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
 Floating-point convert to fixed-point. More...
 
static unsigned int number_of_ones (int32_t val)
 
void writeVecElem (VReg *dest, XReg src, int index, int eSize)
 Write a single NEON vector element leaving the others untouched. More...
 
XReg readVecElem (VReg src, int index, int eSize)
 Read a single NEON vector element. More...
 
static uint32_t rotate_imm (uint32_t immValue, uint32_t rotateValue)
 
static uint32_t modified_imm (uint8_t ctrlImm, uint8_t dataImm)
 
static uint64_t simd_modified_imm (bool op, uint8_t cmode, uint8_t data, bool &immValid, bool isAarch64=false)
 
static uint64_t vfp_modified_imm (uint8_t data, FpDataType dtype)
 
static FpDataType decode_fp_data_type (uint8_t encoding)
 
static uint8_t getRestoredITBits (ThreadContext *tc, CPSR spsr)
 
static bool illegalExceptionReturn (ThreadContext *tc, CPSR cpsr, CPSR spsr)
 
const char * svePredTypeToStr (SvePredType pt)
 Returns the specifier for the predication type pt as a string. More...
 
std::string sveDisasmPredCountImm (uint8_t imm)
 Returns the symbolic name associated with pattern imm for PTRUE(S) instructions. More...
 
unsigned int sveDecodePredCount (uint8_t imm, unsigned int num_elems)
 Returns the actual number of elements active for PTRUE(S) instructions. More...
 
uint64_t sveExpandFpImmAddSub (uint8_t imm, uint8_t size)
 Expand 1-bit floating-point immediate to 0.5 or 1.0 (FADD, FSUB, FSUBR). More...
 
uint64_t sveExpandFpImmMaxMin (uint8_t imm, uint8_t size)
 Expand 1-bit floating-point immediate to 0.0 or 1.0 (FMAX, FMAXNM, FMIN, FMINNM). More...
 
uint64_t sveExpandFpImmMul (uint8_t imm, uint8_t size)
 Expand 1-bit floating-point immediate to 0.5 or 2.0 (FMUL). More...
 
VfpSavedState prepFpState (uint32_t rMode)
 
void finishVfp (FPSCR &fpscr, VfpSavedState state, bool flush, FPSCR mask)
 
template<class fpType >
fpType fixDest (bool flush, bool defaultNan, fpType val, fpType op1)
 
template float fixDest< float > (bool flush, bool defaultNan, float val, float op1)
 
template double fixDest< double > (bool flush, bool defaultNan, double val, double op1)
 
template<class fpType >
fpType fixDest (bool flush, bool defaultNan, fpType val, fpType op1, fpType op2)
 
template float fixDest< float > (bool flush, bool defaultNan, float val, float op1, float op2)
 
template double fixDest< double > (bool flush, bool defaultNan, double val, double op1, double op2)
 
template<class fpType >
fpType fixDivDest (bool flush, bool defaultNan, fpType val, fpType op1, fpType op2)
 
template float fixDivDest< float > (bool flush, bool defaultNan, float val, float op1, float op2)
 
template double fixDivDest< double > (bool flush, bool defaultNan, double val, double op1, double op2)
 
float fixFpDFpSDest (FPSCR fpscr, double val)
 
double fixFpSFpDDest (FPSCR fpscr, float val)
 
static uint16_t vcvtFpFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, uint64_t opBits, bool isDouble)
 
uint16_t vcvtFpSFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, float op)
 
uint16_t vcvtFpDFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, double op)
 
static uint64_t vcvtFpHFp (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op, bool isDouble)
 
double vcvtFpHFpD (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
 
float vcvtFpHFpS (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
 
float vfpUFixedToFpS (bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
 
float vfpSFixedToFpS (bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
 
double vfpUFixedToFpD (bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
 
double vfpSFixedToFpD (bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
 
static double recipSqrtEstimate (double a)
 
float fprSqrtEstimate (FPSCR &fpscr, float op)
 
uint32_t unsignedRSqrtEstimate (uint32_t op)
 
static double recipEstimate (double a)
 
float fpRecipEstimate (FPSCR &fpscr, float op)
 
uint32_t unsignedRecipEstimate (uint32_t op)
 
FPSCR fpStandardFPSCRValue (const FPSCR &fpscr)
 
template<class T >
static void setVfpMicroFlags (VfpMicroMode mode, T &flags)
 
static float bitsToFp (uint64_t, float)
 
static double bitsToFp (uint64_t, double)
 
static uint32_t fpToBits (float)
 
static uint64_t fpToBits (double)
 
template<class fpType >
static bool flushToZero (fpType &op)
 
template<class fpType >
static bool flushToZero (fpType &op1, fpType &op2)
 
template<class fpType >
static void vfpFlushToZero (FPSCR &fpscr, fpType &op)
 
template<class fpType >
static void vfpFlushToZero (FPSCR &fpscr, fpType &op1, fpType &op2)
 
template<class fpType >
static bool isSnan (fpType val)
 
template<class fpType >
fpType fixDest (FPSCR fpscr, fpType val, fpType op1)
 
template<class fpType >
fpType fixDest (FPSCR fpscr, fpType val, fpType op1, fpType op2)
 
template<class fpType >
fpType fixDivDest (FPSCR fpscr, fpType val, fpType op1, fpType op2)
 
static double makeDouble (uint32_t low, uint32_t high)
 
static uint32_t lowFromDouble (double val)
 
static uint32_t highFromDouble (double val)
 
static void setFPExceptions (int exceptions)
 
template<typename T >
uint64_t vfpFpToFixed (T val, bool isSigned, uint8_t width, uint8_t imm, bool useRmode=true, VfpRoundingMode roundMode=VfpRoundZero, bool aarch64=false)
 
template<typename T >
static T fpAdd (T a, T b)
 
template<typename T >
static T fpSub (T a, T b)
 
static float fpAddS (float a, float b)
 
static double fpAddD (double a, double b)
 
static float fpSubS (float a, float b)
 
static double fpSubD (double a, double b)
 
static float fpDivS (float a, float b)
 
static double fpDivD (double a, double b)
 
template<typename T >
static T fpDiv (T a, T b)
 
template<typename T >
static T fpMulX (T a, T b)
 
template<typename T >
static T fpMul (T a, T b)
 
static float fpMulS (float a, float b)
 
static double fpMulD (double a, double b)
 
template<typename T >
static T fpMulAdd (T op1, T op2, T addend)
 
template<typename T >
static T fpRIntX (T a, FPSCR &fpscr)
 
template<typename T >
static T fpMaxNum (T a, T b)
 
template<typename T >
static T fpMax (T a, T b)
 
template<typename T >
static T fpMinNum (T a, T b)
 
template<typename T >
static T fpMin (T a, T b)
 
template<typename T >
static T fpRSqrts (T a, T b)
 
template<typename T >
static T fpRecps (T a, T b)
 
static float fpRSqrtsS (float a, float b)
 
static float fpRecpsS (float a, float b)
 
template<typename T >
static T roundNEven (T a)
 
static IntRegIndex INTREG_USR (unsigned index)
 
static IntRegIndex INTREG_HYP (unsigned index)
 
static IntRegIndex INTREG_SVC (unsigned index)
 
static IntRegIndex INTREG_MON (unsigned index)
 
static IntRegIndex INTREG_ABT (unsigned index)
 
static IntRegIndex INTREG_UND (unsigned index)
 
static IntRegIndex INTREG_IRQ (unsigned index)
 
static IntRegIndex INTREG_FIQ (unsigned index)
 
static int intRegInMode (OperatingMode mode, int reg)
 
static int flattenIntRegModeIndex (int reg)
 
static IntRegIndex makeSP (IntRegIndex reg)
 
static IntRegIndex makeZero (IntRegIndex reg)
 
static bool isSP (IntRegIndex reg)
 
template<class XC >
void handleLockedSnoop (XC *xc, PacketPtr pkt, Addr cacheBlockMask)
 
template<class XC >
void handleLockedRead (XC *xc, const RequestPtr &req)
 
template<class XC >
void handleLockedSnoopHit (XC *xc)
 
template<class XC >
bool handleLockedWrite (XC *xc, const RequestPtr &req, Addr cacheBlockMask)
 
template<class XC >
void globalClearExclusive (XC *xc)
 
MiscRegIndex decodeCP14Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
 
MiscRegIndex decodeCP15Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
 
MiscRegIndex decodeCP15Reg64 (unsigned crm, unsigned opc1)
 
std::tuple< bool, bool > canReadCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
 Check for permission to read coprocessor registers. More...
 
std::tuple< bool, bool > canWriteCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
 Check for permission to write coprocessor registers. More...
 
bool AArch32isUndefinedGenericTimer (MiscRegIndex reg, ThreadContext *tc)
 
int snsBankedIndex (MiscRegIndex reg, ThreadContext *tc)
 
int snsBankedIndex (MiscRegIndex reg, ThreadContext *tc, bool ns)
 
int snsBankedIndex64 (MiscRegIndex reg, ThreadContext *tc)
 
void preUnflattenMiscReg ()
 
int unflattenMiscReg (int reg)
 
bool canReadAArch64SysReg (MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, ThreadContext *tc)
 
bool canWriteAArch64SysReg (MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, ThreadContext *tc)
 
MiscRegIndex decodeAArch64SysReg (unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
 
bool aarch64SysRegReadOnly (MiscRegIndex miscReg)
 
 BitUnion32 (CPSR) Bitfield< 31
 
 EndBitUnion (CPSR) BitUnion64(AA64DFR0) Bitfield< 43
 
 EndBitUnion (AA64DFR0) BitUnion64(AA64ISAR0) Bitfield< 63
 
 EndBitUnion (AA64ISAR0) BitUnion64(AA64ISAR1) Bitfield< 43
 
 EndBitUnion (AA64ISAR1) BitUnion64(AA64MMFR0) Bitfield< 63
 
 EndBitUnion (AA64MMFR0) BitUnion64(AA64MMFR1) Bitfield< 31
 
 EndBitUnion (AA64MMFR1) BitUnion64(AA64MMFR2) Bitfield< 63
 
 EndBitUnion (AA64MMFR2) BitUnion64(AA64PFR0) Bitfield< 63
 
 EndBitUnion (AA64PFR0) BitUnion32(HDCR) Bitfield< 11 > tdra
 
 EndBitUnion (HDCR) BitUnion32(HCPTR) Bitfield< 31 > tcpac
 
 EndBitUnion (HCPTR) BitUnion32(HSTR) Bitfield< 17 > tjdbx
 
 EndBitUnion (HSTR) BitUnion64(HCR) Bitfield< 47 > fien
 
 EndBitUnion (HCR) BitUnion32(NSACR) Bitfield< 20 > nstrcdis
 
 EndBitUnion (NSACR) BitUnion32(SCR) Bitfield< 21 > fien
 
 EndBitUnion (SCR) BitUnion32(SCTLR) Bitfield< 31 > enia
 
 EndBitUnion (SCTLR) BitUnion32(CPACR) Bitfield< 1
 
 EndBitUnion (CPACR) BitUnion32(FSR) Bitfield< 3
 
 EndBitUnion (FSR) BitUnion32(FPSCR) Bitfield< 0 > ioc
 
 EndBitUnion (FPSCR) BitUnion32(FPEXC) Bitfield< 31 > ex
 
 EndBitUnion (FPEXC) BitUnion32(MVFR0) Bitfield< 3
 
 EndBitUnion (MVFR0) BitUnion32(MVFR1) Bitfield< 3
 
 EndBitUnion (MVFR1) BitUnion64(TTBCR) Bitfield< 2
 
 EndBitUnion (TTBCR) BitUnion64(TCR) Bitfield< 5
 
 EndBitUnion (TCR) BitUnion32(HTCR) Bitfield< 2
 
 EndBitUnion (HTCR) BitUnion32(VTCR_t) Bitfield< 3
 
 EndBitUnion (VTCR_t) BitUnion32(PRRR) Bitfield< 1
 
 EndBitUnion (PRRR) BitUnion32(NMRR) Bitfield< 1
 
 EndBitUnion (NMRR) BitUnion32(CONTEXTIDR) Bitfield< 7
 
 EndBitUnion (CONTEXTIDR) BitUnion32(L2CTLR) Bitfield< 2
 
 EndBitUnion (L2CTLR) BitUnion32(CTR) Bitfield< 3
 
 EndBitUnion (CTR) BitUnion32(PMSELR) Bitfield< 4
 
 EndBitUnion (PMSELR) BitUnion64(PAR) Bitfield< 63
 
 EndBitUnion (PAR) BitUnion32(ESR) Bitfield< 31
 
 EndBitUnion (ESR) BitUnion32(CPTR) Bitfield< 31 > tcpac
 
 EndBitUnion (CPTR) BitUnion64(ZCR) Bitfield< 3
 
 EndBitUnion (ZCR) BitUnion32(OSL) Bitfield< 64
 
 EndBitUnion (OSL) BitUnion64(DBGBCR) Bitfield< 63
 
 EndBitUnion (DBGBCR) BitUnion64(DBGWCR) Bitfield< 63
 
 EndBitUnion (DBGWCR) BitUnion32(DBGDS32) Bitfield< 31 > tfo
 
 EndBitUnion (DBGDS32) BitUnion32(DBGVCR) Bitfield< 31 > nsf
 
 EndBitUnion (DBGVCR) BitUnion32(DEVID) Bitfield< 31
 
bool upperAndLowerRange (ThreadContext *tc, ExceptionLevel el)
 
bool calculateTBI (ThreadContext *tc, ExceptionLevel el, uint64_t ptr, bool data)
 
int calculateBottomPACBit (ThreadContext *tc, ExceptionLevel el, bool top_bit)
 
Fault trapPACUse (ThreadContext *tc, ExceptionLevel el)
 
uint64_t addPAC (ThreadContext *tc, ExceptionLevel el, uint64_t ptr, uint64_t modifier, uint64_t k1, uint64_t k0, bool data)
 
uint64_t auth (ThreadContext *tc, ExceptionLevel el, uint64_t ptr, uint64_t modifier, uint64_t k1, uint64_t K0, bool data, uint8_t errorcode)
 
Fault authDA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault authDB (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault authIA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault authIB (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault addPACDA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault addPACDB (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault addPACGA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault addPACIA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault addPACIB (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault stripPAC (ThreadContext *tc, uint64_t A, bool data, uint64_t *out)
 
template<typename T >
TLBgetITBPtr (T *tc)
 
template<typename T >
TLBgetDTBPtr (T *tc)
 
 BitUnion8 (ITSTATE) Bitfield< 7
 
 EndBitUnion (ITSTATE) BitUnion64(ExtMachInst) Bitfield< 63
 
 SubBitUnion (puswl, 24, 20) Bitfield< 24 > prepost
 
 EndSubBitUnion (puswl) Bitfield< 24
 
 BitUnion8 (OperatingMode64) Bitfield< 0 > spX
 
 EndBitUnion (OperatingMode64) static bool inline opModeIs64(OperatingMode mode)
 
static bool opModeIsH (OperatingMode mode)
 
static bool opModeIsT (OperatingMode mode)
 
static ExceptionLevel opModeToEL (OperatingMode mode)
 
static bool unknownMode (OperatingMode mode)
 
static bool unknownMode32 (OperatingMode mode)
 
uint64_t getArgument (ThreadContext *tc, int &number, uint16_t size, bool fp)
 
static void copyVecRegs (ThreadContext *src, ThreadContext *dest)
 
void copyRegs (ThreadContext *src, ThreadContext *dest)
 
void sendEvent (ThreadContext *tc)
 Send an event (SEV) to a specific PE if there isn't already a pending event. More...
 
bool isSecure (ThreadContext *tc)
 
bool isSecureBelowEL3 (ThreadContext *tc)
 
ExceptionLevel debugTargetFrom (ThreadContext *tc, bool secure)
 
bool inAArch64 (ThreadContext *tc)
 
bool longDescFormatInUse (ThreadContext *tc)
 
RegVal readMPIDR (ArmSystem *arm_sys, ThreadContext *tc)
 This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR), or it is issuing a read to VMPIDR_EL2 (as it happens in virtualized systems) More...
 
RegVal getMPIDR (ArmSystem *arm_sys, ThreadContext *tc)
 This helper function is returning the value of MPIDR_EL1. More...
 
static RegVal getAff2 (ArmSystem *arm_sys, ThreadContext *tc)
 
static RegVal getAff1 (ArmSystem *arm_sys, ThreadContext *tc)
 
static RegVal getAff0 (ArmSystem *arm_sys, ThreadContext *tc)
 
RegVal getAffinity (ArmSystem *arm_sys, ThreadContext *tc)
 Retrieves MPIDR_EL1. More...
 
bool HavePACExt (ThreadContext *tc)
 
bool HaveVirtHostExt (ThreadContext *tc)
 
ExceptionLevel s1TranslationRegime (ThreadContext *tc, ExceptionLevel el)
 
bool HaveSecureEL2Ext (ThreadContext *tc)
 
bool IsSecureEL2Enabled (ThreadContext *tc)
 
bool EL2Enabled (ThreadContext *tc)
 
bool ELIs64 (ThreadContext *tc, ExceptionLevel el)
 
bool ELIs32 (ThreadContext *tc, ExceptionLevel el)
 
bool ELIsInHost (ThreadContext *tc, ExceptionLevel el)
 Returns true if the current exception level el is executing a Host OS or an application of a Host OS (Armv8.1 Virtualization Host Extensions). More...
 
std::pair< bool, bool > ELUsingAArch32K (ThreadContext *tc, ExceptionLevel el)
 This function checks whether selected EL provided as an argument is using the AArch32 ISA. More...
 
bool haveAArch32EL (ThreadContext *tc, ExceptionLevel el)
 
std::pair< bool, bool > ELStateUsingAArch32K (ThreadContext *tc, ExceptionLevel el, bool secure)
 
bool ELStateUsingAArch32 (ThreadContext *tc, ExceptionLevel el, bool secure)
 
bool isBigEndian64 (const ThreadContext *tc)
 
bool badMode32 (ThreadContext *tc, OperatingMode mode)
 badMode is checking if the execution mode provided as an argument is valid and implemented for AArch32 More...
 
bool badMode (ThreadContext *tc, OperatingMode mode)
 badMode is checking if the execution mode provided as an argument is valid and implemented. More...
 
int computeAddrTop (ThreadContext *tc, bool selbit, bool isInstr, TCR tcr, ExceptionLevel el)
 
Addr purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool isInstr)
 Removes the tag from tagged addresses if that mode is enabled. More...
 
Addr purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, bool isInstr)
 
Addr truncPage (Addr addr)
 
Addr roundPage (Addr addr)
 
Fault mcrMrc15Trap (const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm)
 
bool mcrMrc15TrapToHyp (const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
 
bool mcrMrc14TrapToHyp (const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
 
Fault mcrrMrrc15Trap (const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm)
 
bool mcrrMrrc15TrapToHyp (const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
 
Fault AArch64AArch32SystemAccessTrap (const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm, ExceptionClass ec)
 
bool isAArch64AArch32SystemAccessTrapEL1 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isGenericTimerHypTrap (const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
 
bool isGenericTimerCommonEL0HypTrap (const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
 
bool isGenericTimerPhysHypTrap (const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
 
bool condGenericTimerPhysHypTrap (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isGenericTimerSystemAccessTrapEL1 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool condGenericTimerSystemAccessTrapEL1 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isAArch64AArch32SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isGenericTimerSystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isGenericTimerCommonEL0SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isGenericTimerPhysEL0SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isGenericTimerPhysEL1SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isGenericTimerVirtSystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool condGenericTimerCommonEL0SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool condGenericTimerCommonEL1SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool condGenericTimerPhysEL1SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isGenericTimerSystemAccessTrapEL3 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool decodeMrsMsrBankedReg (uint8_t sysM, bool r, bool &isIntReg, int &regIdx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
 
bool isUnpriviledgeAccess (ThreadContext *tc)
 
bool SPAlignmentCheckEnabled (ThreadContext *tc)
 
int decodePhysAddrRange64 (uint8_t pa_enc)
 Returns the n. More...
 
uint8_t encodePhysAddrRange64 (int pa_size)
 Returns the encoding corresponding to the specified n. More...
 
PCState buildRetPC (const PCState &curPC, const PCState &callPC)
 
bool testPredicate (uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
 
static void copyMiscRegs (ThreadContext *src, ThreadContext *dest)
 
static bool inUserMode (CPSR cpsr)
 
static bool inUserMode (ThreadContext *tc)
 
static bool inPrivilegedMode (CPSR cpsr)
 
static bool inPrivilegedMode (ThreadContext *tc)
 
static OperatingMode currOpMode (const ThreadContext *tc)
 
static ExceptionLevel currEL (const ThreadContext *tc)
 
ExceptionLevel currEL (CPSR cpsr)
 
static uint8_t itState (CPSR psr)
 
static bool inSecureState (SCR scr, CPSR cpsr)
 
static uint32_t mcrMrcIssBuild (bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn, uint32_t opc1, uint32_t opc2)
 
static void mcrMrcIssExtract (uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt, uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
 
static uint32_t mcrrMrrcIssBuild (bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2, uint32_t opc1)
 
static uint32_t msrMrs64IssBuild (bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, IntRegIndex rt)
 
void advancePC (PCState &pc, const StaticInstPtr &inst)
 
uint64_t getExecutingAsid (ThreadContext *tc)
 
static int decodeMrsMsrBankedIntRegIndex (uint8_t sysM, bool r)
 
ByteOrder byteOrder (const ThreadContext *tc)
 
 BitUnion64 (CNTKCTL) Bitfield< 17 > evntis
 
 EndBitUnion (CNTKCTL) BitUnion64(CNTHCTL) Bitfield< 17 > evntis
 
 EndBitUnion (CNTHCTL) BitUnion64(CNTHCTL_E2H) Bitfield< 17 > evntis
 

Variables

const char *const ccRegName [NUM_CCREGS]
 
const uint32_t HighVecs = 0xFFFF0000
 
static const uint8_t recip_sqrt_estimate [256]
 
const IntRegMap IntReg64Map
 
const IntRegMap IntRegUsrMap
 
const IntRegMap IntRegHypMap
 
const IntRegMap IntRegSvcMap
 
const IntRegMap IntRegMonMap
 
const IntRegMap IntRegAbtMap
 
const IntRegMap IntRegUndMap
 
const IntRegMap IntRegIrqMap
 
const IntRegMap IntRegFiqMap
 
static const unsigned intRegsPerMode = NUM_INTREGS
 
const ByteOrder GuestByteOrder = ByteOrder::little
 
const Addr PageShift = 12
 
const Addr PageBytes = ULL(1) << PageShift
 
int unflattenResultMiscReg [NUM_MISCREGS]
 If the reg is a child reg of a banked set, then the parent is the last banked one in the list. More...
 
bitset< NUM_MISCREG_INFOSmiscRegInfo [NUM_MISCREGS]
 
const char *const miscRegName []
 
static const uint32_t CondCodesMask = 0xF00F0000
 
static const uint32_t CpsrMaskQ = 0x08000000
 
static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0
 
static const uint32_t CpsrMask = ApsrMask | 0x00F003DF
 
static const uint32_t FpCondCodesMask = 0xF0000000
 
static const uint32_t FpscrQcMask = 0x08000000
 
static const uint32_t FpscrAhpMask = 0x04000000
 
static const uint32_t FpscrExcMask = 0x0000009F
 
 nz
 
Bitfield< 29 > c
 
Bitfield< 28 > v
 
Bitfield< 27 > q
 
Bitfield< 26, 25 > it1
 
Bitfield< 24 > j
 
Bitfield< 22 > pan
 
Bitfield< 21 > ss
 
Bitfield< 20 > il
 
Bitfield< 19, 16 > ge
 
Bitfield< 15, 10 > it2
 
Bitfield< 9 > d
 
Bitfield< 9 > e
 
Bitfield< 8 > a
 
Bitfield< 7 > i
 
Bitfield< 6 > f
 
Bitfield< 8, 6 > aif
 
Bitfield< 9, 6 > daif
 
Bitfield< 5 > t
 
Bitfield< 4 > width
 
Bitfield< 3, 2 > el
 
Bitfield< 4, 0 > mode
 
Bitfield< 0 > sp
 
 tracefilt
 
Bitfield< 39, 36 > doublelock
 
Bitfield< 35, 32 > pmsver
 
Bitfield< 31, 28 > ctx_cmps
 
Bitfield< 23, 20 > wrps
 
Bitfield< 15, 12 > brps
 
Bitfield< 11, 8 > pmuver
 
Bitfield< 7, 4 > tracever
 
Bitfield< 3, 0 > debugver
 
 rndr
 
Bitfield< 59, 56 > tlb
 
Bitfield< 55, 52 > ts
 
Bitfield< 51, 48 > fhm
 
Bitfield< 47, 44 > dp
 
Bitfield< 43, 40 > sm4
 
Bitfield< 39, 36 > sm3
 
Bitfield< 35, 32 > sha3
 
Bitfield< 31, 28 > rdm
 
Bitfield< 23, 20 > atomic
 
Bitfield< 19, 16 > crc32
 
Bitfield< 15, 12 > sha2
 
Bitfield< 11, 8 > sha1
 
Bitfield< 3, 0 > aes
 
 specres
 
Bitfield< 39, 36 > sb
 
Bitfield< 35, 32 > frintts
 
Bitfield< 31, 28 > gpi
 
Bitfield< 27, 24 > gpa
 
Bitfield< 23, 20 > lrcpc
 
Bitfield< 19, 16 > fcma
 
Bitfield< 15, 12 > jscvt
 
Bitfield< 11, 8 > api
 
Bitfield< 7, 4 > apa
 
Bitfield< 3, 0 > dpb
 
 ecv
 
Bitfield< 47, 44 > exs
 
Bitfield< 43, 40 > tgran4_2
 
Bitfield< 39, 36 > tgran64_2
 
Bitfield< 35, 32 > tgran16_2
 
Bitfield< 31, 28 > tgran4
 
Bitfield< 27, 24 > tgran64
 
Bitfield< 23, 20 > tgran16
 
Bitfield< 19, 16 > bigendEL0
 
Bitfield< 15, 12 > snsmem
 
Bitfield< 11, 8 > bigend
 
Bitfield< 7, 4 > asidbits
 
Bitfield< 3, 0 > parange
 
 xnx
 
Bitfield< 27, 24 > specsei
 
Bitfield< 19, 16 > lo
 
Bitfield< 15, 12 > hpds
 
Bitfield< 11, 8 > vh
 
Bitfield< 7, 4 > vmidbits
 
Bitfield< 3, 0 > hafdbs
 
 e0pd
 
Bitfield< 59, 56 > evt
 
Bitfield< 55, 52 > bbm
 
Bitfield< 51, 48 > ttl
 
Bitfield< 43, 40 > fwb
 
Bitfield< 39, 36 > ids
 
Bitfield< 35, 32 > at
 
Bitfield< 31, 28 > st
 
Bitfield< 27, 24 > nv
 
Bitfield< 23, 20 > ccidx
 
Bitfield< 19, 16 > varange
 
Bitfield< 15, 12 > iesb
 
Bitfield< 11, 8 > lsm
 
Bitfield< 7, 4 > uao
 
Bitfield< 3, 0 > cnp
 
 csv3
 
Bitfield< 59, 56 > csv2
 
Bitfield< 51, 48 > dit
 
Bitfield< 47, 44 > amu
 
Bitfield< 43, 40 > mpam
 
Bitfield< 39, 36 > sel2
 
Bitfield< 35, 32 > sve
 
Bitfield< 31, 28 > ras
 
Bitfield< 27, 24 > gic
 
Bitfield< 23, 20 > advsimd
 
Bitfield< 19, 16 > fp
 
Bitfield< 15, 12 > el3
 
Bitfield< 11, 8 > el2
 
Bitfield< 7, 4 > el1
 
Bitfield< 3, 0 > el0
 
Bitfield< 10 > tdosa
 
Bitfield< 9 > tda
 
Bitfield< 8 > tde
 
Bitfield< 7 > hpme
 
Bitfield< 6 > tpm
 
Bitfield< 5 > tpmcr
 
Bitfield< 4, 0 > hpmn
 
Bitfield< 20 > tta
 
Bitfield< 15 > tase
 
Bitfield< 13 > tcp13
 
Bitfield< 12 > tcp12
 
Bitfield< 11 > tcp11
 
Bitfield< 10 > tcp10
 
Bitfield< 10 > tfp
 
Bitfield< 9 > tcp9
 
Bitfield< 8 > tcp8
 
Bitfield< 8 > tz
 
Bitfield< 7 > tcp7
 
Bitfield< 6 > tcp6
 
Bitfield< 5 > tcp5
 
Bitfield< 4 > tcp4
 
Bitfield< 3 > tcp3
 
Bitfield< 2 > tcp2
 
Bitfield< 1 > tcp1
 
Bitfield< 0 > tcp0
 
Bitfield< 16 > ttee
 
Bitfield< 15 > t15
 
Bitfield< 13 > t13
 
Bitfield< 12 > t12
 
Bitfield< 11 > t11
 
Bitfield< 10 > t10
 
Bitfield< 9 > t9
 
Bitfield< 8 > t8
 
Bitfield< 7 > t7
 
Bitfield< 6 > t6
 
Bitfield< 5 > t5
 
Bitfield< 4 > t4
 
Bitfield< 3 > t3
 
Bitfield< 2 > t2
 
Bitfield< 1 > t1
 
Bitfield< 0 > t0
 
Bitfield< 45 > nv2
 
Bitfield< 43 > nv1
 
Bitfield< 40 > apk
 
Bitfield< 38 > miocnce
 
Bitfield< 37 > tea
 
Bitfield< 36 > terr
 
Bitfield< 35 > tlor
 
Bitfield< 34 > e2h
 
Bitfield< 33 > id
 
Bitfield< 32 > cd
 
Bitfield< 31 > rw
 
Bitfield< 30 > trvm
 
Bitfield< 29 > hcd
 
Bitfield< 28 > tdz
 
Bitfield< 27 > tge
 
Bitfield< 26 > tvm
 
Bitfield< 25 > ttlb
 
Bitfield< 24 > tpu
 
Bitfield< 23 > tpc
 
Bitfield< 22 > tsw
 
Bitfield< 21 > tac
 
Bitfield< 21 > tacr
 
Bitfield< 20 > tidcp
 
Bitfield< 19 > tsc
 
Bitfield< 18 > tid3
 
Bitfield< 17 > tid2
 
Bitfield< 16 > tid1
 
Bitfield< 15 > tid0
 
Bitfield< 14 > twe
 
Bitfield< 13 > twi
 
Bitfield< 12 > dc
 
Bitfield< 11, 10 > bsu
 
Bitfield< 9 > fb
 
Bitfield< 8 > va
 
Bitfield< 8 > vse
 
Bitfield< 7 > vi
 
Bitfield< 6 > vf
 
Bitfield< 5 > amo
 
Bitfield< 4 > imo
 
Bitfield< 3 > fmo
 
Bitfield< 2 > ptw
 
Bitfield< 1 > swio
 
Bitfield< 0 > vm
 
Bitfield< 19 > rfr
 
Bitfield< 15 > nsasedis
 
Bitfield< 14 > nsd32dis
 
Bitfield< 13 > cp13
 
Bitfield< 12 > cp12
 
Bitfield< 11 > cp11
 
Bitfield< 10 > cp10
 
Bitfield< 9 > cp9
 
Bitfield< 8 > cp8
 
Bitfield< 7 > cp7
 
Bitfield< 6 > cp6
 
Bitfield< 5 > cp5
 
Bitfield< 4 > cp4
 
Bitfield< 3 > cp3
 
Bitfield< 2 > cp2
 
Bitfield< 1 > cp1
 
Bitfield< 0 > cp0
 
Bitfield< 20 > nmea
 
Bitfield< 19 > ease
 
Bitfield< 18 > eel2
 
Bitfield< 15 > teer
 
Bitfield< 9 > sif
 
Bitfield< 8 > hce
 
Bitfield< 7 > scd
 
Bitfield< 7 > smd
 
Bitfield< 6 > nEt
 
Bitfield< 5 > aw
 
Bitfield< 4 > fw
 
Bitfield< 3 > ea
 
Bitfield< 2 > fiq
 
Bitfield< 1 > irq
 
Bitfield< 0 > ns
 
Bitfield< 30 > enib
 
Bitfield< 30 > te
 
Bitfield< 29 > afe
 
Bitfield< 28 > tre
 
Bitfield< 27 > nmfi
 
Bitfield< 27 > enda
 
Bitfield< 26 > uci
 
Bitfield< 25 > ee
 
Bitfield< 24 > e0e
 
Bitfield< 23 > span
 
Bitfield< 23 > xp
 
Bitfield< 22 > u
 
Bitfield< 21 > fi
 
Bitfield< 20 > uwxn
 
Bitfield< 19 > dz
 
Bitfield< 19 > wxn
 
Bitfield< 18 > ntwe
 
Bitfield< 18 > rao2
 
Bitfield< 16 > ntwi
 
Bitfield< 16 > rao3
 
Bitfield< 15 > uct
 
Bitfield< 14 > rr
 
Bitfield< 14 > dze
 
Bitfield< 13 > endb
 
Bitfield< 11 > z
 
Bitfield< 10 > sw
 
Bitfield< 9, 8 > rs
 
Bitfield< 9 > uma
 
Bitfield< 8 > sed
 
Bitfield< 7 > b
 
Bitfield< 7 > itd
 
Bitfield< 6, 3 > rao4
 
Bitfield< 6 > thee
 
Bitfield< 5 > cp15ben
 
Bitfield< 4 > sa0
 
Bitfield< 3 > sa
 
Bitfield< 0 > m
 
Bitfield< 17, 16 > zen
 
Bitfield< 21, 20 > fpen
 
Bitfield< 29, 28 > rsvd
 
Bitfield< 30 > d32dis
 
Bitfield< 31 > asedis
 
 fsLow
 
Bitfield< 5, 0 > status
 
Bitfield< 7, 4 > domain
 
Bitfield< 9 > lpae
 
Bitfield< 10 > fsHigh
 
Bitfield< 11 > wnr
 
Bitfield< 12 > ext
 
Bitfield< 13 > cm
 
Bitfield< 1 > dzc
 
Bitfield< 2 > ofc
 
Bitfield< 3 > ufc
 
Bitfield< 4 > ixc
 
Bitfield< 7 > idc
 
Bitfield< 8 > ioe
 
Bitfield< 10 > ofe
 
Bitfield< 11 > ufe
 
Bitfield< 12 > ixe
 
Bitfield< 15 > ide
 
Bitfield< 18, 16 > len
 
Bitfield< 19 > fz16
 
Bitfield< 21, 20 > stride
 
Bitfield< 23, 22 > rMode
 
Bitfield< 24 > fz
 
Bitfield< 25 > dn
 
Bitfield< 26 > ahp
 
Bitfield< 27 > qc
 
Bitfield< 31 > n
 
Bitfield< 30 > en
 
Bitfield< 29, 0 > subArchDefined
 
 advSimdRegisters
 
Bitfield< 7, 4 > singlePrecision
 
Bitfield< 11, 8 > doublePrecision
 
Bitfield< 15, 12 > vfpExceptionTrapping
 
Bitfield< 19, 16 > divide
 
Bitfield< 23, 20 > squareRoot
 
Bitfield< 27, 24 > shortVectors
 
Bitfield< 31, 28 > roundingModes
 
 flushToZero
 
Bitfield< 7, 4 > defaultNaN
 
Bitfield< 11, 8 > advSimdLoadStore
 
Bitfield< 15, 12 > advSimdInteger
 
Bitfield< 19, 16 > advSimdSinglePrecision
 
Bitfield< 23, 20 > advSimdHalfPrecision
 
Bitfield< 27, 24 > vfpHalfPrecision
 
Bitfield< 31, 28 > raz
 
Bitfield< 4 > pd0
 
Bitfield< 5 > pd1
 
Bitfield< 2, 0 > t0sz
 
Bitfield< 6 > t2e
 
Bitfield< 7 > epd0
 
Bitfield< 9, 8 > irgn0
 
Bitfield< 11, 10 > orgn0
 
Bitfield< 13, 12 > sh0
 
Bitfield< 14 > tg0
 
Bitfield< 18, 16 > t1sz
 
Bitfield< 22 > a1
 
Bitfield< 23 > epd1
 
Bitfield< 25, 24 > irgn1
 
Bitfield< 27, 26 > orgn1
 
Bitfield< 29, 28 > sh1
 
Bitfield< 30 > tg1
 
Bitfield< 34, 32 > ips
 
Bitfield< 36 > as
 
Bitfield< 37 > tbi0
 
Bitfield< 38 > tbi1
 
Bitfield< 31 > eae
 
Bitfield< 18, 16 > ps
 
Bitfield< 20 > tbi
 
Bitfield< 41 > hpd0
 
Bitfield< 42 > hpd1
 
Bitfield< 24 > hpd
 
Bitfield< 29 > tbid
 
Bitfield< 39 > ha
 
Bitfield< 40 > hd
 
Bitfield< 51 > tbid0
 
Bitfield< 52 > tbid1
 
Bitfield< 4 > s
 
Bitfield< 5, 0 > t0sz64
 
Bitfield< 7, 6 > sl0
 
 tr0
 
Bitfield< 3, 2 > tr1
 
Bitfield< 5, 4 > tr2
 
Bitfield< 7, 6 > tr3
 
Bitfield< 9, 8 > tr4
 
Bitfield< 11, 10 > tr5
 
Bitfield< 13, 12 > tr6
 
Bitfield< 15, 14 > tr7
 
Bitfield< 16 > ds0
 
Bitfield< 17 > ds1
 
Bitfield< 18 > ns0
 
Bitfield< 19 > ns1
 
Bitfield< 24 > nos0
 
Bitfield< 25 > nos1
 
Bitfield< 26 > nos2
 
Bitfield< 27 > nos3
 
Bitfield< 28 > nos4
 
Bitfield< 29 > nos5
 
Bitfield< 30 > nos6
 
Bitfield< 31 > nos7
 
 ir0
 
Bitfield< 3, 2 > ir1
 
Bitfield< 5, 4 > ir2
 
Bitfield< 7, 6 > ir3
 
Bitfield< 9, 8 > ir4
 
Bitfield< 11, 10 > ir5
 
Bitfield< 13, 12 > ir6
 
Bitfield< 15, 14 > ir7
 
Bitfield< 17, 16 > or0
 
Bitfield< 19, 18 > or1
 
Bitfield< 21, 20 > or2
 
Bitfield< 23, 22 > or3
 
Bitfield< 25, 24 > or4
 
Bitfield< 27, 26 > or5
 
Bitfield< 29, 28 > or6
 
Bitfield< 31, 30 > or7
 
 asid
 
Bitfield< 31, 8 > procid
 
 sataRAMLatency
 
Bitfield< 4, 3 > reserved_4_3
 
Bitfield< 5 > dataRAMSetup
 
Bitfield< 8, 6 > tagRAMLatency
 
Bitfield< 9 > tagRAMSetup
 
Bitfield< 11, 10 > dataRAMSlice
 
Bitfield< 12 > tagRAMSlice
 
Bitfield< 20, 13 > reserved_20_13
 
Bitfield< 21 > eccandParityEnable
 
Bitfield< 22 > reserved_22
 
Bitfield< 23 > interptCtrlPresent
 
Bitfield< 25, 24 > numCPUs
 
Bitfield< 30, 26 > reserved_30_26
 
Bitfield< 31 > l2rstDISABLE_monitor
 
 iCacheLineSize
 
Bitfield< 13, 4 > raz_13_4
 
Bitfield< 15, 14 > l1IndexPolicy
 
Bitfield< 19, 16 > dCacheLineSize
 
Bitfield< 23, 20 > erg
 
Bitfield< 27, 24 > cwg
 
Bitfield< 28 > raz_28
 
Bitfield< 31, 29 > format
 
 sel
 
 attr
 
Bitfield< 39, 12 > pa
 
Bitfield< 8, 7 > sh
 
Bitfield< 6, 1 > fst
 
Bitfield< 6 > fs5
 
Bitfield< 5, 1 > fs4_0
 
 ec
 
Bitfield< 15, 0 > imm16
 
Bitfield< 30 > tam
 
Bitfield< 28 > tta_e2h
 
Bitfield< 13, 12 > res1_13_12_el2
 
Bitfield< 9 > res1_9_el2
 
Bitfield< 8 > res1_8_el2
 
Bitfield< 8 > ez
 
Bitfield< 7, 0 > res1_7_0_el2
 
 res0
 
Bitfield< 3 > oslm_3
 
Bitfield< 2 > nTT
 
Bitfield< 1 > oslk
 
Bitfield< 0 > oslm_0
 
 res0_2
 
Bitfield< 23, 20 > bt
 
Bitfield< 19, 16 > lbn
 
Bitfield< 15, 14 > ssc
 
Bitfield< 13 > hmc
 
Bitfield< 12, 9 > res0_1
 
Bitfield< 8, 5 > bas
 
Bitfield< 4, 3 > res0_0
 
Bitfield< 2, 1 > pmc
 
Bitfield< 28, 24 > mask
 
Bitfield< 20 > wt
 
Bitfield< 4, 3 > lsv
 
Bitfield< 2, 1 > pac
 
Bitfield< 30 > rxfull
 
Bitfield< 29 > txfull
 
Bitfield< 28 > res0_5
 
Bitfield< 27 > rxo
 
Bitfield< 26 > txu
 
Bitfield< 25, 24 > res0_4
 
Bitfield< 23, 22 > intdis
 
Bitfield< 20 > res0_3
 
Bitfield< 19 > sc2
 
Bitfield< 17 > spniddis
 
Bitfield< 16 > spiddis
 
Bitfield< 15 > mdbgen
 
Bitfield< 14 > hde
 
Bitfield< 13 > res0_
 
Bitfield< 12 > udccdis
 
Bitfield< 12 > tdcc
 
Bitfield< 6 > err
 
Bitfield< 5, 2 > moe
 
Bitfield< 30 > nsi
 
Bitfield< 28 > nsd
 
Bitfield< 27 > nsp
 
Bitfield< 26 > nss
 
Bitfield< 25 > nsu
 
Bitfield< 15 > mf
 
Bitfield< 14 > mi
 
Bitfield< 12 > md
 
Bitfield< 11 > mp
 
Bitfield< 10 > ms
 
Bitfield< 7 > sf
 
Bitfield< 6 > si
 
Bitfield< 4 > sd
 
Bitfield< 1 > su
 
 cidmask
 
Bitfield< 27, 24 > auxregs
 
Bitfield< 19, 16 > virtextns
 
Bitfield< 15, 12 > vectorcatch
 
Bitfield< 11, 8 > bpaddremask
 
Bitfield< 7, 4 > wpaddrmask
 
Bitfield< 3, 0 > pcsample
 
const unsigned MaxPhysAddrRange = 48
 
const int MaxInstSrcRegs
 
constexpr unsigned NumVecElemPerNeonVecReg = 4
 
constexpr unsigned NumVecElemPerVecReg = MaxSveVecLenInWords
 
const int NumIntArchRegs = NUM_ARCH_INTREGS
 
const int NumIntRegs = NUM_INTREGS
 
const int NumFloatRegs = 0
 
const int NumCCRegs = NUM_CCREGS
 
const int NumMiscRegs = NUM_MISCREGS
 
const int NumFloatV7ArchRegs = 64
 
const int NumVecV7ArchRegs = 16
 
const int NumVecV8ArchRegs = 32
 
const int NumVecSpecialRegs = 8
 
const int NumVecIntrlvRegs = 4
 
const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs
 
const int NumVecPredRegs = 18
 
const int TotalNumRegs
 
const int ReturnValueReg = 0
 
const int ReturnValueReg1 = 1
 
const int ReturnValueReg2 = 2
 
const int NumArgumentRegs = 4
 
const int NumArgumentRegs64 = 8
 
const int ArgumentReg0 = 0
 
const int ArgumentReg1 = 1
 
const int ArgumentReg2 = 2
 
const int ArgumentReg3 = 3
 
const int FramePointerReg = 11
 
const int StackPointerReg = INTREG_SP
 
const int ReturnAddressReg = INTREG_LR
 
const int PCReg = INTREG_PC
 
const int ZeroReg = INTREG_ZERO
 
const int VecSpecialElem = NumVecV8ArchRegs * NumVecElemPerNeonVecReg
 
const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs
 
const int INTRLVREG1 = INTRLVREG0 + 1
 
const int INTRLVREG2 = INTRLVREG0 + 2
 
const int INTRLVREG3 = INTRLVREG0 + 3
 
const int VECREG_UREG0 = 32
 
const int PREDREG_FFR = 16
 
const int PREDREG_UREG0 = 17
 
const int SyscallNumReg = ReturnValueReg
 
const int SyscallPseudoReturnReg = ReturnValueReg
 
const int SyscallSuccessReg = ReturnValueReg
 
 cond
 
Bitfield< 7, 2 > top6
 
Bitfield< 1, 0 > bottom2
 
 decoderFault
 
Bitfield< 61 > illegalExecution
 
Bitfield< 60 > debugStep
 
Bitfield< 59, 56 > sveLen
 
Bitfield< 55, 48 > itstate
 
Bitfield< 55, 52 > itstateCond
 
Bitfield< 51, 48 > itstateMask
 
Bitfield< 41, 40 > fpscrStride
 
Bitfield< 39, 37 > fpscrLen
 
Bitfield< 36 > thumb
 
Bitfield< 35 > bigThumb
 
Bitfield< 34 > aarch64
 
Bitfield< 33 > sevenAndFour
 
Bitfield< 32 > isMisc
 
uint32_t instBits
 
Bitfield< 27, 25 > encoding
 
Bitfield< 25 > useImm
 
Bitfield< 24, 21 > opcode
 
Bitfield< 24, 20 > mediaOpcode
 
Bitfield< 24 > opcode24
 
Bitfield< 24, 23 > opcode24_23
 
Bitfield< 23, 20 > opcode23_20
 
Bitfield< 23, 21 > opcode23_21
 
Bitfield< 20 > opcode20
 
Bitfield< 22 > opcode22
 
Bitfield< 19, 16 > opcode19_16
 
Bitfield< 19 > opcode19
 
Bitfield< 18 > opcode18
 
Bitfield< 15, 12 > opcode15_12
 
Bitfield< 15 > opcode15
 
Bitfield< 7, 4 > miscOpcode
 
Bitfield< 7, 5 > opc2
 
Bitfield< 7 > opcode7
 
Bitfield< 6 > opcode6
 
Bitfield< 4 > opcode4
 
Bitfield< 31, 28 > condCode
 
Bitfield< 20 > sField
 
Bitfield< 19, 16 > rn
 
Bitfield< 15, 12 > rd
 
Bitfield< 15, 12 > rt
 
Bitfield< 11, 7 > shiftSize
 
Bitfield< 6, 5 > shift
 
Bitfield< 3, 0 > rm
 
Bitfield< 23 > up
 
Bitfield< 22 > psruser
 
Bitfield< 21 > writeback
 
Bitfield< 20 > loadOp
 
 pubwl
 
Bitfield< 7, 0 > imm
 
Bitfield< 11, 8 > rotate
 
Bitfield< 11, 0 > immed11_0
 
Bitfield< 7, 0 > immed7_0
 
Bitfield< 11, 8 > immedHi11_8
 
Bitfield< 3, 0 > immedLo3_0
 
Bitfield< 15, 0 > regList
 
Bitfield< 23, 0 > offset
 
Bitfield< 23, 0 > immed23_0
 
Bitfield< 11, 8 > cpNum
 
Bitfield< 18, 16 > fn
 
Bitfield< 14, 12 > fd
 
Bitfield< 3 > fpRegImm
 
Bitfield< 3, 0 > fm
 
Bitfield< 2, 0 > fpImm
 
Bitfield< 24, 20 > punwl
 
Bitfield< 15, 8 > m5Func
 
Bitfield< 15, 13 > topcode15_13
 
Bitfield< 13, 11 > topcode13_11
 
Bitfield< 12, 11 > topcode12_11
 
Bitfield< 12, 10 > topcode12_10
 
Bitfield< 11, 9 > topcode11_9
 
Bitfield< 11, 8 > topcode11_8
 
Bitfield< 10, 9 > topcode10_9
 
Bitfield< 10, 8 > topcode10_8
 
Bitfield< 9, 6 > topcode9_6
 
Bitfield< 7 > topcode7
 
Bitfield< 7, 6 > topcode7_6
 
Bitfield< 7, 5 > topcode7_5
 
Bitfield< 7, 4 > topcode7_4
 
Bitfield< 3, 0 > topcode3_0
 
Bitfield< 28, 27 > htopcode12_11
 
Bitfield< 26, 25 > htopcode10_9
 
Bitfield< 25 > htopcode9
 
Bitfield< 25, 24 > htopcode9_8
 
Bitfield< 25, 21 > htopcode9_5
 
Bitfield< 25, 20 > htopcode9_4
 
Bitfield< 24 > htopcode8
 
Bitfield< 24, 23 > htopcode8_7
 
Bitfield< 24, 22 > htopcode8_6
 
Bitfield< 24, 21 > htopcode8_5
 
Bitfield< 23 > htopcode7
 
Bitfield< 23, 21 > htopcode7_5
 
Bitfield< 22 > htopcode6
 
Bitfield< 22, 21 > htopcode6_5
 
Bitfield< 21, 20 > htopcode5_4
 
Bitfield< 20 > htopcode4
 
Bitfield< 19, 16 > htrn
 
Bitfield< 20 > hts
 
Bitfield< 15 > ltopcode15
 
Bitfield< 11, 8 > ltopcode11_8
 
Bitfield< 7, 6 > ltopcode7_6
 
Bitfield< 7, 4 > ltopcode7_4
 
Bitfield< 4 > ltopcode4
 
Bitfield< 11, 8 > ltrd
 
Bitfield< 11, 8 > ltcoproc
 
constexpr unsigned MaxSveVecLenInBits = 2048
 
constexpr unsigned MaxSveVecLenInBytes = MaxSveVecLenInBits >> 3
 
constexpr unsigned MaxSveVecLenInWords = MaxSveVecLenInBits >> 5
 
constexpr unsigned MaxSveVecLenInDWords = MaxSveVecLenInBits >> 6
 
constexpr unsigned VecRegSizeBytes = MaxSveVecLenInBytes
 
constexpr unsigned VecPredRegSizeBits = MaxSveVecLenInBytes
 
constexpr unsigned VecPredRegHasPackedRepr = false
 
Bitfield< 9 > el0pten
 
Bitfield< 8 > el0vten
 
Bitfield< 7, 4 > evnti
 
Bitfield< 3 > evntdir
 
Bitfield< 2 > evnten
 
Bitfield< 1 > el0vcten
 
Bitfield< 0 > el0pcten
 
Bitfield< 16 > el1nvvct
 
Bitfield< 15 > el1nvpct
 
Bitfield< 14 > el1tvct
 
Bitfield< 13 > el1tvt
 
Bitfield< 1 > el1pcen
 
Bitfield< 0 > el1pcten
 
Bitfield< 11 > el1pten
 

Typedef Documentation

◆ ConstVecPredReg

Definition at line 76 of file registers.hh.

◆ ConstVecReg

Definition at line 70 of file registers.hh.

◆ FaultOffset

Definition at line 56 of file faults.hh.

◆ IntRegMap

typedef IntRegIndex ArmISA::IntRegMap[NUM_ARCH_INTREGS]

Definition at line 302 of file intregs.hh.

◆ MachInst

typedef uint32_t ArmISA::MachInst

Definition at line 52 of file types.hh.

◆ RegContextParam

Definition at line 586 of file types.hh.

◆ RegContextVal

typedef int ArmISA::RegContextVal

Definition at line 587 of file types.hh.

◆ VecElem

using ArmISA::VecElem = typedef uint32_t

Definition at line 68 of file registers.hh.

◆ VecPredReg

Definition at line 74 of file registers.hh.

◆ VecPredRegContainer

Definition at line 77 of file registers.hh.

◆ VecReg

using ArmISA::VecReg = typedef ::VecRegT<VecElem, NumVecElemPerVecReg, false>

Definition at line 69 of file registers.hh.

◆ VecRegContainer

Definition at line 71 of file registers.hh.

◆ VfpSavedState

typedef int ArmISA::VfpSavedState

Definition at line 211 of file vfp.hh.

◆ XReg

typedef uint64_t ArmISA::XReg

Definition at line 47 of file neon64_mem.hh.

Enumeration Type Documentation

◆ ArmExtendType

Enumerator
UXTB 
UXTH 
UXTW 
UXTX 
SXTB 
SXTH 
SXTW 
SXTX 

Definition at line 575 of file types.hh.

◆ ArmShiftType

Enumerator
LSL 
LSR 
ASR 
ROR 

Definition at line 567 of file types.hh.

◆ ccRegIndex

Enumerator
CCREG_NZ 
CCREG_C 
CCREG_V 
CCREG_GE 
CCREG_FP 
CCREG_ZERO 
NUM_CCREGS 

Definition at line 44 of file ccregs.hh.

◆ ConditionCode

Enumerator
COND_EQ 
COND_NE 
COND_CS 
COND_CC 
COND_MI 
COND_PL 
COND_VS 
COND_VC 
COND_HI 
COND_LS 
COND_GE 
COND_LT 
COND_GT 
COND_LE 
COND_AL 
COND_UC 

Definition at line 63 of file ccregs.hh.

◆ ConvertType

Enumerator
SINGLE_TO_DOUBLE 
SINGLE_TO_WORD 
SINGLE_TO_LONG 
DOUBLE_TO_SINGLE 
DOUBLE_TO_WORD 
DOUBLE_TO_LONG 
LONG_TO_SINGLE 
LONG_TO_DOUBLE 
LONG_TO_WORD 
LONG_TO_PS 
WORD_TO_SINGLE 
WORD_TO_DOUBLE 
WORD_TO_LONG 
WORD_TO_PS 
PL_TO_SINGLE 
PU_TO_SINGLE 

Definition at line 590 of file types.hh.

◆ DecoderFault

enum ArmISA::DecoderFault : std::uint8_t

Instruction decoder fault codes in ExtMachInst.

Enumerator
OK 

No fault.

UNALIGNED 

Unaligned instruction fault.

PANIC 

Internal gem5 error.

Definition at line 703 of file types.hh.

◆ ExceptionClass

Enumerator
EC_INVALID 
EC_UNKNOWN 
EC_TRAPPED_WFI_WFE 
EC_TRAPPED_CP15_MCR_MRC 
EC_TRAPPED_CP15_MCRR_MRRC 
EC_TRAPPED_CP14_MCR_MRC 
EC_TRAPPED_CP14_LDC_STC 
EC_TRAPPED_HCPTR 
EC_TRAPPED_SIMD_FP 
EC_TRAPPED_CP10_MRC_VMRS 
EC_TRAPPED_PAC 
EC_TRAPPED_BXJ 
EC_TRAPPED_CP14_MCRR_MRRC 
EC_ILLEGAL_INST 
EC_SVC_TO_HYP 
EC_SVC 
EC_HVC 
EC_SMC_TO_HYP 
EC_SMC 
EC_SVC_64 
EC_HVC_64 
EC_SMC_64 
EC_TRAPPED_MSR_MRS_64 
EC_TRAPPED_SVE 
EC_PREFETCH_ABORT_TO_HYP 
EC_PREFETCH_ABORT_LOWER_EL 
EC_PREFETCH_ABORT_FROM_HYP 
EC_PREFETCH_ABORT_CURR_EL 
EC_PC_ALIGNMENT 
EC_DATA_ABORT_TO_HYP 
EC_DATA_ABORT_LOWER_EL 
EC_DATA_ABORT_FROM_HYP 
EC_DATA_ABORT_CURR_EL 
EC_STACK_PTR_ALIGNMENT 
EC_FP_EXCEPTION 
EC_FP_EXCEPTION_64 
EC_SERROR 
EC_HW_BREAKPOINT 
EC_HW_BREAKPOINT_LOWER_EL 
EC_HW_BREAKPOINT_CURR_EL 
EC_SOFTWARE_STEP 
EC_SOFTWARE_STEP_LOWER_EL 
EC_SOFTWARE_STEP_CURR_EL 
EC_WATCHPOINT 
EC_WATCHPOINT_LOWER_EL 
EC_WATCHPOINT_CURR_EL 
EC_SOFTWARE_BREAKPOINT 
EC_VECTOR_CATCH 
EC_SOFTWARE_BREAKPOINT_64 

Definition at line 648 of file types.hh.

◆ ExceptionLevel

Enumerator
EL0 
EL1 
EL2 
EL3 

Definition at line 621 of file types.hh.

◆ FeExceptionBit

Enumerator
FeDivByZero 
FeInexact 
FeInvalid 
FeOverflow 
FeUnderflow 
FeAllExceptions 

Definition at line 82 of file vfp.hh.

◆ FeRoundingMode

Enumerator
FeRoundDown 
FeRoundNearest 
FeRoundZero 
FeRoundUpward 

Definition at line 92 of file vfp.hh.

◆ FpDataType

enum ArmISA::FpDataType
strong

Floating point data types.

Enumerator
Fp16 
Fp32 
Fp64 

Definition at line 162 of file pred_inst.hh.

◆ FPRounding

Enumerator
FPRounding_TIEEVEN 
FPRounding_POSINF 
FPRounding_NEGINF 
FPRounding_ZERO 
FPRounding_TIEAWAY 
FPRounding_ODD 

Definition at line 57 of file fplib.hh.

◆ InterruptTypes

Enumerator
INT_RST 
INT_ABT 
INT_IRQ 
INT_FIQ 
INT_SEV 
INT_VIRT_IRQ 
INT_VIRT_FIQ 
NumInterruptTypes 

Definition at line 57 of file interrupts.hh.

◆ IntRegIndex

Enumerator
INTREG_R0 
INTREG_R1 
INTREG_R2 
INTREG_R3 
INTREG_R4 
INTREG_R5 
INTREG_R6 
INTREG_R7 
INTREG_R8 
INTREG_R9 
INTREG_R10 
INTREG_R11 
INTREG_R12 
INTREG_R13 
INTREG_SP 
INTREG_R14 
INTREG_LR 
INTREG_R15 
INTREG_PC 
INTREG_R13_SVC 
INTREG_SP_SVC 
INTREG_R14_SVC 
INTREG_LR_SVC 
INTREG_R13_MON 
INTREG_SP_MON 
INTREG_R14_MON 
INTREG_LR_MON 
INTREG_R13_HYP 
INTREG_SP_HYP 
INTREG_R13_ABT 
INTREG_SP_ABT 
INTREG_R14_ABT 
INTREG_LR_ABT 
INTREG_R13_UND 
INTREG_SP_UND 
INTREG_R14_UND 
INTREG_LR_UND 
INTREG_R13_IRQ 
INTREG_SP_IRQ 
INTREG_R14_IRQ 
INTREG_LR_IRQ 
INTREG_R8_FIQ 
INTREG_R9_FIQ 
INTREG_R10_FIQ 
INTREG_R11_FIQ 
INTREG_R12_FIQ 
INTREG_R13_FIQ 
INTREG_SP_FIQ 
INTREG_R14_FIQ 
INTREG_LR_FIQ 
INTREG_ZERO 
INTREG_UREG0 
INTREG_UREG1 
INTREG_UREG2 
INTREG_DUMMY 
INTREG_SP0 
INTREG_SP1 
INTREG_SP2 
INTREG_SP3 
NUM_INTREGS 
NUM_ARCH_INTREGS 
INTREG_X0 
INTREG_X1 
INTREG_X2 
INTREG_X3 
INTREG_X4 
INTREG_X5 
INTREG_X6 
INTREG_X7 
INTREG_X8 
INTREG_X9 
INTREG_X10 
INTREG_X11 
INTREG_X12 
INTREG_X13 
INTREG_X14 
INTREG_X15 
INTREG_X16 
INTREG_X17 
INTREG_X18 
INTREG_X19 
INTREG_X20 
INTREG_X21 
INTREG_X22 
INTREG_X23 
INTREG_X24 
INTREG_X25 
INTREG_X26 
INTREG_X27 
INTREG_X28 
INTREG_X29 
INTREG_X30 
INTREG_X31 
INTREG_SPX 
INTREG_R0_USR 
INTREG_R1_USR 
INTREG_R2_USR 
INTREG_R3_USR 
INTREG_R4_USR 
INTREG_R5_USR 
INTREG_R6_USR 
INTREG_R7_USR 
INTREG_R8_USR 
INTREG_R9_USR 
INTREG_R10_USR 
INTREG_R11_USR 
INTREG_R12_USR 
INTREG_R13_USR 
INTREG_SP_USR 
INTREG_R14_USR 
INTREG_LR_USR 
INTREG_R15_USR 
INTREG_PC_USR 
INTREG_R0_SVC 
INTREG_R1_SVC 
INTREG_R2_SVC 
INTREG_R3_SVC 
INTREG_R4_SVC 
INTREG_R5_SVC 
INTREG_R6_SVC 
INTREG_R7_SVC 
INTREG_R8_SVC 
INTREG_R9_SVC 
INTREG_R10_SVC 
INTREG_R11_SVC 
INTREG_R12_SVC 
INTREG_PC_SVC 
INTREG_R15_SVC 
INTREG_R0_MON 
INTREG_R1_MON 
INTREG_R2_MON 
INTREG_R3_MON 
INTREG_R4_MON 
INTREG_R5_MON 
INTREG_R6_MON 
INTREG_R7_MON 
INTREG_R8_MON 
INTREG_R9_MON 
INTREG_R10_MON 
INTREG_R11_MON 
INTREG_R12_MON 
INTREG_PC_MON 
INTREG_R15_MON 
INTREG_R0_ABT 
INTREG_R1_ABT 
INTREG_R2_ABT 
INTREG_R3_ABT 
INTREG_R4_ABT 
INTREG_R5_ABT 
INTREG_R6_ABT 
INTREG_R7_ABT 
INTREG_R8_ABT 
INTREG_R9_ABT 
INTREG_R10_ABT 
INTREG_R11_ABT 
INTREG_R12_ABT 
INTREG_PC_ABT 
INTREG_R15_ABT 
INTREG_R0_HYP 
INTREG_R1_HYP 
INTREG_R2_HYP 
INTREG_R3_HYP 
INTREG_R4_HYP 
INTREG_R5_HYP 
INTREG_R6_HYP 
INTREG_R7_HYP 
INTREG_R8_HYP 
INTREG_R9_HYP 
INTREG_R10_HYP 
INTREG_R11_HYP 
INTREG_R12_HYP 
INTREG_LR_HYP 
INTREG_R14_HYP 
INTREG_PC_HYP 
INTREG_R15_HYP 
INTREG_R0_UND 
INTREG_R1_UND 
INTREG_R2_UND 
INTREG_R3_UND 
INTREG_R4_UND 
INTREG_R5_UND 
INTREG_R6_UND 
INTREG_R7_UND 
INTREG_R8_UND 
INTREG_R9_UND 
INTREG_R10_UND 
INTREG_R11_UND 
INTREG_R12_UND 
INTREG_PC_UND 
INTREG_R15_UND 
INTREG_R0_IRQ 
INTREG_R1_IRQ 
INTREG_R2_IRQ 
INTREG_R3_IRQ 
INTREG_R4_IRQ 
INTREG_R5_IRQ 
INTREG_R6_IRQ 
INTREG_R7_IRQ 
INTREG_R8_IRQ 
INTREG_R9_IRQ 
INTREG_R10_IRQ 
INTREG_R11_IRQ 
INTREG_R12_IRQ 
INTREG_PC_IRQ 
INTREG_R15_IRQ 
INTREG_R0_FIQ 
INTREG_R1_FIQ 
INTREG_R2_FIQ 
INTREG_R3_FIQ 
INTREG_R4_FIQ 
INTREG_R5_FIQ 
INTREG_R6_FIQ 
INTREG_R7_FIQ 
INTREG_PC_FIQ 
INTREG_R15_FIQ 

Definition at line 51 of file intregs.hh.

◆ LookupLevel

Enumerator
L0 
L1 
L2 
L3 
MAX_LOOKUP_LEVELS 

Definition at line 72 of file pagetable.hh.

◆ MiscRegIndex

Enumerator
MISCREG_CPSR 
MISCREG_SPSR 
MISCREG_SPSR_FIQ 
MISCREG_SPSR_IRQ 
MISCREG_SPSR_SVC 
MISCREG_SPSR_MON 
MISCREG_SPSR_ABT 
MISCREG_SPSR_HYP 
MISCREG_SPSR_UND 
MISCREG_ELR_HYP 
MISCREG_FPSID 
MISCREG_FPSCR 
MISCREG_MVFR1 
MISCREG_MVFR0 
MISCREG_FPEXC 
MISCREG_CPSR_MODE 
MISCREG_CPSR_Q 
MISCREG_FPSCR_EXC 
MISCREG_FPSCR_QC 
MISCREG_LOCKADDR 
MISCREG_LOCKFLAG 
MISCREG_PRRR_MAIR0 
MISCREG_PRRR_MAIR0_NS 
MISCREG_PRRR_MAIR0_S 
MISCREG_NMRR_MAIR1 
MISCREG_NMRR_MAIR1_NS 
MISCREG_NMRR_MAIR1_S 
MISCREG_PMXEVTYPER_PMCCFILTR 
MISCREG_SCTLR_RST 
MISCREG_SEV_MAILBOX 
MISCREG_DBGDIDR 
MISCREG_DBGDSCRint 
MISCREG_DBGDCCINT 
MISCREG_DBGDTRTXint 
MISCREG_DBGDTRRXint 
MISCREG_DBGWFAR 
MISCREG_DBGVCR 
MISCREG_DBGDTRRXext 
MISCREG_DBGDSCRext 
MISCREG_DBGDTRTXext 
MISCREG_DBGOSECCR 
MISCREG_DBGBVR0 
MISCREG_DBGBVR1 
MISCREG_DBGBVR2 
MISCREG_DBGBVR3 
MISCREG_DBGBVR4 
MISCREG_DBGBVR5 
MISCREG_DBGBVR6 
MISCREG_DBGBVR7 
MISCREG_DBGBVR8 
MISCREG_DBGBVR9 
MISCREG_DBGBVR10 
MISCREG_DBGBVR11 
MISCREG_DBGBVR12 
MISCREG_DBGBVR13 
MISCREG_DBGBVR14 
MISCREG_DBGBVR15 
MISCREG_DBGBCR0 
MISCREG_DBGBCR1 
MISCREG_DBGBCR2 
MISCREG_DBGBCR3 
MISCREG_DBGBCR4 
MISCREG_DBGBCR5 
MISCREG_DBGBCR6 
MISCREG_DBGBCR7 
MISCREG_DBGBCR8 
MISCREG_DBGBCR9 
MISCREG_DBGBCR10 
MISCREG_DBGBCR11 
MISCREG_DBGBCR12 
MISCREG_DBGBCR13 
MISCREG_DBGBCR14 
MISCREG_DBGBCR15 
MISCREG_DBGWVR0 
MISCREG_DBGWVR1 
MISCREG_DBGWVR2 
MISCREG_DBGWVR3 
MISCREG_DBGWVR4 
MISCREG_DBGWVR5 
MISCREG_DBGWVR6 
MISCREG_DBGWVR7 
MISCREG_DBGWVR8 
MISCREG_DBGWVR9 
MISCREG_DBGWVR10 
MISCREG_DBGWVR11 
MISCREG_DBGWVR12 
MISCREG_DBGWVR13 
MISCREG_DBGWVR14 
MISCREG_DBGWVR15 
MISCREG_DBGWCR0 
MISCREG_DBGWCR1 
MISCREG_DBGWCR2 
MISCREG_DBGWCR3 
MISCREG_DBGWCR4 
MISCREG_DBGWCR5 
MISCREG_DBGWCR6 
MISCREG_DBGWCR7 
MISCREG_DBGWCR8 
MISCREG_DBGWCR9 
MISCREG_DBGWCR10 
MISCREG_DBGWCR11 
MISCREG_DBGWCR12 
MISCREG_DBGWCR13 
MISCREG_DBGWCR14 
MISCREG_DBGWCR15 
MISCREG_DBGDRAR 
MISCREG_DBGBXVR0 
MISCREG_DBGBXVR1 
MISCREG_DBGBXVR2 
MISCREG_DBGBXVR3 
MISCREG_DBGBXVR4 
MISCREG_DBGBXVR5 
MISCREG_DBGBXVR6 
MISCREG_DBGBXVR7 
MISCREG_DBGBXVR8 
MISCREG_DBGBXVR9 
MISCREG_DBGBXVR10 
MISCREG_DBGBXVR11 
MISCREG_DBGBXVR12 
MISCREG_DBGBXVR13 
MISCREG_DBGBXVR14 
MISCREG_DBGBXVR15 
MISCREG_DBGOSLAR 
MISCREG_DBGOSLSR 
MISCREG_DBGOSDLR 
MISCREG_DBGPRCR 
MISCREG_DBGDSAR 
MISCREG_DBGCLAIMSET 
MISCREG_DBGCLAIMCLR 
MISCREG_DBGAUTHSTATUS 
MISCREG_DBGDEVID2 
MISCREG_DBGDEVID1 
MISCREG_DBGDEVID0 
MISCREG_TEECR 
MISCREG_JIDR 
MISCREG_TEEHBR 
MISCREG_JOSCR 
MISCREG_JMCR 
MISCREG_MIDR 
MISCREG_CTR 
MISCREG_TCMTR 
MISCREG_TLBTR 
MISCREG_MPIDR 
MISCREG_REVIDR 
MISCREG_ID_PFR0 
MISCREG_ID_PFR1 
MISCREG_ID_DFR0 
MISCREG_ID_AFR0 
MISCREG_ID_MMFR0 
MISCREG_ID_MMFR1 
MISCREG_ID_MMFR2 
MISCREG_ID_MMFR3 
MISCREG_ID_ISAR0 
MISCREG_ID_ISAR1 
MISCREG_ID_ISAR2 
MISCREG_ID_ISAR3 
MISCREG_ID_ISAR4 
MISCREG_ID_ISAR5 
MISCREG_CCSIDR 
MISCREG_CLIDR 
MISCREG_AIDR 
MISCREG_CSSELR 
MISCREG_CSSELR_NS 
MISCREG_CSSELR_S 
MISCREG_VPIDR 
MISCREG_VMPIDR 
MISCREG_SCTLR 
MISCREG_SCTLR_NS 
MISCREG_SCTLR_S 
MISCREG_ACTLR 
MISCREG_ACTLR_NS 
MISCREG_ACTLR_S 
MISCREG_CPACR 
MISCREG_SDCR 
MISCREG_SCR 
MISCREG_SDER 
MISCREG_NSACR 
MISCREG_HSCTLR 
MISCREG_HACTLR 
MISCREG_HCR 
MISCREG_HCR2 
MISCREG_HDCR 
MISCREG_HCPTR 
MISCREG_HSTR 
MISCREG_HACR 
MISCREG_TTBR0 
MISCREG_TTBR0_NS 
MISCREG_TTBR0_S 
MISCREG_TTBR1 
MISCREG_TTBR1_NS 
MISCREG_TTBR1_S 
MISCREG_TTBCR 
MISCREG_TTBCR_NS 
MISCREG_TTBCR_S 
MISCREG_HTCR 
MISCREG_VTCR 
MISCREG_DACR 
MISCREG_DACR_NS 
MISCREG_DACR_S 
MISCREG_DFSR 
MISCREG_DFSR_NS 
MISCREG_DFSR_S 
MISCREG_IFSR 
MISCREG_IFSR_NS 
MISCREG_IFSR_S 
MISCREG_ADFSR 
MISCREG_ADFSR_NS 
MISCREG_ADFSR_S 
MISCREG_AIFSR 
MISCREG_AIFSR_NS 
MISCREG_AIFSR_S 
MISCREG_HADFSR 
MISCREG_HAIFSR 
MISCREG_HSR 
MISCREG_DFAR 
MISCREG_DFAR_NS 
MISCREG_DFAR_S 
MISCREG_IFAR 
MISCREG_IFAR_NS 
MISCREG_IFAR_S 
MISCREG_HDFAR 
MISCREG_HIFAR 
MISCREG_HPFAR 
MISCREG_ICIALLUIS 
MISCREG_BPIALLIS 
MISCREG_PAR 
MISCREG_PAR_NS 
MISCREG_PAR_S 
MISCREG_ICIALLU 
MISCREG_ICIMVAU 
MISCREG_CP15ISB 
MISCREG_BPIALL 
MISCREG_BPIMVA 
MISCREG_DCIMVAC 
MISCREG_DCISW 
MISCREG_ATS1CPR 
MISCREG_ATS1CPW 
MISCREG_ATS1CUR 
MISCREG_ATS1CUW 
MISCREG_ATS12NSOPR 
MISCREG_ATS12NSOPW 
MISCREG_ATS12NSOUR 
MISCREG_ATS12NSOUW 
MISCREG_DCCMVAC 
MISCREG_DCCSW 
MISCREG_CP15DSB 
MISCREG_CP15DMB 
MISCREG_DCCMVAU 
MISCREG_DCCIMVAC 
MISCREG_DCCISW 
MISCREG_ATS1HR 
MISCREG_ATS1HW 
MISCREG_TLBIALLIS 
MISCREG_TLBIMVAIS 
MISCREG_TLBIASIDIS 
MISCREG_TLBIMVAAIS 
MISCREG_TLBIMVALIS 
MISCREG_TLBIMVAALIS 
MISCREG_ITLBIALL 
MISCREG_ITLBIMVA 
MISCREG_ITLBIASID 
MISCREG_DTLBIALL 
MISCREG_DTLBIMVA 
MISCREG_DTLBIASID 
MISCREG_TLBIALL 
MISCREG_TLBIMVA 
MISCREG_TLBIASID 
MISCREG_TLBIMVAA 
MISCREG_TLBIMVAL 
MISCREG_TLBIMVAAL 
MISCREG_TLBIIPAS2IS 
MISCREG_TLBIIPAS2LIS 
MISCREG_TLBIALLHIS 
MISCREG_TLBIMVAHIS 
MISCREG_TLBIALLNSNHIS 
MISCREG_TLBIMVALHIS 
MISCREG_TLBIIPAS2 
MISCREG_TLBIIPAS2L 
MISCREG_TLBIALLH 
MISCREG_TLBIMVAH 
MISCREG_TLBIALLNSNH 
MISCREG_TLBIMVALH 
MISCREG_PMCR 
MISCREG_PMCNTENSET 
MISCREG_PMCNTENCLR 
MISCREG_PMOVSR 
MISCREG_PMSWINC 
MISCREG_PMSELR 
MISCREG_PMCEID0 
MISCREG_PMCEID1 
MISCREG_PMCCNTR 
MISCREG_PMXEVTYPER 
MISCREG_PMCCFILTR 
MISCREG_PMXEVCNTR 
MISCREG_PMUSERENR 
MISCREG_PMINTENSET 
MISCREG_PMINTENCLR 
MISCREG_PMOVSSET 
MISCREG_L2CTLR 
MISCREG_L2ECTLR 
MISCREG_PRRR 
MISCREG_PRRR_NS 
MISCREG_PRRR_S 
MISCREG_MAIR0 
MISCREG_MAIR0_NS 
MISCREG_MAIR0_S 
MISCREG_NMRR 
MISCREG_NMRR_NS 
MISCREG_NMRR_S 
MISCREG_MAIR1 
MISCREG_MAIR1_NS 
MISCREG_MAIR1_S 
MISCREG_AMAIR0 
MISCREG_AMAIR0_NS 
MISCREG_AMAIR0_S 
MISCREG_AMAIR1 
MISCREG_AMAIR1_NS 
MISCREG_AMAIR1_S 
MISCREG_HMAIR0 
MISCREG_HMAIR1 
MISCREG_HAMAIR0 
MISCREG_HAMAIR1 
MISCREG_VBAR 
MISCREG_VBAR_NS 
MISCREG_VBAR_S 
MISCREG_MVBAR 
MISCREG_RMR 
MISCREG_ISR 
MISCREG_HVBAR 
MISCREG_FCSEIDR 
MISCREG_CONTEXTIDR 
MISCREG_CONTEXTIDR_NS 
MISCREG_CONTEXTIDR_S 
MISCREG_TPIDRURW 
MISCREG_TPIDRURW_NS 
MISCREG_TPIDRURW_S 
MISCREG_TPIDRURO 
MISCREG_TPIDRURO_NS 
MISCREG_TPIDRURO_S 
MISCREG_TPIDRPRW 
MISCREG_TPIDRPRW_NS 
MISCREG_TPIDRPRW_S 
MISCREG_HTPIDR 
MISCREG_CNTFRQ 
MISCREG_CNTPCT 
MISCREG_CNTVCT 
MISCREG_CNTP_CTL 
MISCREG_CNTP_CTL_NS 
MISCREG_CNTP_CTL_S 
MISCREG_CNTP_CVAL 
MISCREG_CNTP_CVAL_NS 
MISCREG_CNTP_CVAL_S 
MISCREG_CNTP_TVAL 
MISCREG_CNTP_TVAL_NS 
MISCREG_CNTP_TVAL_S 
MISCREG_CNTV_CTL 
MISCREG_CNTV_CVAL 
MISCREG_CNTV_TVAL 
MISCREG_CNTKCTL 
MISCREG_CNTHCTL 
MISCREG_CNTHP_CTL 
MISCREG_CNTHP_CVAL 
MISCREG_CNTHP_TVAL 
MISCREG_CNTVOFF 
MISCREG_IL1DATA0 
MISCREG_IL1DATA1 
MISCREG_IL1DATA2 
MISCREG_IL1DATA3 
MISCREG_DL1DATA0 
MISCREG_DL1DATA1 
MISCREG_DL1DATA2 
MISCREG_DL1DATA3 
MISCREG_DL1DATA4 
MISCREG_RAMINDEX 
MISCREG_L2ACTLR 
MISCREG_CBAR 
MISCREG_HTTBR 
MISCREG_VTTBR 
MISCREG_CPUMERRSR 
MISCREG_L2MERRSR 
MISCREG_MDCCINT_EL1 
MISCREG_OSDTRRX_EL1 
MISCREG_MDSCR_EL1 
MISCREG_OSDTRTX_EL1 
MISCREG_OSECCR_EL1 
MISCREG_DBGBVR0_EL1 
MISCREG_DBGBVR1_EL1 
MISCREG_DBGBVR2_EL1 
MISCREG_DBGBVR3_EL1 
MISCREG_DBGBVR4_EL1 
MISCREG_DBGBVR5_EL1 
MISCREG_DBGBVR6_EL1 
MISCREG_DBGBVR7_EL1 
MISCREG_DBGBVR8_EL1 
MISCREG_DBGBVR9_EL1 
MISCREG_DBGBVR10_EL1 
MISCREG_DBGBVR11_EL1 
MISCREG_DBGBVR12_EL1 
MISCREG_DBGBVR13_EL1 
MISCREG_DBGBVR14_EL1 
MISCREG_DBGBVR15_EL1 
MISCREG_DBGBCR0_EL1 
MISCREG_DBGBCR1_EL1 
MISCREG_DBGBCR2_EL1 
MISCREG_DBGBCR3_EL1 
MISCREG_DBGBCR4_EL1 
MISCREG_DBGBCR5_EL1 
MISCREG_DBGBCR6_EL1 
MISCREG_DBGBCR7_EL1 
MISCREG_DBGBCR8_EL1 
MISCREG_DBGBCR9_EL1 
MISCREG_DBGBCR10_EL1 
MISCREG_DBGBCR11_EL1 
MISCREG_DBGBCR12_EL1 
MISCREG_DBGBCR13_EL1 
MISCREG_DBGBCR14_EL1 
MISCREG_DBGBCR15_EL1 
MISCREG_DBGWVR0_EL1 
MISCREG_DBGWVR1_EL1 
MISCREG_DBGWVR2_EL1 
MISCREG_DBGWVR3_EL1 
MISCREG_DBGWVR4_EL1 
MISCREG_DBGWVR5_EL1 
MISCREG_DBGWVR6_EL1 
MISCREG_DBGWVR7_EL1 
MISCREG_DBGWVR8_EL1 
MISCREG_DBGWVR9_EL1 
MISCREG_DBGWVR10_EL1 
MISCREG_DBGWVR11_EL1 
MISCREG_DBGWVR12_EL1 
MISCREG_DBGWVR13_EL1 
MISCREG_DBGWVR14_EL1 
MISCREG_DBGWVR15_EL1 
MISCREG_DBGWCR0_EL1 
MISCREG_DBGWCR1_EL1 
MISCREG_DBGWCR2_EL1 
MISCREG_DBGWCR3_EL1 
MISCREG_DBGWCR4_EL1 
MISCREG_DBGWCR5_EL1 
MISCREG_DBGWCR6_EL1 
MISCREG_DBGWCR7_EL1 
MISCREG_DBGWCR8_EL1 
MISCREG_DBGWCR9_EL1 
MISCREG_DBGWCR10_EL1 
MISCREG_DBGWCR11_EL1 
MISCREG_DBGWCR12_EL1 
MISCREG_DBGWCR13_EL1 
MISCREG_DBGWCR14_EL1 
MISCREG_DBGWCR15_EL1 
MISCREG_MDCCSR_EL0 
MISCREG_MDDTR_EL0 
MISCREG_MDDTRTX_EL0 
MISCREG_MDDTRRX_EL0 
MISCREG_DBGVCR32_EL2 
MISCREG_MDRAR_EL1 
MISCREG_OSLAR_EL1 
MISCREG_OSLSR_EL1 
MISCREG_OSDLR_EL1 
MISCREG_DBGPRCR_EL1 
MISCREG_DBGCLAIMSET_EL1 
MISCREG_DBGCLAIMCLR_EL1 
MISCREG_DBGAUTHSTATUS_EL1 
MISCREG_TEECR32_EL1 
MISCREG_TEEHBR32_EL1 
MISCREG_MIDR_EL1 
MISCREG_MPIDR_EL1 
MISCREG_REVIDR_EL1 
MISCREG_ID_PFR0_EL1 
MISCREG_ID_PFR1_EL1 
MISCREG_ID_DFR0_EL1 
MISCREG_ID_AFR0_EL1 
MISCREG_ID_MMFR0_EL1 
MISCREG_ID_MMFR1_EL1 
MISCREG_ID_MMFR2_EL1 
MISCREG_ID_MMFR3_EL1 
MISCREG_ID_ISAR0_EL1 
MISCREG_ID_ISAR1_EL1 
MISCREG_ID_ISAR2_EL1 
MISCREG_ID_ISAR3_EL1 
MISCREG_ID_ISAR4_EL1 
MISCREG_ID_ISAR5_EL1 
MISCREG_MVFR0_EL1 
MISCREG_MVFR1_EL1 
MISCREG_MVFR2_EL1 
MISCREG_ID_AA64PFR0_EL1 
MISCREG_ID_AA64PFR1_EL1 
MISCREG_ID_AA64DFR0_EL1 
MISCREG_ID_AA64DFR1_EL1 
MISCREG_ID_AA64AFR0_EL1 
MISCREG_ID_AA64AFR1_EL1 
MISCREG_ID_AA64ISAR0_EL1 
MISCREG_ID_AA64ISAR1_EL1 
MISCREG_ID_AA64MMFR0_EL1 
MISCREG_ID_AA64MMFR1_EL1 
MISCREG_CCSIDR_EL1 
MISCREG_CLIDR_EL1 
MISCREG_AIDR_EL1 
MISCREG_CSSELR_EL1 
MISCREG_CTR_EL0 
MISCREG_DCZID_EL0 
MISCREG_VPIDR_EL2 
MISCREG_VMPIDR_EL2 
MISCREG_SCTLR_EL1 
MISCREG_SCTLR_EL12 
MISCREG_ACTLR_EL1 
MISCREG_CPACR_EL1 
MISCREG_CPACR_EL12 
MISCREG_SCTLR_EL2 
MISCREG_ACTLR_EL2 
MISCREG_HCR_EL2 
MISCREG_MDCR_EL2 
MISCREG_CPTR_EL2 
MISCREG_HSTR_EL2 
MISCREG_HACR_EL2 
MISCREG_SCTLR_EL3 
MISCREG_ACTLR_EL3 
MISCREG_SCR_EL3 
MISCREG_SDER32_EL3 
MISCREG_CPTR_EL3 
MISCREG_MDCR_EL3 
MISCREG_TTBR0_EL1 
MISCREG_TTBR0_EL12 
MISCREG_TTBR1_EL1 
MISCREG_TTBR1_EL12 
MISCREG_TCR_EL1 
MISCREG_TCR_EL12 
MISCREG_TTBR0_EL2 
MISCREG_TCR_EL2 
MISCREG_VTTBR_EL2 
MISCREG_VTCR_EL2 
MISCREG_VSTTBR_EL2 
MISCREG_VSTCR_EL2 
MISCREG_TTBR0_EL3 
MISCREG_TCR_EL3 
MISCREG_DACR32_EL2 
MISCREG_SPSR_EL1 
MISCREG_SPSR_EL12 
MISCREG_ELR_EL1 
MISCREG_ELR_EL12 
MISCREG_SP_EL0 
MISCREG_SPSEL 
MISCREG_CURRENTEL 
MISCREG_NZCV 
MISCREG_DAIF 
MISCREG_FPCR 
MISCREG_FPSR 
MISCREG_DSPSR_EL0 
MISCREG_DLR_EL0 
MISCREG_SPSR_EL2 
MISCREG_ELR_EL2 
MISCREG_SP_EL1 
MISCREG_SPSR_IRQ_AA64 
MISCREG_SPSR_ABT_AA64 
MISCREG_SPSR_UND_AA64 
MISCREG_SPSR_FIQ_AA64 
MISCREG_SPSR_EL3 
MISCREG_ELR_EL3 
MISCREG_SP_EL2 
MISCREG_AFSR0_EL1 
MISCREG_AFSR0_EL12 
MISCREG_AFSR1_EL1 
MISCREG_AFSR1_EL12 
MISCREG_ESR_EL1 
MISCREG_ESR_EL12 
MISCREG_IFSR32_EL2 
MISCREG_AFSR0_EL2 
MISCREG_AFSR1_EL2 
MISCREG_ESR_EL2 
MISCREG_FPEXC32_EL2 
MISCREG_AFSR0_EL3 
MISCREG_AFSR1_EL3 
MISCREG_ESR_EL3 
MISCREG_FAR_EL1 
MISCREG_FAR_EL12 
MISCREG_FAR_EL2 
MISCREG_HPFAR_EL2 
MISCREG_FAR_EL3 
MISCREG_IC_IALLUIS 
MISCREG_PAR_EL1 
MISCREG_IC_IALLU 
MISCREG_DC_IVAC_Xt 
MISCREG_DC_ISW_Xt 
MISCREG_AT_S1E1R_Xt 
MISCREG_AT_S1E1W_Xt 
MISCREG_AT_S1E0R_Xt 
MISCREG_AT_S1E0W_Xt 
MISCREG_DC_CSW_Xt 
MISCREG_DC_CISW_Xt 
MISCREG_DC_ZVA_Xt 
MISCREG_IC_IVAU_Xt 
MISCREG_DC_CVAC_Xt 
MISCREG_DC_CVAU_Xt 
MISCREG_DC_CIVAC_Xt 
MISCREG_AT_S1E2R_Xt 
MISCREG_AT_S1E2W_Xt 
MISCREG_AT_S12E1R_Xt 
MISCREG_AT_S12E1W_Xt 
MISCREG_AT_S12E0R_Xt 
MISCREG_AT_S12E0W_Xt 
MISCREG_AT_S1E3R_Xt 
MISCREG_AT_S1E3W_Xt 
MISCREG_TLBI_VMALLE1IS 
MISCREG_TLBI_VAE1IS_Xt 
MISCREG_TLBI_ASIDE1IS_Xt 
MISCREG_TLBI_VAAE1IS_Xt 
MISCREG_TLBI_VALE1IS_Xt 
MISCREG_TLBI_VAALE1IS_Xt 
MISCREG_TLBI_VMALLE1 
MISCREG_TLBI_VAE1_Xt 
MISCREG_TLBI_ASIDE1_Xt 
MISCREG_TLBI_VAAE1_Xt 
MISCREG_TLBI_VALE1_Xt 
MISCREG_TLBI_VAALE1_Xt 
MISCREG_TLBI_IPAS2E1IS_Xt 
MISCREG_TLBI_IPAS2LE1IS_Xt 
MISCREG_TLBI_ALLE2IS 
MISCREG_TLBI_VAE2IS_Xt 
MISCREG_TLBI_ALLE1IS 
MISCREG_TLBI_VALE2IS_Xt 
MISCREG_TLBI_VMALLS12E1IS 
MISCREG_TLBI_IPAS2E1_Xt 
MISCREG_TLBI_IPAS2LE1_Xt 
MISCREG_TLBI_ALLE2 
MISCREG_TLBI_VAE2_Xt 
MISCREG_TLBI_ALLE1 
MISCREG_TLBI_VALE2_Xt 
MISCREG_TLBI_VMALLS12E1 
MISCREG_TLBI_ALLE3IS 
MISCREG_TLBI_VAE3IS_Xt 
MISCREG_TLBI_VALE3IS_Xt 
MISCREG_TLBI_ALLE3 
MISCREG_TLBI_VAE3_Xt 
MISCREG_TLBI_VALE3_Xt 
MISCREG_PMINTENSET_EL1 
MISCREG_PMINTENCLR_EL1 
MISCREG_PMCR_EL0 
MISCREG_PMCNTENSET_EL0 
MISCREG_PMCNTENCLR_EL0 
MISCREG_PMOVSCLR_EL0 
MISCREG_PMSWINC_EL0 
MISCREG_PMSELR_EL0 
MISCREG_PMCEID0_EL0 
MISCREG_PMCEID1_EL0 
MISCREG_PMCCNTR_EL0 
MISCREG_PMXEVTYPER_EL0 
MISCREG_PMCCFILTR_EL0 
MISCREG_PMXEVCNTR_EL0 
MISCREG_PMUSERENR_EL0 
MISCREG_PMOVSSET_EL0 
MISCREG_MAIR_EL1 
MISCREG_MAIR_EL12 
MISCREG_AMAIR_EL1 
MISCREG_AMAIR_EL12 
MISCREG_MAIR_EL2 
MISCREG_AMAIR_EL2 
MISCREG_MAIR_EL3 
MISCREG_AMAIR_EL3 
MISCREG_L2CTLR_EL1 
MISCREG_L2ECTLR_EL1 
MISCREG_VBAR_EL1 
MISCREG_VBAR_EL12 
MISCREG_RVBAR_EL1 
MISCREG_ISR_EL1 
MISCREG_VBAR_EL2 
MISCREG_RVBAR_EL2 
MISCREG_VBAR_EL3 
MISCREG_RVBAR_EL3 
MISCREG_RMR_EL3 
MISCREG_CONTEXTIDR_EL1 
MISCREG_CONTEXTIDR_EL12 
MISCREG_TPIDR_EL1 
MISCREG_TPIDR_EL0 
MISCREG_TPIDRRO_EL0 
MISCREG_TPIDR_EL2 
MISCREG_TPIDR_EL3 
MISCREG_CNTFRQ_EL0 
MISCREG_CNTPCT_EL0 
MISCREG_CNTVCT_EL0 
MISCREG_CNTP_CTL_EL0 
MISCREG_CNTP_CVAL_EL0 
MISCREG_CNTP_TVAL_EL0 
MISCREG_CNTV_CTL_EL0 
MISCREG_CNTV_CVAL_EL0 
MISCREG_CNTV_TVAL_EL0 
MISCREG_CNTP_CTL_EL02 
MISCREG_CNTP_CVAL_EL02 
MISCREG_CNTP_TVAL_EL02 
MISCREG_CNTV_CTL_EL02 
MISCREG_CNTV_CVAL_EL02 
MISCREG_CNTV_TVAL_EL02 
MISCREG_CNTKCTL_EL1 
MISCREG_CNTKCTL_EL12 
MISCREG_CNTPS_CTL_EL1 
MISCREG_CNTPS_CVAL_EL1 
MISCREG_CNTPS_TVAL_EL1 
MISCREG_CNTHCTL_EL2 
MISCREG_CNTHP_CTL_EL2 
MISCREG_CNTHP_CVAL_EL2 
MISCREG_CNTHP_TVAL_EL2 
MISCREG_CNTHPS_CTL_EL2 
MISCREG_CNTHPS_CVAL_EL2 
MISCREG_CNTHPS_TVAL_EL2 
MISCREG_CNTHV_CTL_EL2 
MISCREG_CNTHV_CVAL_EL2 
MISCREG_CNTHV_TVAL_EL2 
MISCREG_CNTHVS_CTL_EL2 
MISCREG_CNTHVS_CVAL_EL2 
MISCREG_CNTHVS_TVAL_EL2 
MISCREG_CNTVOFF_EL2 
MISCREG_PMEVCNTR0_EL0 
MISCREG_PMEVCNTR1_EL0 
MISCREG_PMEVCNTR2_EL0 
MISCREG_PMEVCNTR3_EL0 
MISCREG_PMEVCNTR4_EL0 
MISCREG_PMEVCNTR5_EL0 
MISCREG_PMEVTYPER0_EL0 
MISCREG_PMEVTYPER1_EL0 
MISCREG_PMEVTYPER2_EL0 
MISCREG_PMEVTYPER3_EL0 
MISCREG_PMEVTYPER4_EL0 
MISCREG_PMEVTYPER5_EL0 
MISCREG_IL1DATA0_EL1 
MISCREG_IL1DATA1_EL1 
MISCREG_IL1DATA2_EL1 
MISCREG_IL1DATA3_EL1 
MISCREG_DL1DATA0_EL1 
MISCREG_DL1DATA1_EL1 
MISCREG_DL1DATA2_EL1 
MISCREG_DL1DATA3_EL1 
MISCREG_DL1DATA4_EL1 
MISCREG_L2ACTLR_EL1 
MISCREG_CPUACTLR_EL1 
MISCREG_CPUECTLR_EL1 
MISCREG_CPUMERRSR_EL1 
MISCREG_L2MERRSR_EL1 
MISCREG_CBAR_EL1 
MISCREG_CONTEXTIDR_EL2 
MISCREG_TTBR1_EL2 
MISCREG_ID_AA64MMFR2_EL1 
MISCREG_APDAKeyHi_EL1 
MISCREG_APDAKeyLo_EL1 
MISCREG_APDBKeyHi_EL1 
MISCREG_APDBKeyLo_EL1 
MISCREG_APGAKeyHi_EL1 
MISCREG_APGAKeyLo_EL1 
MISCREG_APIAKeyHi_EL1 
MISCREG_APIAKeyLo_EL1 
MISCREG_APIBKeyHi_EL1 
MISCREG_APIBKeyLo_EL1 
MISCREG_ICC_PMR_EL1 
MISCREG_ICC_IAR0_EL1 
MISCREG_ICC_EOIR0_EL1 
MISCREG_ICC_HPPIR0_EL1 
MISCREG_ICC_BPR0_EL1 
MISCREG_ICC_AP0R0_EL1 
MISCREG_ICC_AP0R1_EL1 
MISCREG_ICC_AP0R2_EL1 
MISCREG_ICC_AP0R3_EL1 
MISCREG_ICC_AP1R0_EL1 
MISCREG_ICC_AP1R0_EL1_NS 
MISCREG_ICC_AP1R0_EL1_S 
MISCREG_ICC_AP1R1_EL1 
MISCREG_ICC_AP1R1_EL1_NS 
MISCREG_ICC_AP1R1_EL1_S 
MISCREG_ICC_AP1R2_EL1 
MISCREG_ICC_AP1R2_EL1_NS 
MISCREG_ICC_AP1R2_EL1_S 
MISCREG_ICC_AP1R3_EL1 
MISCREG_ICC_AP1R3_EL1_NS 
MISCREG_ICC_AP1R3_EL1_S 
MISCREG_ICC_DIR_EL1 
MISCREG_ICC_RPR_EL1 
MISCREG_ICC_SGI1R_EL1 
MISCREG_ICC_ASGI1R_EL1 
MISCREG_ICC_SGI0R_EL1 
MISCREG_ICC_IAR1_EL1 
MISCREG_ICC_EOIR1_EL1 
MISCREG_ICC_HPPIR1_EL1 
MISCREG_ICC_BPR1_EL1 
MISCREG_ICC_BPR1_EL1_NS 
MISCREG_ICC_BPR1_EL1_S 
MISCREG_ICC_CTLR_EL1 
MISCREG_ICC_CTLR_EL1_NS 
MISCREG_ICC_CTLR_EL1_S 
MISCREG_ICC_SRE_EL1 
MISCREG_ICC_SRE_EL1_NS 
MISCREG_ICC_SRE_EL1_S 
MISCREG_ICC_IGRPEN0_EL1 
MISCREG_ICC_IGRPEN1_EL1 
MISCREG_ICC_IGRPEN1_EL1_NS 
MISCREG_ICC_IGRPEN1_EL1_S 
MISCREG_ICC_SRE_EL2 
MISCREG_ICC_CTLR_EL3 
MISCREG_ICC_SRE_EL3 
MISCREG_ICC_IGRPEN1_EL3 
MISCREG_ICH_AP0R0_EL2 
MISCREG_ICH_AP0R1_EL2 
MISCREG_ICH_AP0R2_EL2 
MISCREG_ICH_AP0R3_EL2 
MISCREG_ICH_AP1R0_EL2 
MISCREG_ICH_AP1R1_EL2 
MISCREG_ICH_AP1R2_EL2 
MISCREG_ICH_AP1R3_EL2 
MISCREG_ICH_HCR_EL2 
MISCREG_ICH_VTR_EL2 
MISCREG_ICH_MISR_EL2 
MISCREG_ICH_EISR_EL2 
MISCREG_ICH_ELRSR_EL2 
MISCREG_ICH_VMCR_EL2 
MISCREG_ICH_LR0_EL2 
MISCREG_ICH_LR1_EL2 
MISCREG_ICH_LR2_EL2 
MISCREG_ICH_LR3_EL2 
MISCREG_ICH_LR4_EL2 
MISCREG_ICH_LR5_EL2 
MISCREG_ICH_LR6_EL2 
MISCREG_ICH_LR7_EL2 
MISCREG_ICH_LR8_EL2 
MISCREG_ICH_LR9_EL2 
MISCREG_ICH_LR10_EL2 
MISCREG_ICH_LR11_EL2 
MISCREG_ICH_LR12_EL2 
MISCREG_ICH_LR13_EL2 
MISCREG_ICH_LR14_EL2 
MISCREG_ICH_LR15_EL2 
MISCREG_ICV_PMR_EL1 
MISCREG_ICV_IAR0_EL1 
MISCREG_ICV_EOIR0_EL1 
MISCREG_ICV_HPPIR0_EL1 
MISCREG_ICV_BPR0_EL1 
MISCREG_ICV_AP0R0_EL1 
MISCREG_ICV_AP0R1_EL1 
MISCREG_ICV_AP0R2_EL1 
MISCREG_ICV_AP0R3_EL1 
MISCREG_ICV_AP1R0_EL1 
MISCREG_ICV_AP1R0_EL1_NS 
MISCREG_ICV_AP1R0_EL1_S 
MISCREG_ICV_AP1R1_EL1 
MISCREG_ICV_AP1R1_EL1_NS 
MISCREG_ICV_AP1R1_EL1_S 
MISCREG_ICV_AP1R2_EL1 
MISCREG_ICV_AP1R2_EL1_NS 
MISCREG_ICV_AP1R2_EL1_S 
MISCREG_ICV_AP1R3_EL1 
MISCREG_ICV_AP1R3_EL1_NS 
MISCREG_ICV_AP1R3_EL1_S 
MISCREG_ICV_DIR_EL1 
MISCREG_ICV_RPR_EL1 
MISCREG_ICV_SGI1R_EL1 
MISCREG_ICV_ASGI1R_EL1 
MISCREG_ICV_SGI0R_EL1 
MISCREG_ICV_IAR1_EL1 
MISCREG_ICV_EOIR1_EL1 
MISCREG_ICV_HPPIR1_EL1 
MISCREG_ICV_BPR1_EL1 
MISCREG_ICV_BPR1_EL1_NS 
MISCREG_ICV_BPR1_EL1_S 
MISCREG_ICV_CTLR_EL1 
MISCREG_ICV_CTLR_EL1_NS 
MISCREG_ICV_CTLR_EL1_S 
MISCREG_ICV_SRE_EL1 
MISCREG_ICV_SRE_EL1_NS 
MISCREG_ICV_SRE_EL1_S 
MISCREG_ICV_IGRPEN0_EL1 
MISCREG_ICV_IGRPEN1_EL1 
MISCREG_ICV_IGRPEN1_EL1_NS 
MISCREG_ICV_IGRPEN1_EL1_S 
MISCREG_ICC_AP0R0 
MISCREG_ICC_AP0R1 
MISCREG_ICC_AP0R2 
MISCREG_ICC_AP0R3 
MISCREG_ICC_AP1R0 
MISCREG_ICC_AP1R0_NS 
MISCREG_ICC_AP1R0_S 
MISCREG_ICC_AP1R1 
MISCREG_ICC_AP1R1_NS 
MISCREG_ICC_AP1R1_S 
MISCREG_ICC_AP1R2 
MISCREG_ICC_AP1R2_NS 
MISCREG_ICC_AP1R2_S 
MISCREG_ICC_AP1R3 
MISCREG_ICC_AP1R3_NS 
MISCREG_ICC_AP1R3_S 
MISCREG_ICC_ASGI1R 
MISCREG_ICC_BPR0 
MISCREG_ICC_BPR1 
MISCREG_ICC_BPR1_NS 
MISCREG_ICC_BPR1_S 
MISCREG_ICC_CTLR 
MISCREG_ICC_CTLR_NS 
MISCREG_ICC_CTLR_S 
MISCREG_ICC_DIR 
MISCREG_ICC_EOIR0 
MISCREG_ICC_EOIR1 
MISCREG_ICC_HPPIR0 
MISCREG_ICC_HPPIR1 
MISCREG_ICC_HSRE 
MISCREG_ICC_IAR0 
MISCREG_ICC_IAR1 
MISCREG_ICC_IGRPEN0 
MISCREG_ICC_IGRPEN1 
MISCREG_ICC_IGRPEN1_NS 
MISCREG_ICC_IGRPEN1_S 
MISCREG_ICC_MCTLR 
MISCREG_ICC_MGRPEN1 
MISCREG_ICC_MSRE 
MISCREG_ICC_PMR 
MISCREG_ICC_RPR 
MISCREG_ICC_SGI0R 
MISCREG_ICC_SGI1R 
MISCREG_ICC_SRE 
MISCREG_ICC_SRE_NS 
MISCREG_ICC_SRE_S 
MISCREG_ICH_AP0R0 
MISCREG_ICH_AP0R1 
MISCREG_ICH_AP0R2 
MISCREG_ICH_AP0R3 
MISCREG_ICH_AP1R0 
MISCREG_ICH_AP1R1 
MISCREG_ICH_AP1R2 
MISCREG_ICH_AP1R3 
MISCREG_ICH_HCR 
MISCREG_ICH_VTR 
MISCREG_ICH_MISR 
MISCREG_ICH_EISR 
MISCREG_ICH_ELRSR 
MISCREG_ICH_VMCR 
MISCREG_ICH_LR0 
MISCREG_ICH_LR1 
MISCREG_ICH_LR2 
MISCREG_ICH_LR3 
MISCREG_ICH_LR4 
MISCREG_ICH_LR5 
MISCREG_ICH_LR6 
MISCREG_ICH_LR7 
MISCREG_ICH_LR8 
MISCREG_ICH_LR9 
MISCREG_ICH_LR10 
MISCREG_ICH_LR11 
MISCREG_ICH_LR12 
MISCREG_ICH_LR13 
MISCREG_ICH_LR14 
MISCREG_ICH_LR15 
MISCREG_ICH_LRC0 
MISCREG_ICH_LRC1 
MISCREG_ICH_LRC2 
MISCREG_ICH_LRC3 
MISCREG_ICH_LRC4 
MISCREG_ICH_LRC5 
MISCREG_ICH_LRC6 
MISCREG_ICH_LRC7 
MISCREG_ICH_LRC8 
MISCREG_ICH_LRC9 
MISCREG_ICH_LRC10 
MISCREG_ICH_LRC11 
MISCREG_ICH_LRC12 
MISCREG_ICH_LRC13 
MISCREG_ICH_LRC14 
MISCREG_ICH_LRC15 
MISCREG_ID_AA64ZFR0_EL1 
MISCREG_ZCR_EL3 
MISCREG_ZCR_EL2 
MISCREG_ZCR_EL12 
MISCREG_ZCR_EL1 
NUM_PHYS_MISCREGS 
MISCREG_NOP 
MISCREG_RAZ 
MISCREG_CP14_UNIMPL 
MISCREG_CP15_UNIMPL 
MISCREG_UNKNOWN 
MISCREG_IMPDEF_UNIMPL 
MISCREG_ERRIDR_EL1 
MISCREG_ERRSELR_EL1 
MISCREG_ERXFR_EL1 
MISCREG_ERXCTLR_EL1 
MISCREG_ERXSTATUS_EL1 
MISCREG_ERXADDR_EL1 
MISCREG_ERXMISC0_EL1 
MISCREG_ERXMISC1_EL1 
MISCREG_DISR_EL1 
MISCREG_VSESR_EL2 
MISCREG_VDISR_EL2 
MISCREG_PAN 
NUM_MISCREGS 

Definition at line 56 of file miscregs.hh.

◆ MiscRegInfo

Enumerator
MISCREG_IMPLEMENTED 
MISCREG_UNVERIFIABLE 
MISCREG_WARN_NOT_FAIL 
MISCREG_MUTEX 
MISCREG_BANKED 
MISCREG_BANKED64 
MISCREG_BANKED_CHILD 
MISCREG_USR_NS_RD 
MISCREG_USR_NS_WR 
MISCREG_USR_S_RD 
MISCREG_USR_S_WR 
MISCREG_PRI_NS_RD 
MISCREG_PRI_NS_WR 
MISCREG_PRI_S_RD 
MISCREG_PRI_S_WR 
MISCREG_HYP_RD 
MISCREG_HYP_WR 
MISCREG_HYP_E2H_RD 
MISCREG_HYP_E2H_WR 
MISCREG_MON_NS0_RD 
MISCREG_MON_NS0_WR 
MISCREG_MON_NS1_RD 
MISCREG_MON_NS1_WR 
MISCREG_MON_E2H_RD 
MISCREG_MON_E2H_WR 
NUM_MISCREG_INFOS 

Definition at line 1091 of file miscregs.hh.

◆ OperatingMode

Enumerator
MODE_EL0T 
MODE_EL1T 
MODE_EL1H 
MODE_EL2T 
MODE_EL2H 
MODE_EL3T 
MODE_EL3H 
MODE_USER 
MODE_FIQ 
MODE_IRQ 
MODE_SVC 
MODE_MON 
MODE_ABORT 
MODE_HYP 
MODE_UNDEFINED 
MODE_SYSTEM 
MODE_MAXMODE 

Definition at line 628 of file types.hh.

◆ RoundMode

Enumerator
RND_ZERO 
RND_DOWN 
RND_UP 
RND_NEAREST 

Definition at line 614 of file types.hh.

◆ SvePredType

enum ArmISA::SvePredType
strong
Enumerator
NONE 
MERGE 
ZERO 
SELECT 

Definition at line 45 of file sve.hh.

◆ VfpMicroMode

Enumerator
VfpNotAMicroop 
VfpMicroop 
VfpFirstMicroop 
VfpLastMicroop 

Definition at line 51 of file vfp.hh.

◆ VfpRoundingMode

Enumerator
VfpRoundNearest 
VfpRoundUpward 
VfpRoundDown 
VfpRoundZero 
VfpRoundAway 

Definition at line 100 of file vfp.hh.

Function Documentation

◆ AArch32isUndefinedGenericTimer()

bool ArmISA::AArch32isUndefinedGenericTimer ( MiscRegIndex  reg,
ThreadContext tc 
)

◆ AArch64AArch32SystemAccessTrap()

Fault ArmISA::AArch64AArch32SystemAccessTrap ( const MiscRegIndex  miscReg,
ExtMachInst  machInst,
ThreadContext tc,
uint32_t  imm,
ExceptionClass  ec 
)

◆ aarch64SysRegReadOnly()

bool ArmISA::aarch64SysRegReadOnly ( MiscRegIndex  miscReg)

◆ add128()

static void ArmISA::add128 ( uint64_t *  x0,
uint64_t *  x1,
uint64_t  a0,
uint64_t  a1,
uint64_t  b0,
uint64_t  b1 
)
inlinestatic

Definition at line 194 of file fplib.cc.

References MipsISA::a0, a1, QARMA::b0, and QARMA::b1.

Referenced by fp64_muladd().

◆ addPAC()

uint64_t ArmISA::addPAC ( ThreadContext tc,
ExceptionLevel  el,
uint64_t  ptr,
uint64_t  modifier,
uint64_t  k1,
uint64_t  k0,
bool  data 
)

◆ addPACDA()

Fault ArmISA::addPACDA ( ThreadContext tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

◆ addPACDB()

Fault ArmISA::addPACDB ( ThreadContext tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

◆ addPACGA()

Fault ArmISA::addPACGA ( ThreadContext tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

◆ addPACIA()

Fault ArmISA::addPACIA ( ThreadContext tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

◆ addPACIB()

Fault ArmISA::addPACIB ( ThreadContext tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

◆ advancePC()

void ArmISA::advancePC ( PCState &  pc,
const StaticInstPtr inst 
)
inline

◆ auth()

uint64_t ArmISA::auth ( ThreadContext tc,
ExceptionLevel  el,
uint64_t  ptr,
uint64_t  modifier,
uint64_t  k1,
uint64_t  K0,
bool  data,
uint8_t  errorcode 
)

◆ authDA()

Fault ArmISA::authDA ( ThreadContext tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

◆ authDB()

Fault ArmISA::authDB ( ThreadContext tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

◆ authIA()

Fault ArmISA::authIA ( ThreadContext tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

◆ authIB()

Fault ArmISA::authIB ( ThreadContext tc,
uint64_t  X,
uint64_t  Y,
uint64_t *  out 
)

◆ badMode()

bool ArmISA::badMode ( ThreadContext tc,
OperatingMode  mode 
)

badMode is checking if the execution mode provided as an argument is valid and implemented.

Parameters
tcThreadContext
modeOperatingMode to check
Returns
false if mode is valid and implemented, true otherwise

Definition at line 507 of file utility.cc.

References ArmSystem::haveEL(), mode, opModeToEL(), and unknownMode().

Referenced by ArmISA::ArmStaticInst::cpsrWriteByInstr().

◆ badMode32()

bool ArmISA::badMode32 ( ThreadContext tc,
OperatingMode  mode 
)

badMode is checking if the execution mode provided as an argument is valid and implemented for AArch32

Parameters
tcThreadContext
modeOperatingMode to check
Returns
false if mode is valid and implemented, true otherwise

Definition at line 501 of file utility.cc.

References ArmSystem::haveEL(), mode, opModeToEL(), and unknownMode32().

◆ bitsToFp() [1/2]

static double ArmISA::bitsToFp ( uint64_t  bits,
double  junk 
)
inlinestatic

Definition at line 190 of file vfp.hh.

References bits(), fp, and X86ISA::val.

◆ bitsToFp() [2/2]

static float ArmISA::bitsToFp ( uint64_t  bits,
float  junk 
)
inlinestatic

◆ BitUnion32()

ArmISA::BitUnion32 ( CPSR  )

◆ BitUnion64()

ArmISA::BitUnion64 ( CNTKCTL  )

◆ BitUnion8() [1/2]

ArmISA::BitUnion8 ( ITSTATE  )

◆ BitUnion8() [2/2]

ArmISA::BitUnion8 ( OperatingMode64  )

◆ buildRetPC()

PCState ArmISA::buildRetPC ( const PCState &  curPC,
const PCState &  callPC 
)
inline

Definition at line 59 of file utility.hh.

Referenced by BPredUnit::predict().

◆ byteOrder()

ByteOrder ArmISA::byteOrder ( const ThreadContext tc)
inline

◆ calculateBottomPACBit()

int ArmISA::calculateBottomPACBit ( ThreadContext tc,
ExceptionLevel  el,
bool  top_bit 
)

◆ calculateTBI()

bool ArmISA::calculateTBI ( ThreadContext tc,
ExceptionLevel  el,
uint64_t  ptr,
bool  data 
)

◆ canReadAArch64SysReg()

bool ArmISA::canReadAArch64SysReg ( MiscRegIndex  reg,
HCR  hcr,
SCR  scr,
CPSR  cpsr,
ThreadContext tc 
)

◆ canReadCoprocReg()

std::tuple< bool, bool > ArmISA::canReadCoprocReg ( MiscRegIndex  reg,
SCR  scr,
CPSR  cpsr,
ThreadContext tc 
)

Check for permission to read coprocessor registers.

Checks whether an instruction at the current program mode has permissions to read the coprocessor registers. This function returns whether the check is undefined and if not whether the read access is permitted.

Parameters
themisc reg indicating the coprocessor
theSCR
theCPSR
thethread context on the core
Returns
a tuple of booleans: can_read, undefined

Definition at line 1207 of file miscregs.cc.

References AArch32isUndefinedGenericTimer(), MISCREG_BANKED, MISCREG_CNTFRQ, MISCREG_CNTVOFF, MISCREG_HYP_RD, MISCREG_MON_NS0_RD, MISCREG_MON_NS1_RD, MISCREG_PRI_NS_RD, MISCREG_PRI_S_RD, MISCREG_USR_NS_RD, MISCREG_USR_S_RD, miscRegInfo, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, and X86ISA::reg.

◆ canWriteAArch64SysReg()

bool ArmISA::canWriteAArch64SysReg ( MiscRegIndex  reg,
HCR  hcr,
SCR  scr,
CPSR  cpsr,
ThreadContext tc 
)

◆ canWriteCoprocReg()

std::tuple< bool, bool > ArmISA::canWriteCoprocReg ( MiscRegIndex  reg,
SCR  scr,
CPSR  cpsr,
ThreadContext tc 
)

Check for permission to write coprocessor registers.

Checks whether an instruction at the current program mode has permissions to write the coprocessor registers. This function returns whether the check is undefined and if not whether the write access is permitted.

Parameters
themisc reg indicating the coprocessor
theSCR
theCPSR
thethread context on the core
Returns
a tuple of booleans: can_write, undefined

Definition at line 1253 of file miscregs.cc.

References AArch32isUndefinedGenericTimer(), MISCREG_BANKED, MISCREG_CNTFRQ, MISCREG_CNTVOFF, MISCREG_HYP_WR, MISCREG_MON_NS0_WR, MISCREG_MON_NS1_WR, MISCREG_PRI_NS_WR, MISCREG_PRI_S_WR, MISCREG_USR_NS_WR, MISCREG_USR_S_WR, miscRegInfo, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, and X86ISA::reg.

◆ cmp128()

static int ArmISA::cmp128 ( uint64_t  a0,
uint64_t  a1,
uint64_t  b0,
uint64_t  b1 
)
inlinestatic

Definition at line 210 of file fplib.cc.

References QARMA::b0, and QARMA::b1.

Referenced by fp64_div(), fp64_muladd(), and fp64_sqrt().

◆ computeAddrTop()

int ArmISA::computeAddrTop ( ThreadContext tc,
bool  selbit,
bool  isInstr,
TCR  tcr,
ExceptionLevel  el 
)

◆ condGenericTimerCommonEL0SystemAccessTrapEL2()

bool ArmISA::condGenericTimerCommonEL0SystemAccessTrapEL2 ( const MiscRegIndex  miscReg,
ThreadContext tc 
)

◆ condGenericTimerCommonEL1SystemAccessTrapEL2()

bool ArmISA::condGenericTimerCommonEL1SystemAccessTrapEL2 ( const MiscRegIndex  miscReg,
ThreadContext tc 
)

◆ condGenericTimerPhysEL1SystemAccessTrapEL2()

bool ArmISA::condGenericTimerPhysEL1SystemAccessTrapEL2 ( const MiscRegIndex  miscReg,
ThreadContext tc 
)

◆ condGenericTimerPhysHypTrap()

bool ArmISA::condGenericTimerPhysHypTrap ( const MiscRegIndex  miscReg,
ThreadContext tc 
)

◆ condGenericTimerSystemAccessTrapEL1()

bool ArmISA::condGenericTimerSystemAccessTrapEL1 ( const MiscRegIndex  miscReg,
ThreadContext tc 
)

◆ copyMiscRegs()

static void ArmISA::copyMiscRegs ( ThreadContext src,
ThreadContext dest 
)
inlinestatic

Definition at line 98 of file utility.hh.

References panic.

◆ copyRegs()

void ArmISA::copyRegs ( ThreadContext src,
ThreadContext dest 
)

◆ copyVecRegs()

static void ArmISA::copyVecRegs ( ThreadContext src,
ThreadContext dest 
)
static

◆ currEL() [1/2]

static ExceptionLevel ArmISA::currEL ( const ThreadContext tc)
inlinestatic

Definition at line 143 of file utility.hh.

References currOpMode(), and opModeToEL().

Referenced by AArch32isUndefinedGenericTimer(), AArch64AArch32SystemAccessTrap(), addPACDA(), addPACDB(), addPACGA(), addPACIA(), addPACIB(), authDA(), authDB(), authIA(), authIB(), canReadAArch64SysReg(), canWriteAArch64SysReg(), ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), ArmISA::ArmStaticInst::checkFPAdvSIMDEnabled64(), ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64(), ArmISA::Interrupts::checkInterrupts(), ArmISA::ArmStaticInst::checkSETENDEnabled(), ELStateUsingAArch32K(), ArmISA::Interrupts::getInterrupt(), ArmISA::ArmStaticInst::getPSTATEFromPSR(), illegalExceptionReturn(), isAArch64AArch32SystemAccessTrapEL1(), isAArch64AArch32SystemAccessTrapEL2(), isBigEndian64(), ArmISA::SelfDebug::isDebugEnabled(), ArmISA::PMU::CounterState::isFiltered(), isGenericTimerHypTrap(), isGenericTimerSystemAccessTrapEL2(), isGenericTimerSystemAccessTrapEL3(), isSecure(), isUnpriviledgeAccess(), readMPIDR(), ArmISA::ISA::redirectRegVHE(), ArmISA::SupervisorTrap::routeToHyp(), ArmISA::PrefetchAbort::routeToHyp(), ArmISA::SPAlignmentFault::routeToHyp(), ArmISA::SelfDebug::setAArch32(), GenericTimer::setMiscReg(), SPAlignmentCheckEnabled(), stripPAC(), ArmISA::Interrupts::takeInt(), ArmISA::SelfDebug::testBreakPoints(), ArmISA::BrkPoint::testContextMatch(), ArmISA::SelfDebug::testVectorCatch(), ArmISA::BrkPoint::testVMIDMatch(), ArmISA::SelfDebug::testWatchPoints(), FastModel::CortexA76TC::translateAddress(), ArmISA::TLB::translateMmuOff(), ArmISA::TLB::tranTypeEL(), trapPACUse(), and ArmISA::ArmStaticInst::trapWFx().

◆ currEL() [2/2]

ExceptionLevel ArmISA::currEL ( CPSR  cpsr)
inline

Definition at line 149 of file utility.hh.

References opModeToEL().

◆ currOpMode()

static OperatingMode ArmISA::currOpMode ( const ThreadContext tc)
inlinestatic

Definition at line 136 of file utility.hh.

References MISCREG_CPSR, and ThreadContext::readMiscRegNoEffect().

Referenced by currEL().

◆ debugTargetFrom()

ExceptionLevel ArmISA::debugTargetFrom ( ThreadContext tc,
bool  secure 
)

◆ decode_fp_data_type()

static FpDataType ArmISA::decode_fp_data_type ( uint8_t  encoding)
inlinestatic

Definition at line 195 of file pred_inst.hh.

References encoding, Fp16, Fp32, Fp64, and panic.

◆ decodeAArch64SysReg()

MiscRegIndex ArmISA::decodeAArch64SysReg ( unsigned  op0,
unsigned  op1,
unsigned  crn,
unsigned  crm,
unsigned  op2 
)

Definition at line 1442 of file miscregs.cc.

References M5_FALLTHROUGH, MISCREG_ACTLR_EL1, MISCREG_ACTLR_EL2, MISCREG_ACTLR_EL3, MISCREG_AFSR0_EL1, MISCREG_AFSR0_EL12, MISCREG_AFSR0_EL2, MISCREG_AFSR0_EL3, MISCREG_AFSR1_EL1, MISCREG_AFSR1_EL12, MISCREG_AFSR1_EL2, MISCREG_AFSR1_EL3, MISCREG_AIDR_EL1, MISCREG_AMAIR_EL1, MISCREG_AMAIR_EL12, MISCREG_AMAIR_EL2, MISCREG_AMAIR_EL3, MISCREG_APDAKeyHi_EL1, MISCREG_APDAKeyLo_EL1, MISCREG_APDBKeyHi_EL1, MISCREG_APDBKeyLo_EL1, MISCREG_APGAKeyHi_EL1, MISCREG_APGAKeyLo_EL1, MISCREG_APIAKeyHi_EL1, MISCREG_APIAKeyLo_EL1, MISCREG_APIBKeyHi_EL1, MISCREG_APIBKeyLo_EL1, MISCREG_AT_S12E0R_Xt, MISCREG_AT_S12E0W_Xt, MISCREG_AT_S12E1R_Xt, MISCREG_AT_S12E1W_Xt, MISCREG_AT_S1E0R_Xt, MISCREG_AT_S1E0W_Xt, MISCREG_AT_S1E1R_Xt, MISCREG_AT_S1E1W_Xt, MISCREG_AT_S1E2R_Xt, MISCREG_AT_S1E2W_Xt, MISCREG_AT_S1E3R_Xt, MISCREG_AT_S1E3W_Xt, MISCREG_CBAR_EL1, MISCREG_CCSIDR_EL1, MISCREG_CLIDR_EL1, MISCREG_CNTFRQ_EL0, MISCREG_CNTHCTL_EL2, MISCREG_CNTHP_CTL_EL2, MISCREG_CNTHP_CVAL_EL2, MISCREG_CNTHP_TVAL_EL2, MISCREG_CNTHV_CTL_EL2, MISCREG_CNTHV_CVAL_EL2, MISCREG_CNTHV_TVAL_EL2, MISCREG_CNTKCTL_EL1, MISCREG_CNTKCTL_EL12, MISCREG_CNTP_CTL_EL0, MISCREG_CNTP_CTL_EL02, MISCREG_CNTP_CVAL_EL0, MISCREG_CNTP_CVAL_EL02, MISCREG_CNTP_TVAL_EL0, MISCREG_CNTP_TVAL_EL02, MISCREG_CNTPCT_EL0, MISCREG_CNTPS_CTL_EL1, MISCREG_CNTPS_CVAL_EL1, MISCREG_CNTPS_TVAL_EL1, MISCREG_CNTV_CTL_EL0, MISCREG_CNTV_CTL_EL02, MISCREG_CNTV_CVAL_EL0, MISCREG_CNTV_CVAL_EL02, MISCREG_CNTV_TVAL_EL0, MISCREG_CNTV_TVAL_EL02, MISCREG_CNTVCT_EL0, MISCREG_CNTVOFF_EL2, MISCREG_CONTEXTIDR_EL1, MISCREG_CONTEXTIDR_EL12, MISCREG_CONTEXTIDR_EL2, MISCREG_CPACR_EL1, MISCREG_CPACR_EL12, MISCREG_CPTR_EL2, MISCREG_CPTR_EL3, MISCREG_CPUACTLR_EL1, MISCREG_CPUECTLR_EL1, MISCREG_CPUMERRSR_EL1, MISCREG_CSSELR_EL1, MISCREG_CTR_EL0, MISCREG_CURRENTEL, MISCREG_DACR32_EL2, MISCREG_DAIF, MISCREG_DBGAUTHSTATUS_EL1, MISCREG_DBGBCR0_EL1, MISCREG_DBGBCR10_EL1, MISCREG_DBGBCR11_EL1, MISCREG_DBGBCR12_EL1, MISCREG_DBGBCR13_EL1, MISCREG_DBGBCR14_EL1, MISCREG_DBGBCR15_EL1, MISCREG_DBGBCR1_EL1, MISCREG_DBGBCR2_EL1, MISCREG_DBGBCR3_EL1, MISCREG_DBGBCR4_EL1, MISCREG_DBGBCR5_EL1, MISCREG_DBGBCR6_EL1, MISCREG_DBGBCR7_EL1, MISCREG_DBGBCR8_EL1, MISCREG_DBGBCR9_EL1, MISCREG_DBGBVR0_EL1, MISCREG_DBGBVR10_EL1, MISCREG_DBGBVR11_EL1, MISCREG_DBGBVR12_EL1, MISCREG_DBGBVR13_EL1, MISCREG_DBGBVR14_EL1, MISCREG_DBGBVR15_EL1, MISCREG_DBGBVR1_EL1, MISCREG_DBGBVR2_EL1, MISCREG_DBGBVR3_EL1, MISCREG_DBGBVR4_EL1, MISCREG_DBGBVR5_EL1, MISCREG_DBGBVR6_EL1, MISCREG_DBGBVR7_EL1, MISCREG_DBGBVR8_EL1, MISCREG_DBGBVR9_EL1, MISCREG_DBGCLAIMCLR_EL1, MISCREG_DBGCLAIMSET_EL1, MISCREG_DBGPRCR_EL1, MISCREG_DBGVCR32_EL2, MISCREG_DBGWCR0_EL1, MISCREG_DBGWCR10_EL1, MISCREG_DBGWCR11_EL1, MISCREG_DBGWCR12_EL1, MISCREG_DBGWCR13_EL1, MISCREG_DBGWCR14_EL1, MISCREG_DBGWCR15_EL1, MISCREG_DBGWCR1_EL1, MISCREG_DBGWCR2_EL1, MISCREG_DBGWCR3_EL1, MISCREG_DBGWCR4_EL1, MISCREG_DBGWCR5_EL1, MISCREG_DBGWCR6_EL1, MISCREG_DBGWCR7_EL1, MISCREG_DBGWCR8_EL1, MISCREG_DBGWCR9_EL1, MISCREG_DBGWVR0_EL1, MISCREG_DBGWVR10_EL1, MISCREG_DBGWVR11_EL1, MISCREG_DBGWVR12_EL1, MISCREG_DBGWVR13_EL1, MISCREG_DBGWVR14_EL1, MISCREG_DBGWVR15_EL1, MISCREG_DBGWVR1_EL1, MISCREG_DBGWVR2_EL1, MISCREG_DBGWVR3_EL1, MISCREG_DBGWVR4_EL1, MISCREG_DBGWVR5_EL1, MISCREG_DBGWVR6_EL1, MISCREG_DBGWVR7_EL1, MISCREG_DBGWVR8_EL1, MISCREG_DBGWVR9_EL1, MISCREG_DC_CISW_Xt, MISCREG_DC_CIVAC_Xt, MISCREG_DC_CSW_Xt, MISCREG_DC_CVAC_Xt, MISCREG_DC_CVAU_Xt, MISCREG_DC_ISW_Xt, MISCREG_DC_IVAC_Xt, MISCREG_DC_ZVA_Xt, MISCREG_DCZID_EL0, MISCREG_DISR_EL1, MISCREG_DL1DATA0_EL1, MISCREG_DL1DATA1_EL1, MISCREG_DL1DATA2_EL1, MISCREG_DL1DATA3_EL1, MISCREG_DL1DATA4_EL1, MISCREG_DLR_EL0, MISCREG_DSPSR_EL0, MISCREG_ELR_EL1, MISCREG_ELR_EL12, MISCREG_ELR_EL2, MISCREG_ELR_EL3, MISCREG_ERRIDR_EL1, MISCREG_ERRSELR_EL1, MISCREG_ERXADDR_EL1, MISCREG_ERXCTLR_EL1, MISCREG_ERXFR_EL1, MISCREG_ERXMISC0_EL1, MISCREG_ERXMISC1_EL1, MISCREG_ERXSTATUS_EL1, MISCREG_ESR_EL1, MISCREG_ESR_EL12, MISCREG_ESR_EL2, MISCREG_ESR_EL3, MISCREG_FAR_EL1, MISCREG_FAR_EL12, MISCREG_FAR_EL2, MISCREG_FAR_EL3, MISCREG_FPCR, MISCREG_FPEXC32_EL2, MISCREG_FPSR, MISCREG_HACR_EL2, MISCREG_HCR_EL2, MISCREG_HPFAR_EL2, MISCREG_HSTR_EL2, MISCREG_IC_IALLU, MISCREG_IC_IALLUIS, MISCREG_IC_IVAU_Xt, MISCREG_ICC_AP0R0_EL1, MISCREG_ICC_AP0R1_EL1, MISCREG_ICC_AP0R2_EL1, MISCREG_ICC_AP0R3_EL1, MISCREG_ICC_AP1R0_EL1, MISCREG_ICC_AP1R1_EL1, MISCREG_ICC_AP1R2_EL1, MISCREG_ICC_AP1R3_EL1, MISCREG_ICC_ASGI1R_EL1, MISCREG_ICC_BPR0_EL1, MISCREG_ICC_BPR1_EL1, MISCREG_ICC_CTLR_EL1, MISCREG_ICC_CTLR_EL3, MISCREG_ICC_DIR_EL1, MISCREG_ICC_EOIR0_EL1, MISCREG_ICC_EOIR1_EL1, MISCREG_ICC_HPPIR0_EL1, MISCREG_ICC_HPPIR1_EL1, MISCREG_ICC_IAR0_EL1, MISCREG_ICC_IAR1_EL1, MISCREG_ICC_IGRPEN0_EL1, MISCREG_ICC_IGRPEN1_EL1, MISCREG_ICC_IGRPEN1_EL3, MISCREG_ICC_PMR_EL1, MISCREG_ICC_RPR_EL1, MISCREG_ICC_SGI0R_EL1, MISCREG_ICC_SGI1R_EL1, MISCREG_ICC_SRE_EL1, MISCREG_ICC_SRE_EL2, MISCREG_ICC_SRE_EL3, MISCREG_ICH_AP0R0_EL2, MISCREG_ICH_AP0R1_EL2, MISCREG_ICH_AP0R2_EL2, MISCREG_ICH_AP0R3_EL2, MISCREG_ICH_AP1R0_EL2, MISCREG_ICH_AP1R1_EL2, MISCREG_ICH_AP1R2_EL2, MISCREG_ICH_AP1R3_EL2, MISCREG_ICH_EISR_EL2, MISCREG_ICH_ELRSR_EL2, MISCREG_ICH_HCR_EL2, MISCREG_ICH_LR0_EL2, MISCREG_ICH_LR10_EL2, MISCREG_ICH_LR11_EL2, MISCREG_ICH_LR12_EL2, MISCREG_ICH_LR13_EL2, MISCREG_ICH_LR14_EL2, MISCREG_ICH_LR15_EL2, MISCREG_ICH_LR1_EL2, MISCREG_ICH_LR2_EL2, MISCREG_ICH_LR3_EL2, MISCREG_ICH_LR4_EL2, MISCREG_ICH_LR5_EL2, MISCREG_ICH_LR6_EL2, MISCREG_ICH_LR7_EL2, MISCREG_ICH_LR8_EL2, MISCREG_ICH_LR9_EL2, MISCREG_ICH_MISR_EL2, MISCREG_ICH_VMCR_EL2, MISCREG_ICH_VTR_EL2, MISCREG_ID_AA64AFR0_EL1, MISCREG_ID_AA64AFR1_EL1, MISCREG_ID_AA64DFR0_EL1, MISCREG_ID_AA64DFR1_EL1, MISCREG_ID_AA64ISAR0_EL1, MISCREG_ID_AA64ISAR1_EL1, MISCREG_ID_AA64MMFR0_EL1, MISCREG_ID_AA64MMFR1_EL1, MISCREG_ID_AA64MMFR2_EL1, MISCREG_ID_AA64PFR0_EL1, MISCREG_ID_AA64PFR1_EL1, MISCREG_ID_AA64ZFR0_EL1, MISCREG_ID_AFR0_EL1, MISCREG_ID_DFR0_EL1, MISCREG_ID_ISAR0_EL1, MISCREG_ID_ISAR1_EL1, MISCREG_ID_ISAR2_EL1, MISCREG_ID_ISAR3_EL1, MISCREG_ID_ISAR4_EL1, MISCREG_ID_ISAR5_EL1, MISCREG_ID_MMFR0_EL1, MISCREG_ID_MMFR1_EL1, MISCREG_ID_MMFR2_EL1, MISCREG_ID_MMFR3_EL1, MISCREG_ID_PFR0_EL1, MISCREG_ID_PFR1_EL1, MISCREG_IFSR32_EL2, MISCREG_IL1DATA0_EL1, MISCREG_IL1DATA1_EL1, MISCREG_IL1DATA2_EL1, MISCREG_IL1DATA3_EL1, MISCREG_IMPDEF_UNIMPL, MISCREG_ISR_EL1, MISCREG_L2ACTLR_EL1, MISCREG_L2CTLR_EL1, MISCREG_L2ECTLR_EL1, MISCREG_L2MERRSR_EL1, MISCREG_MAIR_EL1, MISCREG_MAIR_EL12, MISCREG_MAIR_EL2, MISCREG_MAIR_EL3, MISCREG_MDCCINT_EL1, MISCREG_MDCCSR_EL0, MISCREG_MDCR_EL2, MISCREG_MDCR_EL3, MISCREG_MDDTR_EL0, MISCREG_MDDTRRX_EL0, MISCREG_MDRAR_EL1, MISCREG_MDSCR_EL1, MISCREG_MIDR_EL1, MISCREG_MPIDR_EL1, MISCREG_MVFR0_EL1, MISCREG_MVFR1_EL1, MISCREG_MVFR2_EL1, MISCREG_NZCV, MISCREG_OSDLR_EL1, MISCREG_OSDTRRX_EL1, MISCREG_OSDTRTX_EL1, MISCREG_OSECCR_EL1, MISCREG_OSLAR_EL1, MISCREG_OSLSR_EL1, MISCREG_PAN, MISCREG_PAR_EL1, MISCREG_PMCCFILTR_EL0, MISCREG_PMCCNTR_EL0, MISCREG_PMCEID0_EL0, MISCREG_PMCEID1_EL0, MISCREG_PMCNTENCLR_EL0, MISCREG_PMCNTENSET_EL0, MISCREG_PMCR_EL0, MISCREG_PMEVCNTR0_EL0, MISCREG_PMEVCNTR1_EL0, MISCREG_PMEVCNTR2_EL0, MISCREG_PMEVCNTR3_EL0, MISCREG_PMEVCNTR4_EL0, MISCREG_PMEVCNTR5_EL0, MISCREG_PMEVTYPER0_EL0, MISCREG_PMEVTYPER1_EL0, MISCREG_PMEVTYPER2_EL0, MISCREG_PMEVTYPER3_EL0, MISCREG_PMEVTYPER4_EL0, MISCREG_PMEVTYPER5_EL0, MISCREG_PMINTENCLR_EL1, MISCREG_PMINTENSET_EL1, MISCREG_PMOVSCLR_EL0, MISCREG_PMOVSSET_EL0, MISCREG_PMSELR_EL0, MISCREG_PMSWINC_EL0, MISCREG_PMUSERENR_EL0, MISCREG_PMXEVCNTR_EL0, MISCREG_PMXEVTYPER_EL0, MISCREG_RAZ, MISCREG_REVIDR_EL1, MISCREG_RMR_EL3, MISCREG_RVBAR_EL1, MISCREG_RVBAR_EL2, MISCREG_RVBAR_EL3, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL12, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, MISCREG_SDER32_EL3, MISCREG_SP_EL0, MISCREG_SP_EL1, MISCREG_SP_EL2, MISCREG_SPSEL, MISCREG_SPSR_ABT_AA64, MISCREG_SPSR_EL1, MISCREG_SPSR_EL12, MISCREG_SPSR_EL2, MISCREG_SPSR_EL3, MISCREG_SPSR_FIQ_AA64, MISCREG_SPSR_IRQ_AA64, MISCREG_SPSR_UND_AA64, MISCREG_TCR_EL1, MISCREG_TCR_EL12, MISCREG_TCR_EL2, MISCREG_TCR_EL3, MISCREG_TEECR32_EL1, MISCREG_TEEHBR32_EL1, MISCREG_TLBI_ALLE1, MISCREG_TLBI_ALLE1IS, MISCREG_TLBI_ALLE2, MISCREG_TLBI_ALLE2IS, MISCREG_TLBI_ALLE3, MISCREG_TLBI_ALLE3IS, MISCREG_TLBI_ASIDE1_Xt, MISCREG_TLBI_ASIDE1IS_Xt, MISCREG_TLBI_IPAS2E1_Xt, MISCREG_TLBI_IPAS2E1IS_Xt, MISCREG_TLBI_IPAS2LE1_Xt, MISCREG_TLBI_IPAS2LE1IS_Xt, MISCREG_TLBI_VAAE1_Xt, MISCREG_TLBI_VAAE1IS_Xt, MISCREG_TLBI_VAALE1_Xt, MISCREG_TLBI_VAALE1IS_Xt, MISCREG_TLBI_VAE1_Xt, MISCREG_TLBI_VAE1IS_Xt, MISCREG_TLBI_VAE2_Xt, MISCREG_TLBI_VAE2IS_Xt, MISCREG_TLBI_VAE3_Xt, MISCREG_TLBI_VAE3IS_Xt, MISCREG_TLBI_VALE1_Xt, MISCREG_TLBI_VALE1IS_Xt, MISCREG_TLBI_VALE2_Xt, MISCREG_TLBI_VALE2IS_Xt, MISCREG_TLBI_VALE3_Xt, MISCREG_TLBI_VALE3IS_Xt, MISCREG_TLBI_VMALLE1, MISCREG_TLBI_VMALLE1IS, MISCREG_TLBI_VMALLS12E1, MISCREG_TLBI_VMALLS12E1IS, MISCREG_TPIDR_EL0, MISCREG_TPIDR_EL1, MISCREG_TPIDR_EL2, MISCREG_TPIDR_EL3, MISCREG_TPIDRRO_EL0, MISCREG_TTBR0_EL1, MISCREG_TTBR0_EL12, MISCREG_TTBR0_EL2, MISCREG_TTBR0_EL3, MISCREG_TTBR1_EL1, MISCREG_TTBR1_EL12, MISCREG_TTBR1_EL2, MISCREG_UNKNOWN, MISCREG_VBAR_EL1, MISCREG_VBAR_EL12, MISCREG_VBAR_EL2, MISCREG_VBAR_EL3, MISCREG_VDISR_EL2, MISCREG_VMPIDR_EL2, MISCREG_VPIDR_EL2, MISCREG_VSESR_EL2, MISCREG_VSTCR_EL2, MISCREG_VSTTBR_EL2, MISCREG_VTCR_EL2, MISCREG_VTTBR_EL2, MISCREG_ZCR_EL1, MISCREG_ZCR_EL12, MISCREG_ZCR_EL2, and MISCREG_ZCR_EL3.

Referenced by ArmV8KvmCPU::dump(), and ArmV8KvmCPU::getSysRegMap().

◆ decodeCP14Reg()

MiscRegIndex ArmISA::decodeCP14Reg ( unsigned  crn,
unsigned  opc1,
unsigned  crm,
unsigned  opc2 
)

Definition at line 51 of file miscregs.cc.

References MISCREG_CP14_UNIMPL, MISCREG_DBGBCR0, MISCREG_DBGBCR1, MISCREG_DBGBCR10, MISCREG_DBGBCR11, MISCREG_DBGBCR12, MISCREG_DBGBCR13, MISCREG_DBGBCR14, MISCREG_DBGBCR15, MISCREG_DBGBCR2, MISCREG_DBGBCR3, MISCREG_DBGBCR4, MISCREG_DBGBCR5, MISCREG_DBGBCR6, MISCREG_DBGBCR7, MISCREG_DBGBCR8, MISCREG_DBGBCR9, MISCREG_DBGBVR0, MISCREG_DBGBVR1, MISCREG_DBGBVR10, MISCREG_DBGBVR11, MISCREG_DBGBVR12, MISCREG_DBGBVR13, MISCREG_DBGBVR14, MISCREG_DBGBVR15, MISCREG_DBGBVR2, MISCREG_DBGBVR3, MISCREG_DBGBVR4, MISCREG_DBGBVR5, MISCREG_DBGBVR6, MISCREG_DBGBVR7, MISCREG_DBGBVR8, MISCREG_DBGBVR9, MISCREG_DBGBXVR0, MISCREG_DBGBXVR1, MISCREG_DBGBXVR10, MISCREG_DBGBXVR11, MISCREG_DBGBXVR12, MISCREG_DBGBXVR13, MISCREG_DBGBXVR14, MISCREG_DBGBXVR15, MISCREG_DBGBXVR2, MISCREG_DBGBXVR3, MISCREG_DBGBXVR4, MISCREG_DBGBXVR5, MISCREG_DBGBXVR6, MISCREG_DBGBXVR7, MISCREG_DBGBXVR8, MISCREG_DBGBXVR9, MISCREG_DBGDIDR, MISCREG_DBGDSCRext, MISCREG_DBGDSCRint, MISCREG_DBGDTRRXext, MISCREG_DBGDTRTXext, MISCREG_DBGOSDLR, MISCREG_DBGOSECCR, MISCREG_DBGOSLAR, MISCREG_DBGOSLSR, MISCREG_DBGPRCR, MISCREG_DBGVCR, MISCREG_DBGWCR0, MISCREG_DBGWCR1, MISCREG_DBGWCR10, MISCREG_DBGWCR11, MISCREG_DBGWCR12, MISCREG_DBGWCR13, MISCREG_DBGWCR14, MISCREG_DBGWCR15, MISCREG_DBGWCR2, MISCREG_DBGWCR3, MISCREG_DBGWCR4, MISCREG_DBGWCR5, MISCREG_DBGWCR6, MISCREG_DBGWCR7, MISCREG_DBGWCR8, MISCREG_DBGWCR9, MISCREG_DBGWVR0, MISCREG_DBGWVR1, MISCREG_DBGWVR10, MISCREG_DBGWVR11, MISCREG_DBGWVR12, MISCREG_DBGWVR13, MISCREG_DBGWVR14, MISCREG_DBGWVR15, MISCREG_DBGWVR2, MISCREG_DBGWVR3, MISCREG_DBGWVR4, MISCREG_DBGWVR5, MISCREG_DBGWVR6, MISCREG_DBGWVR7, MISCREG_DBGWVR8, MISCREG_DBGWVR9, MISCREG_JIDR, MISCREG_JMCR, MISCREG_JOSCR, MISCREG_TEEHBR, opc2, and warn.

Referenced by ArmKvmCPU::decodeCoProcReg().

◆ decodeCP15Reg()

MiscRegIndex ArmISA::decodeCP15Reg ( unsigned  crn,
unsigned  opc1,
unsigned  crm,
unsigned  opc2 
)

Definition at line 339 of file miscregs.cc.

References MISCREG_ACTLR, MISCREG_ADFSR, MISCREG_AIDR, MISCREG_AIFSR, MISCREG_AMAIR0, MISCREG_AMAIR1, MISCREG_ATS12NSOPR, MISCREG_ATS12NSOPW, MISCREG_ATS12NSOUR, MISCREG_ATS12NSOUW, MISCREG_ATS1CPR, MISCREG_ATS1CPW, MISCREG_ATS1CUR, MISCREG_ATS1CUW, MISCREG_ATS1HR, MISCREG_ATS1HW, MISCREG_BPIALL, MISCREG_BPIALLIS, MISCREG_BPIMVA, MISCREG_CCSIDR, MISCREG_CLIDR, MISCREG_CNTFRQ, MISCREG_CNTHCTL, MISCREG_CNTHP_CTL, MISCREG_CNTHP_TVAL, MISCREG_CNTKCTL, MISCREG_CNTP_CTL, MISCREG_CNTP_TVAL, MISCREG_CNTV_CTL, MISCREG_CNTV_TVAL, MISCREG_CONTEXTIDR, MISCREG_CP15_UNIMPL, MISCREG_CP15DMB, MISCREG_CP15DSB, MISCREG_CP15ISB, MISCREG_CPACR, MISCREG_CSSELR, MISCREG_CTR, MISCREG_DACR, MISCREG_DBGDEVID0, MISCREG_DCCIMVAC, MISCREG_DCCISW, MISCREG_DCCMVAC, MISCREG_DCCMVAU, MISCREG_DCCSW, MISCREG_DCIMVAC, MISCREG_DCISW, MISCREG_DFAR, MISCREG_DFSR, MISCREG_DTLBIALL, MISCREG_DTLBIASID, MISCREG_DTLBIMVA, MISCREG_FCSEIDR, MISCREG_HACR, MISCREG_HACTLR, MISCREG_HADFSR, MISCREG_HAIFSR, MISCREG_HAMAIR0, MISCREG_HAMAIR1, MISCREG_HCPTR, MISCREG_HCR, MISCREG_HCR2, MISCREG_HDCR, MISCREG_HDFAR, MISCREG_HIFAR, MISCREG_HMAIR0, MISCREG_HMAIR1, MISCREG_HPFAR, MISCREG_HSCTLR, MISCREG_HSR, MISCREG_HSTR, MISCREG_HTCR, MISCREG_HTPIDR, MISCREG_HVBAR, MISCREG_ICC_AP0R0, MISCREG_ICC_AP0R1, MISCREG_ICC_AP0R2, MISCREG_ICC_AP0R3, MISCREG_ICC_AP1R0, MISCREG_ICC_AP1R1, MISCREG_ICC_AP1R2, MISCREG_ICC_AP1R3, MISCREG_ICC_BPR0, MISCREG_ICC_BPR1, MISCREG_ICC_CTLR, MISCREG_ICC_DIR, MISCREG_ICC_EOIR0, MISCREG_ICC_EOIR1, MISCREG_ICC_HPPIR0, MISCREG_ICC_HPPIR1, MISCREG_ICC_HSRE, MISCREG_ICC_IAR0, MISCREG_ICC_IAR1, MISCREG_ICC_IGRPEN0, MISCREG_ICC_IGRPEN1, MISCREG_ICC_MCTLR, MISCREG_ICC_MGRPEN1, MISCREG_ICC_MSRE, MISCREG_ICC_PMR, MISCREG_ICC_RPR, MISCREG_ICC_SRE, MISCREG_ICH_AP0R0, MISCREG_ICH_AP0R1, MISCREG_ICH_AP0R2, MISCREG_ICH_AP0R3, MISCREG_ICH_AP1R0, MISCREG_ICH_AP1R1, MISCREG_ICH_AP1R2, MISCREG_ICH_AP1R3, MISCREG_ICH_EISR, MISCREG_ICH_ELRSR, MISCREG_ICH_HCR, MISCREG_ICH_LR0, MISCREG_ICH_LR1, MISCREG_ICH_LR10, MISCREG_ICH_LR11, MISCREG_ICH_LR12, MISCREG_ICH_LR13, MISCREG_ICH_LR14, MISCREG_ICH_LR15, MISCREG_ICH_LR2, MISCREG_ICH_LR3, MISCREG_ICH_LR4, MISCREG_ICH_LR5, MISCREG_ICH_LR6, MISCREG_ICH_LR7, MISCREG_ICH_LR8, MISCREG_ICH_LR9, MISCREG_ICH_LRC0, MISCREG_ICH_LRC1, MISCREG_ICH_LRC10, MISCREG_ICH_LRC11, MISCREG_ICH_LRC12, MISCREG_ICH_LRC13, MISCREG_ICH_LRC14, MISCREG_ICH_LRC15, MISCREG_ICH_LRC2, MISCREG_ICH_LRC3, MISCREG_ICH_LRC4, MISCREG_ICH_LRC5, MISCREG_ICH_LRC6, MISCREG_ICH_LRC7, MISCREG_ICH_LRC8, MISCREG_ICH_LRC9, MISCREG_ICH_MISR, MISCREG_ICH_VMCR, MISCREG_ICH_VTR, MISCREG_ICIALLU, MISCREG_ICIALLUIS, MISCREG_ICIMVAU, MISCREG_ID_AFR0, MISCREG_ID_DFR0, MISCREG_ID_ISAR0, MISCREG_ID_ISAR1, MISCREG_ID_ISAR2, MISCREG_ID_ISAR3, MISCREG_ID_ISAR4, MISCREG_ID_ISAR5, MISCREG_ID_MMFR0, MISCREG_ID_MMFR1, MISCREG_ID_MMFR2, MISCREG_ID_MMFR3, MISCREG_ID_PFR0, MISCREG_ID_PFR1, MISCREG_IFAR, MISCREG_IFSR, MISCREG_IMPDEF_UNIMPL, MISCREG_ISR, MISCREG_ITLBIALL, MISCREG_ITLBIASID, MISCREG_ITLBIMVA, MISCREG_L2CTLR, MISCREG_L2ECTLR, MISCREG_MIDR, MISCREG_MPIDR, MISCREG_MVBAR, MISCREG_NMRR_MAIR1, MISCREG_NOP, MISCREG_NSACR, MISCREG_PAR, MISCREG_PMCCNTR, MISCREG_PMCEID0, MISCREG_PMCEID1, MISCREG_PMCNTENCLR, MISCREG_PMCNTENSET, MISCREG_PMCR, MISCREG_PMINTENCLR, MISCREG_PMINTENSET, MISCREG_PMOVSR, MISCREG_PMOVSSET, MISCREG_PMSELR, MISCREG_PMSWINC, MISCREG_PMUSERENR, MISCREG_PMXEVCNTR, MISCREG_PMXEVTYPER_PMCCFILTR, MISCREG_PRRR_MAIR0, MISCREG_RAZ, MISCREG_REVIDR, MISCREG_SCR, MISCREG_SCTLR, MISCREG_SDCR, MISCREG_SDER, MISCREG_TCMTR, MISCREG_TLBIALL, MISCREG_TLBIALLH, MISCREG_TLBIALLHIS, MISCREG_TLBIALLIS, MISCREG_TLBIALLNSNH, MISCREG_TLBIALLNSNHIS, MISCREG_TLBIASID, MISCREG_TLBIASIDIS, MISCREG_TLBIIPAS2, MISCREG_TLBIIPAS2IS, MISCREG_TLBIIPAS2L, MISCREG_TLBIIPAS2LIS, MISCREG_TLBIMVA, MISCREG_TLBIMVAA, MISCREG_TLBIMVAAIS, MISCREG_TLBIMVAAL, MISCREG_TLBIMVAALIS, MISCREG_TLBIMVAH, MISCREG_TLBIMVAHIS, MISCREG_TLBIMVAIS, MISCREG_TLBIMVAL, MISCREG_TLBIMVALH, MISCREG_TLBIMVALHIS, MISCREG_TLBIMVALIS, MISCREG_TLBTR, MISCREG_TPIDRPRW, MISCREG_TPIDRURO, MISCREG_TPIDRURW, MISCREG_TTBCR, MISCREG_TTBR0, MISCREG_TTBR1, MISCREG_VBAR, MISCREG_VMPIDR, MISCREG_VPIDR, MISCREG_VTCR, and opc2.

Referenced by ArmKvmCPU::decodeCoProcReg().

◆ decodeCP15Reg64()

MiscRegIndex ArmISA::decodeCP15Reg64 ( unsigned  crm,
unsigned  opc1 
)

◆ decodeMrsMsrBankedIntRegIndex()

static int ArmISA::decodeMrsMsrBankedIntRegIndex ( uint8_t  sysM,
bool  r 
)
inlinestatic

Definition at line 429 of file utility.hh.

References decodeMrsMsrBankedReg(), INTREG_DUMMY, and MipsISA::r.

◆ decodeMrsMsrBankedReg()

bool ArmISA::decodeMrsMsrBankedReg ( uint8_t  sysM,
bool  r,
bool &  isIntReg,
int &  regIdx,
CPSR  cpsr,
SCR  scr,
NSACR  nsacr,
bool  checkSecurity 
)

◆ decodePhysAddrRange64()

int ArmISA::decodePhysAddrRange64 ( uint8_t  pa_enc)

Returns the n.

of PA bits corresponding to the specified encoding.

Definition at line 1381 of file utility.cc.

References panic.

◆ EL2Enabled()

bool ArmISA::EL2Enabled ( ThreadContext tc)

◆ ELIs32()

bool ArmISA::ELIs32 ( ThreadContext tc,
ExceptionLevel  el 
)

◆ ELIs64()

bool ArmISA::ELIs64 ( ThreadContext tc,
ExceptionLevel  el 
)

◆ ELIsInHost()

bool ArmISA::ELIsInHost ( ThreadContext tc,
ExceptionLevel  el 
)

◆ ELStateUsingAArch32()

bool ArmISA::ELStateUsingAArch32 ( ThreadContext tc,
ExceptionLevel  el,
bool  secure 
)

Definition at line 473 of file utility.cc.

References el, ELStateUsingAArch32K(), and panic_if.

Referenced by ArmISA::SelfDebug::isDebugEnabledForEL32().

◆ ELStateUsingAArch32K()

std::pair< bool, bool > ArmISA::ELStateUsingAArch32K ( ThreadContext tc,
ExceptionLevel  el,
bool  secure 
)

◆ ELUsingAArch32K()

std::pair< bool, bool > ArmISA::ELUsingAArch32K ( ThreadContext tc,
ExceptionLevel  el 
)

This function checks whether selected EL provided as an argument is using the AArch32 ISA.

This information might be unavailable at the current EL status: it hence returns a pair of boolean values: a first boolean, true if information is available (known), and a second one, true if EL is using AArch32, false for AArch64.

Parameters
tcThe thread context.
elThe target exception level.
Return values
knownis FALSE for EL0 if the current Exception level is not EL0 and EL1 is using AArch64, since it cannot determine the state of EL0; TRUE otherwise.
aarch32is TRUE if the specified Exception level is using AArch32; FALSE otherwise.

Definition at line 402 of file utility.cc.

References el, ELStateUsingAArch32K(), and isSecureBelowEL3().

Referenced by ELIs32(), and illegalExceptionReturn().

◆ encodePhysAddrRange64()

uint8_t ArmISA::encodePhysAddrRange64 ( int  pa_size)

Returns the encoding corresponding to the specified n.

of PA bits.

Definition at line 1404 of file utility.cc.

References panic.

Referenced by ArmISA::ISA::initID64().

◆ EndBitUnion() [1/44]

ArmISA::EndBitUnion ( AA64DFR0  )

◆ EndBitUnion() [2/44]

ArmISA::EndBitUnion ( AA64ISAR0  )

◆ EndBitUnion() [3/44]

ArmISA::EndBitUnion ( AA64ISAR1  )

◆ EndBitUnion() [4/44]

ArmISA::EndBitUnion ( AA64MMFR0  )

◆ EndBitUnion() [5/44]

ArmISA::EndBitUnion ( AA64MMFR1  )

◆ EndBitUnion() [6/44]

ArmISA::EndBitUnion ( AA64MMFR2  )

◆ EndBitUnion() [7/44]

ArmISA::EndBitUnion ( AA64PFR0  )

◆ EndBitUnion() [8/44]

ArmISA::EndBitUnion ( CNTHCTL  )

◆ EndBitUnion() [9/44]

ArmISA::EndBitUnion ( CNTKCTL  )

◆ EndBitUnion() [10/44]

ArmISA::EndBitUnion ( CONTEXTIDR  )

◆ EndBitUnion() [11/44]

ArmISA::EndBitUnion ( CPACR  )

◆ EndBitUnion() [12/44]

ArmISA::EndBitUnion ( CPSR  )

◆ EndBitUnion() [13/44]

ArmISA::EndBitUnion ( CPTR  )

◆ EndBitUnion() [14/44]

ArmISA::EndBitUnion ( CTR  )

◆ EndBitUnion() [15/44]

ArmISA::EndBitUnion ( DBGBCR  )

◆ EndBitUnion() [16/44]

ArmISA::EndBitUnion ( DBGDS32  )

◆ EndBitUnion() [17/44]

ArmISA::EndBitUnion ( DBGVCR  )

◆ EndBitUnion() [18/44]

ArmISA::EndBitUnion ( DBGWCR  )

◆ EndBitUnion() [19/44]

ArmISA::EndBitUnion ( ESR  )

◆ EndBitUnion() [20/44]

ArmISA::EndBitUnion ( FPEXC  )

◆ EndBitUnion() [21/44]

ArmISA::EndBitUnion ( FPSCR  )

◆ EndBitUnion() [22/44]

ArmISA::EndBitUnion ( FSR  )

◆ EndBitUnion() [23/44]

ArmISA::EndBitUnion ( HCPTR  )

◆ EndBitUnion() [24/44]

ArmISA::EndBitUnion ( HCR  )

◆ EndBitUnion() [25/44]

ArmISA::EndBitUnion ( HDCR  )

◆ EndBitUnion() [26/44]

ArmISA::EndBitUnion ( HSTR  )

◆ EndBitUnion() [27/44]

ArmISA::EndBitUnion ( HTCR  )

◆ EndBitUnion() [28/44]

ArmISA::EndBitUnion ( ITSTATE  )

◆ EndBitUnion() [29/44]

ArmISA::EndBitUnion ( L2CTLR  )

◆ EndBitUnion() [30/44]

ArmISA::EndBitUnion ( MVFR0  )

◆ EndBitUnion() [31/44]

ArmISA::EndBitUnion ( MVFR1  )

◆ EndBitUnion() [32/44]

ArmISA::EndBitUnion ( NMRR  )

◆ EndBitUnion() [33/44]

ArmISA::EndBitUnion ( NSACR  )

◆ EndBitUnion() [34/44]

ArmISA::EndBitUnion ( OperatingMode64  )

Definition at line 714 of file types.hh.

References mode.

◆ EndBitUnion() [35/44]

ArmISA::EndBitUnion ( OSL  )

◆ EndBitUnion() [36/44]

ArmISA::EndBitUnion ( PAR  )

◆ EndBitUnion() [37/44]

ArmISA::EndBitUnion ( PMSELR  )

◆ EndBitUnion() [38/44]

ArmISA::EndBitUnion ( PRRR  )

◆ EndBitUnion() [39/44]

ArmISA::EndBitUnion ( SCR  )

◆ EndBitUnion() [40/44]

ArmISA::EndBitUnion ( SCTLR  )

◆ EndBitUnion() [41/44]

ArmISA::EndBitUnion ( TCR  )

◆ EndBitUnion() [42/44]

ArmISA::EndBitUnion ( TTBCR  )

◆ EndBitUnion() [43/44]

ArmISA::EndBitUnion ( VTCR_t  )

◆ EndBitUnion() [44/44]

ArmISA::EndBitUnion ( ZCR  )

◆ EndSubBitUnion()

ArmISA::EndSubBitUnion ( puswl  )

◆ finishVfp()

void ArmISA::finishVfp ( FPSCR &  fpscr,
VfpSavedState  state,
bool  flush,
FPSCR  mask 
)

◆ fixDest() [1/4]

template<class fpType >
fpType ArmISA::fixDest ( bool  flush,
bool  defaultNan,
fpType  val,
fpType  op1 
)

Definition at line 228 of file vfp.cc.

References bitsToFp(), FeInexact, FeUnderflow, fpToBits(), ULL, and X86ISA::val.

Referenced by fixDivDest(), fixFpDFpSDest(), and fixFpSFpDDest().

◆ fixDest() [2/4]

template<class fpType >
fpType ArmISA::fixDest ( bool  flush,
bool  defaultNan,
fpType  val,
fpType  op1,
fpType  op2 
)

Definition at line 258 of file vfp.cc.

References bitsToFp(), FeInexact, FeUnderflow, fpToBits(), ULL, and X86ISA::val.

◆ fixDest() [3/4]

template<class fpType >
fpType ArmISA::fixDest ( FPSCR  fpscr,
fpType  val,
fpType  op1 
)

◆ fixDest() [4/4]

template<class fpType >
fpType ArmISA::fixDest ( FPSCR  fpscr,
fpType  val,
fpType  op1,
fpType  op2 
)

◆ fixDest< double >() [1/2]

template double ArmISA::fixDest< double > ( bool  flush,
bool  defaultNan,
double  val,
double  op1 
)

◆ fixDest< double >() [2/2]

template double ArmISA::fixDest< double > ( bool  flush,
bool  defaultNan,
double  val,
double  op1,
double  op2 
)

◆ fixDest< float >() [1/2]

template float ArmISA::fixDest< float > ( bool  flush,
bool  defaultNan,
float  val,
float  op1 
)

◆ fixDest< float >() [2/2]

template float ArmISA::fixDest< float > ( bool  flush,
bool  defaultNan,
float  val,
float  op1,
float  op2 
)

◆ fixDivDest() [1/2]

template<class fpType >
fpType ArmISA::fixDivDest ( bool  flush,
bool  defaultNan,
fpType  val,
fpType  op1,
fpType  op2 
)

◆ fixDivDest() [2/2]

template<class fpType >
fpType ArmISA::fixDivDest ( FPSCR  fpscr,
fpType  val,
fpType  op1,
fpType  op2 
)

◆ fixDivDest< double >()

template double ArmISA::fixDivDest< double > ( bool  flush,
bool  defaultNan,
double  val,
double  op1,
double  op2 
)

◆ fixDivDest< float >()

template float ArmISA::fixDivDest< float > ( bool  flush,
bool  defaultNan,
float  val,
float  op1,
float  op2 
)

◆ fixFpDFpSDest()

float ArmISA::fixFpDFpSDest ( FPSCR  fpscr,
double  val 
)

◆ fixFpSFpDDest()

double ArmISA::fixFpSFpDDest ( FPSCR  fpscr,
float  val 
)

◆ flattenIntRegModeIndex()

static int ArmISA::flattenIntRegModeIndex ( int  reg)
inlinestatic

◆ flushToZero() [1/2]

template<class fpType >
static bool ArmISA::flushToZero ( fpType &  op)
inlinestatic

Definition at line 116 of file vfp.hh.

References bitsToFp(), fpToBits(), X86ISA::op, and ULL.

◆ flushToZero() [2/2]

template<class fpType >
static bool ArmISA::flushToZero ( fpType &  op1,
fpType &  op2 
)
inlinestatic

Definition at line 129 of file vfp.hh.

References flushToZero.

◆ fp128_normalise()

static void ArmISA::fp128_normalise ( uint64_t *  mnt0,
uint64_t *  mnt1,
int *  exp 
)
inlinestatic

Definition at line 270 of file fplib.cc.

References shift.

Referenced by fp64_mul(), and fp64_muladd().

◆ fp16_add()

static uint16_t ArmISA::fp16_add ( uint16_t  a,
uint16_t  b,
int  neg,
int  mode,
int *  flags 
)
static

◆ fp16_compare_eq()

static int ArmISA::fp16_compare_eq ( uint16_t  a,
uint16_t  b,
int  mode,
int *  flags 
)
static

Definition at line 956 of file fplib.cc.

References a, b, fp16_is_NaN(), fp16_is_signalling_NaN(), fp16_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareEQ().

◆ fp16_compare_ge()

static int ArmISA::fp16_compare_ge ( uint16_t  a,
uint16_t  b,
int  mode,
int *  flags 
)
static

Definition at line 975 of file fplib.cc.

References a, b, fp16_is_NaN(), fp16_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGE().

◆ fp16_compare_gt()

static int ArmISA::fp16_compare_gt ( uint16_t  a,
uint16_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1000 of file fplib.cc.

References a, b, fp16_is_NaN(), fp16_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGT().

◆ fp16_compare_un()

static int ArmISA::fp16_compare_un ( uint16_t  a,
uint16_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1025 of file fplib.cc.

References a, b, fp16_is_NaN(), fp16_is_signalling_NaN(), fp16_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareUN().

◆ fp16_cvtf()

static uint16_t ArmISA::fp16_cvtf ( uint64_t  a,
int  fbits,
int  u,
int  mode,
int *  flags 
)
static

Definition at line 4905 of file fplib.cc.

References a, FP16_BITS, FP16_EXP_BIAS, fp16_round(), fp16_zero(), FP64_BITS, fp64_normalise(), mode, u, and ULL.

Referenced by fplibFixedToFP().

◆ fp16_defaultNaN()

static uint16_t ArmISA::fp16_defaultNaN ( )
inlinestatic

◆ fp16_div()

static uint16_t ArmISA::fp16_div ( uint16_t  a,
uint16_t  b,
int  mode,
int *  flags 
)
static

◆ fp16_FPConvertNaN_32()

static uint16_t ArmISA::fp16_FPConvertNaN_32 ( uint32_t  op)
static

Definition at line 2521 of file fplib.cc.

References FP16_EXP_INF, FP16_MANT_BITS, fp16_pack(), FP32_BITS, FP32_MANT_BITS, X86ISA::op, and ULL.

Referenced by fplibConvert().

◆ fp16_FPConvertNaN_64()

static uint16_t ArmISA::fp16_FPConvertNaN_64 ( uint64_t  op)
static

Definition at line 2529 of file fplib.cc.

References FP16_EXP_INF, FP16_MANT_BITS, fp16_pack(), FP64_BITS, FP64_MANT_BITS, X86ISA::op, and ULL.

Referenced by fplibConvert().

◆ fp16_FPOnePointFive()

static uint16_t ArmISA::fp16_FPOnePointFive ( int  sgn)
static

Definition at line 2569 of file fplib.cc.

References FP16_EXP_BIAS, FP16_MANT_BITS, fp16_pack(), and ULL.

Referenced by fplibRSqrtStepFused().

◆ fp16_FPThree()

static uint16_t ArmISA::fp16_FPThree ( int  sgn)
static

Definition at line 2587 of file fplib.cc.

References FP16_EXP_BIAS, FP16_MANT_BITS, fp16_pack(), and ULL.

Referenced by fplibRSqrtStepFused().

◆ fp16_FPTwo()

static uint16_t ArmISA::fp16_FPTwo ( int  sgn)
static

Definition at line 2605 of file fplib.cc.

References FP16_EXP_BIAS, and fp16_pack().

Referenced by fplibMulX(), and fplibRecipStepFused().

◆ fp16_infinity()

static uint16_t ArmISA::fp16_infinity ( int  sgn)
inlinestatic

◆ fp16_is_infinity()

static int ArmISA::fp16_is_infinity ( int  exp,
uint16_t  mnt 
)
inlinestatic

Definition at line 514 of file fplib.cc.

References FP16_EXP_INF, and FP16_MANT.

Referenced by fp16_muladd().

◆ fp16_is_NaN()

static int ArmISA::fp16_is_NaN ( int  exp,
uint16_t  mnt 
)
inlinestatic

◆ fp16_is_quiet_NaN()

static int ArmISA::fp16_is_quiet_NaN ( int  exp,
uint16_t  mnt 
)
inlinestatic

Definition at line 496 of file fplib.cc.

References FP16_EXP_INF, and FP16_MANT_BITS.

Referenced by fp16_muladd().

◆ fp16_is_signalling_NaN()

static int ArmISA::fp16_is_signalling_NaN ( int  exp,
uint16_t  mnt 
)
inlinestatic

◆ fp16_max_normal()

static uint16_t ArmISA::fp16_max_normal ( int  sgn)
inlinestatic

Definition at line 335 of file fplib.cc.

References FP16_EXP_INF, and fp16_pack().

Referenced by fp16_round_(), and fplibRecipEstimate().

◆ fp16_minmaxnum()

static void ArmISA::fp16_minmaxnum ( uint16_t *  op1,
uint16_t *  op2,
int  sgn 
)
static

Definition at line 3142 of file fplib.cc.

References fp16_infinity(), and FP16_MANT_BITS.

Referenced by fplibMaxNum(), and fplibMinNum().

◆ fp16_mul()

static uint16_t ArmISA::fp16_mul ( uint16_t  a,
uint16_t  b,
int  mode,
int *  flags 
)
static

◆ fp16_muladd()

static uint16_t ArmISA::fp16_muladd ( uint16_t  a,
uint16_t  b,
uint16_t  c,
int  scale,
int  mode,
int *  flags 
)
static

◆ fp16_normalise()

static uint16_t ArmISA::fp16_normalise ( uint16_t  mnt,
int *  exp 
)
inlinestatic

◆ fp16_pack()

static uint16_t ArmISA::fp16_pack ( uint16_t  sgn,
uint16_t  exp,
uint16_t  mnt 
)
inlinestatic

◆ fp16_process_NaN()

static uint16_t ArmISA::fp16_process_NaN ( uint16_t  a,
int  mode,
int *  flags 
)
inlinestatic

◆ fp16_process_NaNs()

static uint16_t ArmISA::fp16_process_NaNs ( uint16_t  a,
uint16_t  b,
int  mode,
int *  flags 
)
static

◆ fp16_process_NaNs3()

static uint16_t ArmISA::fp16_process_NaNs3 ( uint16_t  a,
uint16_t  b,
uint16_t  c,
int  mode,
int *  flags 
)
static

Definition at line 631 of file fplib.cc.

References a, b, c, FP16_EXP, fp16_is_NaN(), fp16_is_signalling_NaN(), FP16_MANT, fp16_process_NaN(), and mode.

Referenced by fp16_muladd().

◆ fp16_repack()

static uint16_t ArmISA::fp16_repack ( int  sgn,
int  exp,
uint16_t  mnt 
)
static

Definition at line 3124 of file fplib.cc.

References FP16_MANT_BITS, and fp16_pack().

Referenced by fplibMax(), and fplibMin().

◆ fp16_round()

static uint16_t ArmISA::fp16_round ( int  sgn,
int  exp,
uint16_t  mnt,
int  mode,
int *  flags 
)
static

Definition at line 796 of file fplib.cc.

References fp16_round_(), and mode.

Referenced by fp16_add(), fp16_cvtf(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_scale(), and fp16_sqrt().

◆ fp16_round_()

static uint16_t ArmISA::fp16_round_ ( int  sgn,
int  exp,
uint16_t  mnt,
int  rm,
int  mode,
int *  flags 
)
static

◆ fp16_scale()

static uint16_t ArmISA::fp16_scale ( uint16_t  a,
int16_t  b,
int  mode,
int *  flags 
)
static

◆ fp16_sqrt()

static uint16_t ArmISA::fp16_sqrt ( uint16_t  a,
int  mode,
int *  flags 
)
static

◆ fp16_unpack()

static void ArmISA::fp16_unpack ( int *  sgn,
int *  exp,
uint16_t *  mnt,
uint16_t  x,
int  mode,
int *  flags 
)
inlinestatic

◆ fp16_zero()

static uint16_t ArmISA::fp16_zero ( int  sgn)
inlinestatic

◆ fp32_add()

static uint32_t ArmISA::fp32_add ( uint32_t  a,
uint32_t  b,
int  neg,
int  mode,
int *  flags 
)
static

◆ fp32_compare_eq()

static int ArmISA::fp32_compare_eq ( uint32_t  a,
uint32_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1044 of file fplib.cc.

References a, b, fp32_is_NaN(), fp32_is_signalling_NaN(), fp32_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareEQ().

◆ fp32_compare_ge()

static int ArmISA::fp32_compare_ge ( uint32_t  a,
uint32_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1063 of file fplib.cc.

References a, b, fp32_is_NaN(), fp32_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGE().

◆ fp32_compare_gt()

static int ArmISA::fp32_compare_gt ( uint32_t  a,
uint32_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1088 of file fplib.cc.

References a, b, fp32_is_NaN(), fp32_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGT().

◆ fp32_compare_un()

static int ArmISA::fp32_compare_un ( uint32_t  a,
uint32_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1113 of file fplib.cc.

References a, b, fp32_is_NaN(), fp32_is_signalling_NaN(), fp32_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareUN().

◆ fp32_cvtf()

static uint32_t ArmISA::fp32_cvtf ( uint64_t  a,
int  fbits,
int  u,
int  mode,
int *  flags 
)
static

Definition at line 4925 of file fplib.cc.

References a, FP32_BITS, FP32_EXP_BIAS, fp32_round(), fp32_zero(), FP64_BITS, fp64_normalise(), mode, u, and ULL.

◆ fp32_defaultNaN()

static uint32_t ArmISA::fp32_defaultNaN ( )
inlinestatic

◆ fp32_div()

static uint32_t ArmISA::fp32_div ( uint32_t  a,
uint32_t  b,
int  mode,
int *  flags 
)
static

◆ fp32_FPConvertNaN_16()

static uint32_t ArmISA::fp32_FPConvertNaN_16 ( uint16_t  op)
static

Definition at line 2537 of file fplib.cc.

References FP16_BITS, FP16_MANT_BITS, FP32_EXP_INF, FP32_MANT_BITS, fp32_pack(), X86ISA::op, and ULL.

Referenced by fplibConvert().

◆ fp32_FPConvertNaN_64()

static uint32_t ArmISA::fp32_FPConvertNaN_64 ( uint64_t  op)
static

Definition at line 2545 of file fplib.cc.

References FP32_EXP_INF, FP32_MANT_BITS, fp32_pack(), FP64_BITS, FP64_MANT_BITS, X86ISA::op, and ULL.

◆ fp32_FPOnePointFive()

static uint32_t ArmISA::fp32_FPOnePointFive ( int  sgn)
static

Definition at line 2575 of file fplib.cc.

References FP32_EXP_BIAS, FP32_MANT_BITS, fp32_pack(), and ULL.

Referenced by fplibRSqrtStepFused().

◆ fp32_FPThree()

static uint32_t ArmISA::fp32_FPThree ( int  sgn)
static

Definition at line 2593 of file fplib.cc.

References FP32_EXP_BIAS, FP32_MANT_BITS, fp32_pack(), and ULL.

Referenced by fplibRSqrtStepFused().

◆ fp32_FPTwo()

static uint32_t ArmISA::fp32_FPTwo ( int  sgn)
static

Definition at line 2611 of file fplib.cc.

References FP32_EXP_BIAS, and fp32_pack().

Referenced by fplibMulX(), and fplibRecipStepFused().

◆ fp32_infinity()

static uint32_t ArmISA::fp32_infinity ( int  sgn)
inlinestatic

◆ fp32_is_infinity()

static int ArmISA::fp32_is_infinity ( int  exp,
uint32_t  mnt 
)
inlinestatic

Definition at line 520 of file fplib.cc.

References FP32_EXP_INF, and FP32_MANT.

Referenced by fp32_muladd().

◆ fp32_is_NaN()

static int ArmISA::fp32_is_NaN ( int  exp,
uint32_t  mnt 
)
inlinestatic

◆ fp32_is_quiet_NaN()

static int ArmISA::fp32_is_quiet_NaN ( int  exp,
uint32_t  mnt 
)
inlinestatic

Definition at line 502 of file fplib.cc.

References FP32_EXP_INF, and FP32_MANT_BITS.

Referenced by fp32_muladd().

◆ fp32_is_signalling_NaN()

static int ArmISA::fp32_is_signalling_NaN ( int  exp,
uint32_t  mnt 
)
inlinestatic

◆ fp32_max_normal()

static uint32_t ArmISA::fp32_max_normal ( int  sgn)
inlinestatic

Definition at line 341 of file fplib.cc.

References FP32_EXP_INF, and fp32_pack().

Referenced by fp32_round_(), and fplibRecipEstimate().

◆ fp32_minmaxnum()

static void ArmISA::fp32_minmaxnum ( uint32_t *  op1,
uint32_t *  op2,
int  sgn 
)
static

Definition at line 3154 of file fplib.cc.

References fp32_infinity(), and FP32_MANT_BITS.

Referenced by fplibMaxNum(), and fplibMinNum().

◆ fp32_mul()

static uint32_t ArmISA::fp32_mul ( uint32_t  a,
uint32_t  b,
int  mode,
int *  flags 
)
static

◆ fp32_muladd()

static uint32_t ArmISA::fp32_muladd ( uint32_t  a,
uint32_t  b,
uint32_t  c,
int  scale,
int  mode,
int *  flags 
)
static

◆ fp32_normalise()

static uint32_t ArmISA::fp32_normalise ( uint32_t  mnt,
int *  exp 
)
inlinestatic

◆ fp32_pack()

static uint32_t ArmISA::fp32_pack ( uint32_t  sgn,
uint32_t  exp,
uint32_t  mnt 
)
inlinestatic

◆ fp32_process_NaN()

static uint32_t ArmISA::fp32_process_NaN ( uint32_t  a,
int  mode,
int *  flags 
)
inlinestatic

◆ fp32_process_NaNs()

static uint32_t ArmISA::fp32_process_NaNs ( uint32_t  a,
uint32_t  b,
int  mode,
int *  flags 
)
static

◆ fp32_process_NaNs3()

static uint32_t ArmISA::fp32_process_NaNs3 ( uint32_t  a,
uint32_t  b,
uint32_t  c,
int  mode,
int *  flags 
)
static

Definition at line 660 of file fplib.cc.

References a, b, c, FP32_EXP, fp32_is_NaN(), fp32_is_signalling_NaN(), FP32_MANT, fp32_process_NaN(), and mode.

Referenced by fp32_muladd().

◆ fp32_repack()

static uint32_t ArmISA::fp32_repack ( int  sgn,
int  exp,
uint32_t  mnt 
)
static

Definition at line 3130 of file fplib.cc.

References FP32_MANT_BITS, and fp32_pack().

Referenced by fplibMax(), and fplibMin().

◆ fp32_round()

static uint32_t ArmISA::fp32_round ( int  sgn,
int  exp,
uint32_t  mnt,
int  mode,
int *  flags 
)
static

Definition at line 873 of file fplib.cc.

References fp32_round_(), and mode.

Referenced by fp32_add(), fp32_cvtf(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_scale(), and fp32_sqrt().

◆ fp32_round_()

static uint32_t ArmISA::fp32_round_ ( int  sgn,
int  exp,
uint32_t  mnt,
int  rm,
int  mode,
int *  flags 
)
static

◆ fp32_scale()

static uint32_t ArmISA::fp32_scale ( uint32_t  a,
int32_t  b,
int  mode,
int *  flags 
)
static

◆ fp32_sqrt()

static uint32_t ArmISA::fp32_sqrt ( uint32_t  a,
int  mode,
int *  flags 
)
static

◆ fp32_unpack()

static void ArmISA::fp32_unpack ( int *  sgn,
int *  exp,
uint32_t *  mnt,
uint32_t  x,
int  mode,
int *  flags 
)
inlinestatic

◆ fp32_zero()

static uint32_t ArmISA::fp32_zero ( int  sgn)
inlinestatic

◆ fp64_add()

static uint64_t ArmISA::fp64_add ( uint64_t  a,
uint64_t  b,
int  neg,
int  mode,
int *  flags 
)
static

◆ fp64_compare_eq()

static int ArmISA::fp64_compare_eq ( uint64_t  a,
uint64_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1132 of file fplib.cc.

References a, b, fp64_is_NaN(), fp64_is_signalling_NaN(), fp64_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareEQ().

◆ fp64_compare_ge()

static int ArmISA::fp64_compare_ge ( uint64_t  a,
uint64_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1151 of file fplib.cc.

References a, b, fp64_is_NaN(), fp64_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGE().

◆ fp64_compare_gt()

static int ArmISA::fp64_compare_gt ( uint64_t  a,
uint64_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1176 of file fplib.cc.

References a, b, fp64_is_NaN(), fp64_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGT().

◆ fp64_compare_un()

static int ArmISA::fp64_compare_un ( uint64_t  a,
uint64_t  b,
int  mode,
int *  flags 
)
static

Definition at line 1201 of file fplib.cc.

References a, b, fp64_is_NaN(), fp64_is_signalling_NaN(), fp64_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareUN().

◆ fp64_cvtf()

static uint64_t ArmISA::fp64_cvtf ( uint64_t  a,
int  fbits,
int  u,
int  mode,
int *  flags 
)
static

Definition at line 4945 of file fplib.cc.

References a, FP64_BITS, FP64_EXP_BIAS, fp64_normalise(), fp64_round(), fp64_zero(), mode, and u.

◆ fp64_defaultNaN()

static uint64_t ArmISA::fp64_defaultNaN ( )
inlinestatic

◆ fp64_div()

static uint64_t ArmISA::fp64_div ( uint64_t  a,
uint64_t  b,
int  mode,
int *  flags 
)
static

◆ fp64_FPConvertNaN_16()

static uint64_t ArmISA::fp64_FPConvertNaN_16 ( uint16_t  op)
static

Definition at line 2553 of file fplib.cc.

References FP16_BITS, FP16_MANT_BITS, FP64_EXP_INF, FP64_MANT_BITS, fp64_pack(), X86ISA::op, and ULL.

◆ fp64_FPConvertNaN_32()

static uint64_t ArmISA::fp64_FPConvertNaN_32 ( uint32_t  op)
static

Definition at line 2561 of file fplib.cc.

References FP32_BITS, FP32_MANT_BITS, FP64_EXP_INF, FP64_MANT_BITS, fp64_pack(), X86ISA::op, and ULL.

◆ fp64_FPOnePointFive()

static uint64_t ArmISA::fp64_FPOnePointFive ( int  sgn)
static

Definition at line 2581 of file fplib.cc.

References FP64_EXP_BIAS, FP64_MANT_BITS, fp64_pack(), and ULL.

Referenced by fplibRSqrtStepFused().

◆ fp64_FPThree()

static uint64_t ArmISA::fp64_FPThree ( int  sgn)
static

Definition at line 2599 of file fplib.cc.

References FP64_EXP_BIAS, FP64_MANT_BITS, fp64_pack(), and ULL.

Referenced by fplibRSqrtStepFused().

◆ fp64_FPTwo()

static uint64_t ArmISA::fp64_FPTwo ( int  sgn)
static

Definition at line 2617 of file fplib.cc.

References FP64_EXP_BIAS, and fp64_pack().

Referenced by fplibMulX(), and fplibRecipStepFused().

◆ fp64_infinity()

static uint64_t ArmISA::fp64_infinity ( int  sgn)
inlinestatic

◆ fp64_is_infinity()

static int ArmISA::fp64_is_infinity ( int  exp,
uint64_t  mnt 
)
inlinestatic

Definition at line 526 of file fplib.cc.

References FP64_EXP_INF, and FP64_MANT.

Referenced by fp64_muladd().

◆ fp64_is_NaN()

static int ArmISA::fp64_is_NaN ( int  exp,
uint64_t  mnt 
)
inlinestatic

◆ fp64_is_quiet_NaN()

static int ArmISA::fp64_is_quiet_NaN ( int  exp,
uint64_t  mnt 
)
inlinestatic

Definition at line 508 of file fplib.cc.

References FP64_EXP_INF, and FP64_MANT_BITS.

Referenced by fp64_muladd().

◆ fp64_is_signalling_NaN()

static int ArmISA::fp64_is_signalling_NaN ( int  exp,
uint64_t  mnt 
)
inlinestatic

◆ fp64_max_normal()

static uint64_t ArmISA::fp64_max_normal ( int  sgn)
inlinestatic

Definition at line 347 of file fplib.cc.

References FP64_EXP_INF, and fp64_pack().

Referenced by fp64_round_(), and fplibRecipEstimate().

◆ fp64_minmaxnum()

static void ArmISA::fp64_minmaxnum ( uint64_t *  op1,
uint64_t *  op2,
int  sgn 
)
static

Definition at line 3166 of file fplib.cc.

References fp64_infinity(), and FP64_MANT_BITS.

Referenced by fplibMaxNum(), and fplibMinNum().

◆ fp64_mul()

static uint64_t ArmISA::fp64_mul ( uint64_t  a,
uint64_t  b,
int  mode,
int *  flags 
)
static

◆ fp64_muladd()

static uint64_t ArmISA::fp64_muladd ( uint64_t  a,
uint64_t  b,
uint64_t  c,
int  scale,
int  mode,
int *  flags 
)
static

◆ fp64_normalise()

static uint64_t ArmISA::fp64_normalise ( uint64_t  mnt,
int *  exp 
)
inlinestatic

◆ fp64_pack()

static uint64_t ArmISA::fp64_pack ( uint64_t  sgn,
uint64_t  exp,
uint64_t  mnt 
)
inlinestatic

◆ fp64_process_NaN()

static uint64_t ArmISA::fp64_process_NaN ( uint64_t  a,
int  mode,
int *  flags 
)
inlinestatic

◆ fp64_process_NaNs()

static uint64_t ArmISA::fp64_process_NaNs ( uint64_t  a,
uint64_t  b,
int  mode,
int *  flags 
)
static

◆ fp64_process_NaNs3()

static uint64_t ArmISA::fp64_process_NaNs3 ( uint64_t  a,
uint64_t  b,
uint64_t  c,
int  mode,
int *  flags 
)
static

Definition at line 689 of file fplib.cc.

References a, b, c, FP64_EXP, fp64_is_NaN(), fp64_is_signalling_NaN(), FP64_MANT, fp64_process_NaN(), and mode.

Referenced by fp64_muladd().

◆ fp64_repack()

static uint64_t ArmISA::fp64_repack ( int  sgn,
int  exp,
uint64_t  mnt 
)
static

Definition at line 3136 of file fplib.cc.

References FP64_MANT_BITS, and fp64_pack().

Referenced by fplibMax(), and fplibMin().

◆ fp64_round()

static uint64_t ArmISA::fp64_round ( int  sgn,
int  exp,
uint64_t  mnt,
int  mode,
int *  flags 
)
static

Definition at line 950 of file fplib.cc.

References fp64_round_(), and mode.

Referenced by fp64_add(), fp64_cvtf(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_scale(), and fp64_sqrt().

◆ fp64_round_()

static uint64_t ArmISA::fp64_round_ ( int  sgn,
int  exp,
uint64_t  mnt,
int  rm,
int  mode,
int *  flags 
)
static

◆ fp64_scale()

static uint64_t ArmISA::fp64_scale ( uint64_t  a,
int64_t  b,
int  mode,
int *  flags 
)
static

◆ fp64_sqrt()

static uint64_t ArmISA::fp64_sqrt ( uint64_t  a,
int  mode,
int *  flags 
)
static

◆ fp64_unpack()

static void ArmISA::fp64_unpack ( int *  sgn,
int *  exp,
uint64_t *  mnt,
uint64_t  x,
int  mode,
int *  flags 
)
inlinestatic

◆ fp64_zero()

static uint64_t ArmISA::fp64_zero ( int  sgn)
inlinestatic

◆ fpAdd()

template<typename T >
static T ArmISA::fpAdd ( a,
b 
)
inlinestatic

Definition at line 476 of file vfp.hh.

References a, and b.

◆ fpAddD()

static double ArmISA::fpAddD ( double  a,
double  b 
)
inlinestatic

Definition at line 495 of file vfp.hh.

References a, and b.

◆ fpAddS()

static float ArmISA::fpAddS ( float  a,
float  b 
)
inlinestatic

Definition at line 489 of file vfp.hh.

References a, and b.

◆ FPCRRounding()

static FPRounding ArmISA::FPCRRounding ( FPSCR &  fpscr)
inlinestatic

Definition at line 67 of file fplib.hh.

Referenced by fplibRecipEstimate().

◆ fpDiv()

template<typename T >
static T ArmISA::fpDiv ( a,
b 
)
inlinestatic

Definition at line 526 of file vfp.hh.

References a, and b.

◆ fpDivD()

static double ArmISA::fpDivD ( double  a,
double  b 
)
inlinestatic

Definition at line 519 of file vfp.hh.

References a, and b.

◆ fpDivS()

static float ArmISA::fpDivS ( float  a,
float  b 
)
inlinestatic

Definition at line 513 of file vfp.hh.

References a, and b.

◆ fplibAbs() [1/4]

template<class T >
T ArmISA::fplibAbs ( op)

Floating-point absolute value.

◆ fplibAbs() [2/4]

template<>
uint16_t ArmISA::fplibAbs ( uint16_t  op)

Definition at line 2369 of file fplib.cc.

References FP16_BITS, X86ISA::op, and ULL.

Referenced by fplibTrigMulAdd().

◆ fplibAbs() [3/4]

template<>
uint32_t ArmISA::fplibAbs ( uint32_t  op)

Definition at line 2376 of file fplib.cc.

References FP32_BITS, X86ISA::op, and ULL.

◆ fplibAbs() [4/4]

template<>
uint64_t ArmISA::fplibAbs ( uint64_t  op)

Definition at line 2383 of file fplib.cc.

References FP64_BITS, X86ISA::op, and ULL.

◆ fplibAdd() [1/4]

template<class T >
T ArmISA::fplibAdd ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point add.

◆ fplibAdd() [2/4]

template<>
uint16_t ArmISA::fplibAdd ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 2390 of file fplib.cc.

References fp16_add(), modeConv(), and set_fpscr0().

◆ fplibAdd() [3/4]

template<>
uint32_t ArmISA::fplibAdd ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 2400 of file fplib.cc.

References fp32_add(), modeConv(), and set_fpscr0().

◆ fplibAdd() [4/4]

template<>
uint64_t ArmISA::fplibAdd ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 2410 of file fplib.cc.

References fp64_add(), modeConv(), and set_fpscr0().

◆ fplibCompare() [1/4]

template<class T >
int ArmISA::fplibCompare ( op1,
op2,
bool  signal_nans,
FPSCR &  fpscr 
)

Floating-point compare (quiet and signaling).

◆ fplibCompare() [2/4]

template<>
int ArmISA::fplibCompare ( uint16_t  op1,
uint16_t  op2,
bool  signal_nans,
FPSCR &  fpscr 
)

◆ fplibCompare() [3/4]

template<>
int ArmISA::fplibCompare ( uint32_t  op1,
uint32_t  op2,
bool  signal_nans,
FPSCR &  fpscr 
)

◆ fplibCompare() [4/4]

template<>
int ArmISA::fplibCompare ( uint64_t  op1,
uint64_t  op2,
bool  signal_nans,
FPSCR &  fpscr 
)

◆ fplibCompareEQ() [1/4]

template<class T >
bool ArmISA::fplibCompareEQ ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point compare equal.

◆ fplibCompareEQ() [2/4]

template<>
bool ArmISA::fplibCompareEQ ( uint16_t  a,
uint16_t  b,
FPSCR &  fpscr 
)

Definition at line 2249 of file fplib.cc.

References a, b, fp16_compare_eq(), modeConv(), set_fpscr(), and RiscvISA::x.

◆ fplibCompareEQ() [3/4]

template<>
bool ArmISA::fplibCompareEQ ( uint32_t  a,
uint32_t  b,
FPSCR &  fpscr 
)

Definition at line 2289 of file fplib.cc.

References a, b, fp32_compare_eq(), modeConv(), set_fpscr(), and RiscvISA::x.

◆ fplibCompareEQ() [4/4]

template<>
bool ArmISA::fplibCompareEQ ( uint64_t  a,
uint64_t  b,
FPSCR &  fpscr 
)

Definition at line 2329 of file fplib.cc.

References a, b, fp64_compare_eq(), modeConv(), set_fpscr(), and RiscvISA::x.

◆ fplibCompareGE() [1/4]

template<class T >
bool ArmISA::fplibCompareGE ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point compare greater than or equal.

◆ fplibCompareGE() [2/4]

template<>
bool ArmISA::fplibCompareGE ( uint16_t  a,
uint16_t  b,
FPSCR &  fpscr 
)

Definition at line 2259 of file fplib.cc.

References a, b, fp16_compare_ge(), modeConv(), set_fpscr(), and RiscvISA::x.

◆ fplibCompareGE() [3/4]

template<>
bool ArmISA::fplibCompareGE ( uint32_t  a,
uint32_t  b,
FPSCR &  fpscr 
)

Definition at line 2299 of file fplib.cc.

References a, b, fp32_compare_ge(), modeConv(), set_fpscr(), and RiscvISA::x.

◆ fplibCompareGE() [4/4]

template<>
bool ArmISA::fplibCompareGE ( uint64_t  a,
uint64_t  b,
FPSCR &  fpscr 
)

Definition at line 2339 of file fplib.cc.

References a, b, fp64_compare_ge(), modeConv(), set_fpscr(), and RiscvISA::x.

◆ fplibCompareGT() [1/4]

template<class T >
bool ArmISA::fplibCompareGT ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point compare greater than.

◆ fplibCompareGT() [2/4]

template<>
bool ArmISA::fplibCompareGT ( uint16_t  a,
uint16_t  b,
FPSCR &  fpscr 
)

Definition at line 2269 of file fplib.cc.

References a, b, fp16_compare_gt(), modeConv(), set_fpscr(), and RiscvISA::x.

◆ fplibCompareGT() [3/4]

template<>
bool ArmISA::fplibCompareGT ( uint32_t  a,
uint32_t  b,
FPSCR &  fpscr 
)

Definition at line 2309 of file fplib.cc.

References a, b, fp32_compare_gt(), modeConv(), set_fpscr(), and RiscvISA::x.

◆ fplibCompareGT() [4/4]

template<>
bool ArmISA::fplibCompareGT ( uint64_t  a,
uint64_t  b,
FPSCR &  fpscr 
)

Definition at line 2349 of file fplib.cc.

References a, b, fp64_compare_gt(), modeConv(), set_fpscr(), and RiscvISA::x.

◆ fplibCompareUN() [1/4]

template<class T >
bool ArmISA::fplibCompareUN ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point compare unordered.

◆ fplibCompareUN() [2/4]

template<>
bool ArmISA::fplibCompareUN ( uint16_t  a,
uint16_t  b,
FPSCR &  fpscr 
)

Definition at line 2279 of file fplib.cc.

References a, b, fp16_compare_un(), modeConv(), set_fpscr(), and RiscvISA::x.

◆ fplibCompareUN() [3/4]

template<>
bool ArmISA::fplibCompareUN ( uint32_t  a,
uint32_t  b,
FPSCR &  fpscr 
)

Definition at line 2319 of file fplib.cc.

References a, b, fp32_compare_un(), modeConv(), set_fpscr(), and RiscvISA::x.

◆ fplibCompareUN() [4/4]

template<>
bool ArmISA::fplibCompareUN ( uint64_t  a,
uint64_t  b,
FPSCR &  fpscr 
)

Definition at line 2359 of file fplib.cc.

References a, b, fp64_compare_un(), modeConv(), set_fpscr(), and RiscvISA::x.

◆ fplibConvert() [1/4]

template<class T1 , class T2 >
T2 ArmISA::fplibConvert ( T1  op,
FPRounding  rounding,
FPSCR &  fpscr 
)

Floating-point convert precision.

◆ fplibConvert() [2/4]

template<>
uint64_t ArmISA::fplibConvert ( uint16_t  op,
FPRounding  rounding,
FPSCR &  fpscr 
)

◆ fplibConvert() [3/4]

template<>
uint64_t ArmISA::fplibConvert ( uint32_t  op,
FPRounding  rounding,
FPSCR &  fpscr 
)

◆ fplibConvert() [4/4]

template<>
uint32_t ArmISA::fplibConvert ( uint64_t  op,
FPRounding  rounding,
FPSCR &  fpscr 
)

◆ fplibDefaultNaN()

template<>
uint64_t ArmISA::fplibDefaultNaN ( )

Foating-point value for default NaN.

Definition at line 5021 of file fplib.cc.

References fp16_defaultNaN().

◆ fplibDiv() [1/4]

template<class T >
T ArmISA::fplibDiv ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point division.

◆ fplibDiv() [2/4]

template<>
uint16_t ArmISA::fplibDiv ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 2905 of file fplib.cc.

References fp16_div(), modeConv(), and set_fpscr0().

◆ fplibDiv() [3/4]

template<>
uint32_t ArmISA::fplibDiv ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 2915 of file fplib.cc.

References fp32_div(), modeConv(), and set_fpscr0().

◆ fplibDiv() [4/4]

template<>
uint64_t ArmISA::fplibDiv ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 2925 of file fplib.cc.

References fp64_div(), modeConv(), and set_fpscr0().

◆ fplibExpA() [1/4]

template<class T >
T ArmISA::fplibExpA ( op)

Floating-point exponential accelerator.

◆ fplibExpA() [2/4]

template<>
uint16_t ArmISA::fplibExpA ( uint16_t  op)

Definition at line 2935 of file fplib.cc.

References FP16_EXP_BITS, FP16_MANT_BITS, and X86ISA::op.

◆ fplibExpA() [3/4]

template<>
uint32_t ArmISA::fplibExpA ( uint32_t  op)

Definition at line 2977 of file fplib.cc.

References FP32_EXP_BITS, FP32_MANT_BITS, and X86ISA::op.

◆ fplibExpA() [4/4]

template<>
uint64_t ArmISA::fplibExpA ( uint64_t  op)

Definition at line 3051 of file fplib.cc.

References FP64_EXP_BITS, FP64_MANT_BITS, X86ISA::op, and ULL.

◆ fplibFixedToFP()

template<>
uint64_t ArmISA::fplibFixedToFP ( uint64_t  op,
int  fbits,
bool  u,
FPRounding  rounding,
FPSCR &  fpscr 
)

Floating-point convert from fixed-point.

Definition at line 4963 of file fplib.cc.

References fp16_cvtf(), X86ISA::op, set_fpscr0(), and u.

◆ fplibFPToFixed() [1/4]

template<class T1 , class T2 >
T2 ArmISA::fplibFPToFixed ( T1  op,
int  fbits,
bool  u,
FPRounding  rounding,
FPSCR &  fpscr 
)

Floating-point convert to fixed-point.

◆ fplibFPToFixed() [2/4]

template<>
uint64_t ArmISA::fplibFPToFixed ( uint16_t  op,
int  fbits,
bool  u,
FPRounding  rounding,
FPSCR &  fpscr 
)

◆ fplibFPToFixed() [3/4]

template<>
uint64_t ArmISA::fplibFPToFixed ( uint32_t  op,
int  fbits,
bool  u,
FPRounding  rounding,
FPSCR &  fpscr 
)

◆ fplibFPToFixed() [4/4]

template<>
uint64_t ArmISA::fplibFPToFixed ( uint64_t  op,
int  fbits,
bool  u,
FPRounding  rounding,
FPSCR &  fpscr 
)

◆ fplibFPToFixedJS()

uint32_t ArmISA::fplibFPToFixedJS ( uint64_t  op,
FPSCR &  fpscr,
bool  is64,
uint8_t &  nz 
)

Floating-point JS convert to a signed integer, with rounding to zero.

Definition at line 4752 of file fplib.cc.

References bits(), err, FP32_BITS, FP64_BITS, FP64_EXP_BIAS, FP64_MANT_BITS, FPLIB_IDC, FPLIB_IOC, FPLIB_IXC, lsl64(), lsr64(), nz, X86ISA::op, set_fpscr0(), and ULL.

◆ fplibInfinity()

template<>
uint64_t ArmISA::fplibInfinity ( int  sgn)

Floating-point value for +/- infinity.

Definition at line 5000 of file fplib.cc.

References fp16_infinity().

◆ fplibMax() [1/4]

template<class T >
T ArmISA::fplibMax ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point maximum.

◆ fplibMax() [2/4]

template<>
uint16_t ArmISA::fplibMax ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

◆ fplibMax() [3/4]

template<>
uint32_t ArmISA::fplibMax ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

◆ fplibMax() [4/4]

template<>
uint64_t ArmISA::fplibMax ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

◆ fplibMaxNum() [1/4]

template<class T >
T ArmISA::fplibMaxNum ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point maximum number.

◆ fplibMaxNum() [2/4]

template<>
uint16_t ArmISA::fplibMaxNum ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 3248 of file fplib.cc.

References fp16_minmaxnum().

◆ fplibMaxNum() [3/4]

template<>
uint32_t ArmISA::fplibMaxNum ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 3256 of file fplib.cc.

References fp32_minmaxnum().

◆ fplibMaxNum() [4/4]

template<>
uint64_t ArmISA::fplibMaxNum ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 3264 of file fplib.cc.

References fp64_minmaxnum().

◆ fplibMin() [1/4]

template<class T >
T ArmISA::fplibMin ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point minimum.

◆ fplibMin() [2/4]

template<>
uint16_t ArmISA::fplibMin ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

◆ fplibMin() [3/4]

template<>
uint32_t ArmISA::fplibMin ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

◆ fplibMin() [4/4]

template<>
uint64_t ArmISA::fplibMin ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

◆ fplibMinNum() [1/4]

template<class T >
T ArmISA::fplibMinNum ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point minimum number.

◆ fplibMinNum() [2/4]

template<>
uint16_t ArmISA::fplibMinNum ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 3341 of file fplib.cc.

References fp16_minmaxnum().

◆ fplibMinNum() [3/4]

template<>
uint32_t ArmISA::fplibMinNum ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 3349 of file fplib.cc.

References fp32_minmaxnum().

◆ fplibMinNum() [4/4]

template<>
uint64_t ArmISA::fplibMinNum ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 3357 of file fplib.cc.

References fp64_minmaxnum().

◆ fplibMul() [1/4]

template<class T >
T ArmISA::fplibMul ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point multiply.

◆ fplibMul() [2/4]

template<>
uint16_t ArmISA::fplibMul ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 3365 of file fplib.cc.

References fp16_mul(), modeConv(), and set_fpscr0().

◆ fplibMul() [3/4]

template<>
uint32_t ArmISA::fplibMul ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 3375 of file fplib.cc.

References fp32_mul(), modeConv(), and set_fpscr0().

◆ fplibMul() [4/4]

template<>
uint64_t ArmISA::fplibMul ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 3385 of file fplib.cc.

References fp64_mul(), modeConv(), and set_fpscr0().

◆ fplibMulAdd() [1/4]

template<class T >
T ArmISA::fplibMulAdd ( addend,
op1,
op2,
FPSCR &  fpscr 
)

Floating-point multiply-add.

◆ fplibMulAdd() [2/4]

template<>
uint16_t ArmISA::fplibMulAdd ( uint16_t  addend,
uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 2875 of file fplib.cc.

References fp16_muladd(), modeConv(), and set_fpscr0().

◆ fplibMulAdd() [3/4]

template<>
uint32_t ArmISA::fplibMulAdd ( uint32_t  addend,
uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 2885 of file fplib.cc.

References fp32_muladd(), modeConv(), and set_fpscr0().

◆ fplibMulAdd() [4/4]

template<>
uint64_t ArmISA::fplibMulAdd ( uint64_t  addend,
uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 2895 of file fplib.cc.

References fp64_muladd(), modeConv(), and set_fpscr0().

◆ fplibMulX() [1/4]

template<class T >
T ArmISA::fplibMulX ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point multiply extended.

◆ fplibMulX() [2/4]

template<>
uint16_t ArmISA::fplibMulX ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

◆ fplibMulX() [3/4]

template<>
uint32_t ArmISA::fplibMulX ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

◆ fplibMulX() [4/4]

template<>
uint64_t ArmISA::fplibMulX ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

◆ fplibNeg() [1/4]

template<class T >
T ArmISA::fplibNeg ( op)

Floating-point negate.

◆ fplibNeg() [2/4]

template<>
uint16_t ArmISA::fplibNeg ( uint16_t  op)

Definition at line 3488 of file fplib.cc.

References FP16_BITS, X86ISA::op, and ULL.

◆ fplibNeg() [3/4]

template<>
uint32_t ArmISA::fplibNeg ( uint32_t  op)

Definition at line 3495 of file fplib.cc.

References FP32_BITS, X86ISA::op, and ULL.

◆ fplibNeg() [4/4]

template<>
uint64_t ArmISA::fplibNeg ( uint64_t  op)

Definition at line 3502 of file fplib.cc.

References FP64_BITS, X86ISA::op, and ULL.

◆ fplibRecipEstimate() [1/4]

template<class T >
T ArmISA::fplibRecipEstimate ( op,
FPSCR &  fpscr 
)

Floating-point reciprocal estimate.

◆ fplibRecipEstimate() [2/4]

template<>
uint16_t ArmISA::fplibRecipEstimate ( uint16_t  op,
FPSCR &  fpscr 
)

◆ fplibRecipEstimate() [3/4]

template<>
uint32_t ArmISA::fplibRecipEstimate ( uint32_t  op,
FPSCR &  fpscr 
)

◆ fplibRecipEstimate() [4/4]

template<>
uint64_t ArmISA::fplibRecipEstimate ( uint64_t  op,
FPSCR &  fpscr 
)

◆ fplibRecipStepFused() [1/4]

template<class T >
T ArmISA::fplibRecipStepFused ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point reciprocal step.

◆ fplibRecipStepFused() [2/4]

template<>
uint16_t ArmISA::fplibRecipStepFused ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

◆ fplibRecipStepFused() [3/4]

template<>
uint32_t ArmISA::fplibRecipStepFused ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

◆ fplibRecipStepFused() [4/4]

template<>
uint64_t ArmISA::fplibRecipStepFused ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

◆ fplibRecpX() [1/4]

template<class T >
T ArmISA::fplibRecpX ( op,
FPSCR &  fpscr 
)

Floating-point reciprocal exponent.

◆ fplibRecpX() [2/4]

template<>
uint16_t ArmISA::fplibRecpX ( uint16_t  op,
FPSCR &  fpscr 
)

◆ fplibRecpX() [3/4]

template<>
uint32_t ArmISA::fplibRecpX ( uint32_t  op,
FPSCR &  fpscr 
)

◆ fplibRecpX() [4/4]

template<>
uint64_t ArmISA::fplibRecpX ( uint64_t  op,
FPSCR &  fpscr 
)

◆ fplibRoundInt() [1/4]

template<class T >
T ArmISA::fplibRoundInt ( op,
FPRounding  rounding,
bool  exact,
FPSCR &  fpscr 
)

Floating-point convert to integer.

◆ fplibRoundInt() [2/4]

template<>
uint16_t ArmISA::fplibRoundInt ( uint16_t  op,
FPRounding  rounding,
bool  exact,
FPSCR &  fpscr 
)

◆ fplibRoundInt() [3/4]

template<>
uint32_t ArmISA::fplibRoundInt ( uint32_t  op,
FPRounding  rounding,
bool  exact,
FPSCR &  fpscr 
)

◆ fplibRoundInt() [4/4]

template<>
uint64_t ArmISA::fplibRoundInt ( uint64_t  op,
FPRounding  rounding,
bool  exact,
FPSCR &  fpscr 
)

◆ fplibRSqrtEstimate() [1/4]

template<class T >
T ArmISA::fplibRSqrtEstimate ( op,
FPSCR &  fpscr 
)

Floating-point reciprocal square root estimate.

◆ fplibRSqrtEstimate() [2/4]

template<>
uint16_t ArmISA::fplibRSqrtEstimate ( uint16_t  op,
FPSCR &  fpscr 
)

◆ fplibRSqrtEstimate() [3/4]

template<>
uint32_t ArmISA::fplibRSqrtEstimate ( uint32_t  op,
FPSCR &  fpscr 
)

◆ fplibRSqrtEstimate() [4/4]

template<>
uint64_t ArmISA::fplibRSqrtEstimate ( uint64_t  op,
FPSCR &  fpscr 
)

◆ fplibRSqrtStepFused() [1/4]

template<class T >
T ArmISA::fplibRSqrtStepFused ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point reciprocal square root step.

◆ fplibRSqrtStepFused() [2/4]

template<>
uint16_t ArmISA::fplibRSqrtStepFused ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

◆ fplibRSqrtStepFused() [3/4]

template<>
uint32_t ArmISA::fplibRSqrtStepFused ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

◆ fplibRSqrtStepFused() [4/4]

template<>
uint64_t ArmISA::fplibRSqrtStepFused ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

◆ fplibScale() [1/4]

template<class T >
T ArmISA::fplibScale ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point adjust exponent.

◆ fplibScale() [2/4]

template<>
uint16_t ArmISA::fplibScale ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 4275 of file fplib.cc.

References fp16_scale(), modeConv(), and set_fpscr0().

◆ fplibScale() [3/4]

template<>
uint32_t ArmISA::fplibScale ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 4285 of file fplib.cc.

References fp32_scale(), modeConv(), and set_fpscr0().

◆ fplibScale() [4/4]

template<>
uint64_t ArmISA::fplibScale ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 4295 of file fplib.cc.

References fp64_scale(), modeConv(), and set_fpscr0().

◆ fplibSqrt() [1/4]

template<class T >
T ArmISA::fplibSqrt ( op,
FPSCR &  fpscr 
)

Floating-point square root.

◆ fplibSqrt() [2/4]

template<>
uint16_t ArmISA::fplibSqrt ( uint16_t  op,
FPSCR &  fpscr 
)

Definition at line 4305 of file fplib.cc.

References fp16_sqrt(), modeConv(), X86ISA::op, and set_fpscr0().

◆ fplibSqrt() [3/4]

template<>
uint32_t ArmISA::fplibSqrt ( uint32_t  op,
FPSCR &  fpscr 
)

Definition at line 4315 of file fplib.cc.

References fp32_sqrt(), modeConv(), X86ISA::op, and set_fpscr0().

◆ fplibSqrt() [4/4]

template<>
uint64_t ArmISA::fplibSqrt ( uint64_t  op,
FPSCR &  fpscr 
)

Definition at line 4325 of file fplib.cc.

References fp64_sqrt(), modeConv(), X86ISA::op, and set_fpscr0().

◆ fplibSub() [1/4]

template<class T >
T ArmISA::fplibSub ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point subtract.

◆ fplibSub() [2/4]

template<>
uint16_t ArmISA::fplibSub ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 4335 of file fplib.cc.

References fp16_add(), modeConv(), and set_fpscr0().

◆ fplibSub() [3/4]

template<>
uint32_t ArmISA::fplibSub ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 4345 of file fplib.cc.

References fp32_add(), modeConv(), and set_fpscr0().

◆ fplibSub() [4/4]

template<>
uint64_t ArmISA::fplibSub ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 4355 of file fplib.cc.

References fp64_add(), modeConv(), and set_fpscr0().

◆ fplibTrigMulAdd() [1/4]

template<class T >
T ArmISA::fplibTrigMulAdd ( uint8_t  coeff_index,
op1,
op2,
FPSCR &  fpscr 
)

Floating-point trigonometric multiply-add coefficient.

◆ fplibTrigMulAdd() [2/4]

template<>
uint16_t ArmISA::fplibTrigMulAdd ( uint8_t  coeff_index,
uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 4365 of file fplib.cc.

References FP16_BITS, fp16_muladd(), fplibAbs(), modeConv(), and set_fpscr0().

◆ fplibTrigMulAdd() [3/4]

template<>
uint32_t ArmISA::fplibTrigMulAdd ( uint8_t  coeff_index,
uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 4399 of file fplib.cc.

References FP32_BITS, fp32_muladd(), fplibAbs(), modeConv(), and set_fpscr0().

◆ fplibTrigMulAdd() [4/4]

template<>
uint64_t ArmISA::fplibTrigMulAdd ( uint8_t  coeff_index,
uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 4433 of file fplib.cc.

References FP64_BITS, fp64_muladd(), fplibAbs(), modeConv(), set_fpscr0(), and ULL.

◆ fplibTrigSMul() [1/4]

template<class T >
T ArmISA::fplibTrigSMul ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point trigonometric starting value.

◆ fplibTrigSMul() [2/4]

template<>
uint16_t ArmISA::fplibTrigSMul ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 4467 of file fplib.cc.

References FP16_BITS, fp16_is_NaN(), fp16_mul(), fp16_unpack(), mode, modeConv(), set_fpscr0(), and ULL.

◆ fplibTrigSMul() [3/4]

template<>
uint32_t ArmISA::fplibTrigSMul ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 4487 of file fplib.cc.

References FP32_BITS, fp32_is_NaN(), fp32_mul(), fp32_unpack(), mode, modeConv(), set_fpscr0(), and ULL.

◆ fplibTrigSMul() [4/4]

template<>
uint64_t ArmISA::fplibTrigSMul ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 4506 of file fplib.cc.

References FP64_BITS, fp64_is_NaN(), fp64_mul(), fp64_unpack(), mode, modeConv(), set_fpscr0(), and ULL.

◆ fplibTrigSSel() [1/4]

template<class T >
T ArmISA::fplibTrigSSel ( op1,
op2,
FPSCR &  fpscr 
)

Floating-point trigonometric select coefficient.

◆ fplibTrigSSel() [2/4]

template<>
uint16_t ArmISA::fplibTrigSSel ( uint16_t  op1,
uint16_t  op2,
FPSCR &  fpscr 
)

Definition at line 4525 of file fplib.cc.

References FP16_BITS, FP16_EXP_BIAS, and FP16_MANT_BITS.

◆ fplibTrigSSel() [3/4]

template<>
uint32_t ArmISA::fplibTrigSSel ( uint32_t  op1,
uint32_t  op2,
FPSCR &  fpscr 
)

Definition at line 4536 of file fplib.cc.

References FP32_BITS, FP32_EXP_BIAS, and FP32_MANT_BITS.

◆ fplibTrigSSel() [4/4]

template<>
uint64_t ArmISA::fplibTrigSSel ( uint64_t  op1,
uint64_t  op2,
FPSCR &  fpscr 
)

Definition at line 4547 of file fplib.cc.

References FP64_BITS, FP64_EXP_BIAS, and FP64_MANT_BITS.

◆ fpMax()

template<typename T >
static T ArmISA::fpMax ( a,
b 
)
inlinestatic

Definition at line 637 of file vfp.hh.

References a, and b.

◆ fpMaxNum()

template<typename T >
static T ArmISA::fpMaxNum ( a,
b 
)
inlinestatic

Definition at line 620 of file vfp.hh.

References a, b, fpToBits(), and ULL.

◆ fpMin()

template<typename T >
static T ArmISA::fpMin ( a,
b 
)
inlinestatic

Definition at line 665 of file vfp.hh.

References a, and b.

◆ fpMinNum()

template<typename T >
static T ArmISA::fpMinNum ( a,
b 
)
inlinestatic

Definition at line 648 of file vfp.hh.

References a, b, fpToBits(), and ULL.

◆ fpMul()

template<typename T >
static T ArmISA::fpMul ( a,
b 
)
inlinestatic

Definition at line 567 of file vfp.hh.

References a, and b.

◆ fpMulAdd()

template<typename T >
static T ArmISA::fpMulAdd ( op1,
op2,
addend 
)
inlinestatic

Definition at line 587 of file vfp.hh.

References bitsToFp(), fpToBits(), and ULL.

◆ fpMulD()

static double ArmISA::fpMulD ( double  a,
double  b 
)
inlinestatic

Definition at line 579 of file vfp.hh.

References a, and b.

◆ fpMulS()

static float ArmISA::fpMulS ( float  a,
float  b 
)
inlinestatic

Definition at line 573 of file vfp.hh.

References a, and b.

◆ fpMulX()

template<typename T >
static T ArmISA::fpMulX ( a,
b 
)
inlinestatic

Definition at line 533 of file vfp.hh.

References a, b, and fpToBits().

◆ fpRecipEstimate()

float ArmISA::fpRecipEstimate ( FPSCR &  fpscr,
float  op 
)

Definition at line 850 of file vfp.cc.

References bits(), bitsToFp(), fpToBits(), X86ISA::op, recipEstimate(), and ULL.

◆ fpRecps()

template<typename T >
static T ArmISA::fpRecps ( a,
b 
)
inlinestatic

Definition at line 698 of file vfp.hh.

References a, b, and FeUnderflow.

◆ fpRecpsS()

static float ArmISA::fpRecpsS ( float  a,
float  b 
)
inlinestatic

Definition at line 741 of file vfp.hh.

References a, b, and FeUnderflow.

◆ fpRIntX()

template<typename T >
static T ArmISA::fpRIntX ( a,
FPSCR &  fpscr 
)
inlinestatic

Definition at line 608 of file vfp.hh.

References a.

◆ fprSqrtEstimate()

float ArmISA::fprSqrtEstimate ( FPSCR &  fpscr,
float  op 
)

Definition at line 768 of file vfp.cc.

References bits(), bitsToFp(), fpToBits(), X86ISA::op, recipSqrtEstimate(), and ULL.

◆ fpRSqrts()

template<typename T >
static T ArmISA::fpRSqrts ( a,
b 
)
inlinestatic

Definition at line 676 of file vfp.hh.

References a, b, and FeUnderflow.

◆ fpRSqrtsS()

static float ArmISA::fpRSqrtsS ( float  a,
float  b 
)
inlinestatic

Definition at line 720 of file vfp.hh.

References a, b, and FeUnderflow.

◆ fpStandardFPSCRValue()

FPSCR ArmISA::fpStandardFPSCRValue ( const FPSCR &  fpscr)

Definition at line 902 of file vfp.cc.

◆ fpSub()

template<typename T >
static T ArmISA::fpSub ( a,
b 
)
inlinestatic

Definition at line 483 of file vfp.hh.

References a, and b.

◆ fpSubD()

static double ArmISA::fpSubD ( double  a,
double  b 
)
inlinestatic

Definition at line 507 of file vfp.hh.

References a, and b.

◆ fpSubS()

static float ArmISA::fpSubS ( float  a,
float  b 
)
inlinestatic

Definition at line 501 of file vfp.hh.

References a, and b.

◆ fpToBits() [1/2]

static uint64_t ArmISA::fpToBits ( double  fp)
inlinestatic

Definition at line 166 of file vfp.hh.

References bits(), fp, and X86ISA::val.

◆ fpToBits() [2/2]

static uint32_t ArmISA::fpToBits ( float  fp)
inlinestatic

◆ FPToFixed_16()

static uint16_t ArmISA::FPToFixed_16 ( int  sgn,
int  exp,
uint64_t  mnt,
bool  u,
FPRounding  rounding,
int *  flags 
)
static

Definition at line 4620 of file fplib.cc.

References FP16_BITS, FPLIB_IOC, FPToFixed_64(), u, ULL, and RiscvISA::x.

Referenced by fplibFPToFixed().

◆ FPToFixed_32()

static uint32_t ArmISA::FPToFixed_32 ( int  sgn,
int  exp,
uint64_t  mnt,
bool  u,
FPRounding  rounding,
int *  flags 
)
static

Definition at line 4606 of file fplib.cc.

References FP32_BITS, FPLIB_IOC, FPToFixed_64(), u, ULL, and RiscvISA::x.

Referenced by fplibFPToFixed().

◆ FPToFixed_64()

static uint64_t ArmISA::FPToFixed_64 ( int  sgn,
int  exp,
uint64_t  mnt,
bool  u,
FPRounding  rounding,
int *  flags 
)
static

◆ getAff0()

static RegVal ArmISA::getAff0 ( ArmSystem arm_sys,
ThreadContext tc 
)
static

Definition at line 306 of file utility.cc.

References ThreadContext::cpuId(), System::multiThread, and ThreadContext::threadId().

Referenced by getAffinity().

◆ getAff1()

static RegVal ArmISA::getAff1 ( ArmSystem arm_sys,
ThreadContext tc 
)
static

Definition at line 300 of file utility.cc.

References ThreadContext::cpuId(), System::multiThread, and ThreadContext::socketId().

Referenced by getAffinity().

◆ getAff2()

static RegVal ArmISA::getAff2 ( ArmSystem arm_sys,
ThreadContext tc 
)
static

Definition at line 294 of file utility.cc.

References System::multiThread, and ThreadContext::socketId().

Referenced by getAffinity().

◆ getAffinity()

RegVal ArmISA::getAffinity ( ArmSystem arm_sys,
ThreadContext tc 
)

Retrieves MPIDR_EL1.

{Aff2,Aff1,Aff0} affinity numbers

Definition at line 312 of file utility.cc.

References getAff0(), getAff1(), and getAff2().

Referenced by getMPIDR(), and FVPBasePwrCtrl::getThreadContextByMPID().

◆ getArgument()

uint64_t ArmISA::getArgument ( ThreadContext tc,
int &  number,
uint16_t  size,
bool  fp 
)

◆ getDTBPtr()

template<typename T >
TLB* ArmISA::getDTBPtr ( T *  tc)

◆ getExecutingAsid()

uint64_t ArmISA::getExecutingAsid ( ThreadContext tc)
inline

Definition at line 414 of file utility.hh.

References MISCREG_CONTEXTIDR, and ThreadContext::readMiscReg().

Referenced by Trace::ExeTracerRecord::traceInst().

◆ getFaultVAddr()

bool ArmISA::getFaultVAddr ( Fault  fault,
Addr va 
)

Returns true if the fault passed as a first argument was triggered by a memory access, false otherwise.

If true it is storing the faulting address in the va argument

Parameters
faultgenerated fault
vafunction will modify this passed-by-reference parameter with the correct faulting virtual address
Returns
true if va contains a valid value, false otherwise

Definition at line 1828 of file faults.cc.

References ArmISA::ArmFault::getFaultVAddr(), and va.

◆ getITBPtr()

template<typename T >
TLB* ArmISA::getITBPtr ( T *  tc)

◆ getMPIDR()

RegVal ArmISA::getMPIDR ( ArmSystem arm_sys,
ThreadContext tc 
)

This helper function is returning the value of MPIDR_EL1.

Definition at line 264 of file utility.cc.

References ThreadContext::cpuId(), getAffinity(), ArmSystem::multiProc, System::multiThread, replaceBits(), and ThreadContext::socketId().

Referenced by Gicv3Redistributor::getAffinity(), ArmISA::Reset::invoke(), and readMPIDR().

◆ getRestoredITBits()

static uint8_t ArmISA::getRestoredITBits ( ThreadContext tc,
CPSR  spsr 
)
static

◆ globalClearExclusive()

template<class XC >
void ArmISA::globalClearExclusive ( XC *  xc)
inline

◆ handleLockedRead()

template<class XC >
void ArmISA::handleLockedRead ( XC *  xc,
const RequestPtr req 
)
inline

◆ handleLockedSnoop()

template<class XC >
void ArmISA::handleLockedSnoop ( XC *  xc,
PacketPtr  pkt,
Addr  cacheBlockMask 
)
inline

◆ handleLockedSnoopHit()

template<class XC >
void ArmISA::handleLockedSnoopHit ( XC *  xc)
inline

Definition at line 101 of file locked_mem.hh.

References DPRINTF, MISCREG_LOCKADDR, MISCREG_LOCKFLAG, and MISCREG_SEV_MAILBOX.

Referenced by LSQUnit< Impl >::checkSnoop().

◆ handleLockedWrite()

template<class XC >
bool ArmISA::handleLockedWrite ( XC *  xc,
const RequestPtr req,
Addr  cacheBlockMask 
)
inline

◆ haveAArch32EL()

bool ArmISA::haveAArch32EL ( ThreadContext tc,
ExceptionLevel  el 
)

Definition at line 409 of file utility.cc.

References el, EL0, ArmSystem::haveEL(), ArmSystem::highestEL(), and ArmSystem::highestELIs64().

Referenced by ELStateUsingAArch32K().

◆ HavePACExt()

bool ArmISA::HavePACExt ( ThreadContext tc)

Definition at line 318 of file utility.cc.

References MISCREG_ID_AA64ISAR1_EL1, and ThreadContext::readMiscReg().

◆ HaveSecureEL2Ext()

bool ArmISA::HaveSecureEL2Ext ( ThreadContext tc)

◆ HaveVirtHostExt()

bool ArmISA::HaveVirtHostExt ( ThreadContext tc)

◆ highFromDouble()

static uint32_t ArmISA::highFromDouble ( double  val)
inlinestatic

Definition at line 250 of file vfp.hh.

References fpToBits(), and X86ISA::val.

◆ illegalExceptionReturn()

static bool ArmISA::illegalExceptionReturn ( ThreadContext tc,
CPSR  cpsr,
CPSR  spsr 
)
static

◆ inAArch64()

bool ArmISA::inAArch64 ( ThreadContext tc)

◆ inPrivilegedMode() [1/2]

static bool ArmISA::inPrivilegedMode ( CPSR  cpsr)
inlinestatic

Definition at line 120 of file utility.hh.

References inUserMode().

◆ inPrivilegedMode() [2/2]

static bool ArmISA::inPrivilegedMode ( ThreadContext tc)
inlinestatic

Definition at line 126 of file utility.hh.

References inUserMode().

◆ inSecureState()

static bool ArmISA::inSecureState ( SCR  scr,
CPSR  cpsr 
)
inlinestatic

◆ INTREG_ABT()

static IntRegIndex ArmISA::INTREG_ABT ( unsigned  index)
inlinestatic

◆ INTREG_FIQ()

static IntRegIndex ArmISA::INTREG_FIQ ( unsigned  index)
inlinestatic

◆ INTREG_HYP()

static IntRegIndex ArmISA::INTREG_HYP ( unsigned  index)
inlinestatic

◆ INTREG_IRQ()

static IntRegIndex ArmISA::INTREG_IRQ ( unsigned  index)
inlinestatic

◆ INTREG_MON()

static IntRegIndex ArmISA::INTREG_MON ( unsigned  index)
inlinestatic

◆ INTREG_SVC()

static IntRegIndex ArmISA::INTREG_SVC ( unsigned  index)
inlinestatic

◆ INTREG_UND()

static IntRegIndex ArmISA::INTREG_UND ( unsigned  index)
inlinestatic

◆ INTREG_USR()

static IntRegIndex ArmISA::INTREG_USR ( unsigned  index)
inlinestatic

◆ intRegInMode()

static int ArmISA::intRegInMode ( OperatingMode  mode,
int  reg 
)
inlinestatic

Definition at line 462 of file intregs.hh.

References intRegsPerMode, mode, NUM_ARCH_INTREGS, and X86ISA::reg.

Referenced by decodeMrsMsrBankedReg(), and ArmISA::MacroMemOp::MacroMemOp().

◆ inUserMode() [1/2]

static bool ArmISA::inUserMode ( CPSR  cpsr)
inlinestatic

Definition at line 108 of file utility.hh.

References MODE_EL0T, and MODE_USER.

Referenced by inPrivilegedMode(), inUserMode(), and Trace::ExeTracerRecord::traceInst().

◆ inUserMode() [2/2]

static bool ArmISA::inUserMode ( ThreadContext tc)
inlinestatic

Definition at line 114 of file utility.hh.

References inUserMode(), MISCREG_CPSR, and ThreadContext::readMiscRegNoEffect().

◆ isAArch64AArch32SystemAccessTrapEL1()

bool ArmISA::isAArch64AArch32SystemAccessTrapEL1 ( const MiscRegIndex  miscReg,
ThreadContext tc 
)

◆ isAArch64AArch32SystemAccessTrapEL2()

bool ArmISA::isAArch64AArch32SystemAccessTrapEL2 ( const MiscRegIndex  miscReg,
ThreadContext tc 
)

◆ isBigEndian64()

bool ArmISA::isBigEndian64 ( const ThreadContext tc)

◆ isGenericTimerCommonEL0HypTrap()

bool ArmISA::isGenericTimerCommonEL0HypTrap ( const MiscRegIndex  miscReg,
ThreadContext tc,
ExceptionClass ec 
)

◆ isGenericTimerCommonEL0SystemAccessTrapEL2()

bool ArmISA::isGenericTimerCommonEL0SystemAccessTrapEL2 ( const MiscRegIndex  miscReg,
ThreadContext tc 
)

◆ isGenericTimerHypTrap()

bool ArmISA::isGenericTimerHypTrap ( const MiscRegIndex  miscReg,
ThreadContext tc,
ExceptionClass ec 
)

◆ isGenericTimerPhysEL0SystemAccessTrapEL2()

bool ArmISA::isGenericTimerPhysEL0SystemAccessTrapEL2 ( const MiscRegIndex  miscReg,
ThreadContext tc 
)

◆ isGenericTimerPhysEL1SystemAccessTrapEL2()

bool ArmISA::isGenericTimerPhysEL1SystemAccessTrapEL2 ( const MiscRegIndex  miscReg,
ThreadContext tc 
)

◆ isGenericTimerPhysHypTrap()

bool ArmISA::isGenericTimerPhysHypTrap ( const MiscRegIndex  miscReg,
ThreadContext tc,
ExceptionClass ec 
)

Definition at line 953 of file utility.cc.

References condGenericTimerPhysHypTrap().

Referenced by isGenericTimerHypTrap().

◆ isGenericTimerSystemAccessTrapEL1()

bool ArmISA::isGenericTimerSystemAccessTrapEL1 ( const MiscRegIndex  miscReg,
ThreadContext tc 
)

◆ isGenericTimerSystemAccessTrapEL2()

bool ArmISA::isGenericTimerSystemAccessTrapEL2 ( const MiscRegIndex  miscReg,
ThreadContext tc 
)

◆ isGenericTimerSystemAccessTrapEL3()

bool ArmISA::isGenericTimerSystemAccessTrapEL3 ( const MiscRegIndex  miscReg,
ThreadContext tc 
)

◆ isGenericTimerVirtSystemAccessTrapEL2()

bool ArmISA::isGenericTimerVirtSystemAccessTrapEL2 ( const MiscRegIndex  miscReg,
ThreadContext tc 
)

◆ isSecure()

bool ArmISA::isSecure ( ThreadContext tc)

◆ isSecureBelowEL3()

bool ArmISA::isSecureBelowEL3 ( ThreadContext tc)

◆ IsSecureEL2Enabled()

bool ArmISA::IsSecureEL2Enabled ( ThreadContext tc)

◆ isSnan()

template<class fpType >
static bool ArmISA::isSnan ( fpType  val)
inlinestatic

Definition at line 203 of file vfp.hh.

References fpToBits(), ULL, and X86ISA::val.

◆ isSP()

static bool ArmISA::isSP ( IntRegIndex  reg)
inlinestatic

◆ isUnpriviledgeAccess()

bool ArmISA::isUnpriviledgeAccess ( ThreadContext tc)

◆ itState()

static uint8_t ArmISA::itState ( CPSR  psr)
inlinestatic

Definition at line 220 of file utility.hh.

Referenced by getRestoredITBits(), and Iris::ThreadContext::pcState().

◆ longDescFormatInUse()

bool ArmISA::longDescFormatInUse ( ThreadContext tc)

◆ lowFromDouble()

static uint32_t ArmISA::lowFromDouble ( double  val)
inlinestatic

Definition at line 244 of file vfp.hh.

References fpToBits(), and X86ISA::val.

◆ lsl128()

static void ArmISA::lsl128 ( uint64_t *  r0,
uint64_t *  r1,
uint64_t  x0,
uint64_t  x1,
uint32_t  shift 
)
inlinestatic

Definition at line 131 of file fplib.cc.

References MipsISA::r0, and shift.

Referenced by fp64_muladd(), and fp64_sqrt().

◆ lsl16()

static uint16_t ArmISA::lsl16 ( uint16_t  x,
uint32_t  shift 
)
inlinestatic

Definition at line 95 of file fplib.cc.

References shift, and RiscvISA::x.

Referenced by fp16_add(), and fp16_round_().

◆ lsl32()

static uint32_t ArmISA::lsl32 ( uint32_t  x,
uint32_t  shift 
)
inlinestatic

Definition at line 107 of file fplib.cc.

References shift, and RiscvISA::x.

Referenced by fp16_mul(), fp16_muladd(), fp32_add(), and fp32_round_().

◆ lsl64()

static uint64_t ArmISA::lsl64 ( uint64_t  x,
uint32_t  shift 
)
inlinestatic

Definition at line 119 of file fplib.cc.

References shift, and RiscvISA::x.

Referenced by fp32_mul(), fp32_muladd(), fp64_add(), fp64_round_(), fplibFPToFixedJS(), and FPToFixed_64().

◆ lsr128()

static void ArmISA::lsr128 ( uint64_t *  r0,
uint64_t *  r1,
uint64_t  x0,
uint64_t  x1,
uint32_t  shift 
)
inlinestatic

Definition at line 149 of file fplib.cc.

References MipsISA::r0, and shift.

Referenced by fp64_div(), fp64_muladd(), and fp64_sqrt().

◆ lsr16()

static uint16_t ArmISA::lsr16 ( uint16_t  x,
uint32_t  shift 
)
inlinestatic

Definition at line 101 of file fplib.cc.

References shift.

Referenced by fp16_add(), and fp16_round_().

◆ lsr32()

static uint32_t ArmISA::lsr32 ( uint32_t  x,
uint32_t  shift 
)
inlinestatic

Definition at line 113 of file fplib.cc.

References shift.

Referenced by fp16_mul(), fp16_muladd(), fp32_add(), and fp32_round_().

◆ lsr64()

static uint64_t ArmISA::lsr64 ( uint64_t  x,
uint32_t  shift 
)
inlinestatic

Definition at line 125 of file fplib.cc.

References shift.

Referenced by fp32_mul(), fp32_muladd(), fp64_add(), fp64_round_(), fplibFPToFixedJS(), and FPToFixed_64().

◆ makeDouble()

static double ArmISA::makeDouble ( uint32_t  low,
uint32_t  high 
)
inlinestatic

Definition at line 237 of file vfp.hh.

References bitsToFp().

◆ makeSP()

static IntRegIndex ArmISA::makeSP ( IntRegIndex  reg)
inlinestatic

◆ makeZero()

static IntRegIndex ArmISA::makeZero ( IntRegIndex  reg)
inlinestatic

Definition at line 507 of file intregs.hh.

References INTREG_X31, INTREG_ZERO, and X86ISA::reg.

◆ mcrMrc14TrapToHyp()

bool ArmISA::mcrMrc14TrapToHyp ( const MiscRegIndex  miscReg,
HCR  hcr,
CPSR  cpsr,
SCR  scr,
HDCR  hdcr,
HSTR  hstr,
HCPTR  hcptr,
uint32_t  iss 
)

◆ mcrMrc15Trap()

Fault ArmISA::mcrMrc15Trap ( const MiscRegIndex  miscReg,
ExtMachInst  machInst,
ThreadContext tc,
uint32_t  imm 
)

◆ mcrMrc15TrapToHyp()

bool ArmISA::mcrMrc15TrapToHyp ( const MiscRegIndex  miscReg,
ThreadContext tc,
uint32_t  iss,
ExceptionClass ec 
)

Definition at line 607 of file utility.cc.

References ec, ThreadContext::getIsaPtr(), inSecureState(), isGenericTimerHypTrap(), mcrMrcIssExtract(), MISCREG_ACTLR, MISCREG_ADFSR, MISCREG_AIDR, MISCREG_AIFSR, MISCREG_CCSIDR, MISCREG_CLIDR, MISCREG_CNTFRQ, MISCREG_CNTV_TVAL, MISCREG_CNTVCT, MISCREG_CONTEXTIDR, MISCREG_CPACR, MISCREG_CPSR, MISCREG_CSSELR, MISCREG_CTR, MISCREG_DACR, MISCREG_DCCIMVAC, MISCREG_DCCISW, MISCREG_DCCMVAC, MISCREG_DCCMVAU, MISCREG_DCCSW, MISCREG_DCIMVAC, MISCREG_DCISW, MISCREG_DFAR, MISCREG_DFSR, MISCREG_DTLBIALL, MISCREG_DTLBIASID, MISCREG_DTLBIMVA, MISCREG_HCPTR, MISCREG_HCR, MISCREG_HDCR, MISCREG_HSTR, MISCREG_ICC_ASGI1R, MISCREG_ICC_SGI0R, MISCREG_ICC_SGI1R, MISCREG_ICIALLU, MISCREG_ICIALLUIS, MISCREG_ICIMVAU, MISCREG_ID_AFR0, MISCREG_ID_DFR0, MISCREG_ID_ISAR0, MISCREG_ID_ISAR1, MISCREG_ID_ISAR2, MISCREG_ID_ISAR3, MISCREG_ID_ISAR4, MISCREG_ID_ISAR5, MISCREG_ID_MMFR0, MISCREG_ID_MMFR1, MISCREG_ID_MMFR2, MISCREG_ID_MMFR3, MISCREG_ID_PFR0, MISCREG_ID_PFR1, MISCREG_IFAR, MISCREG_IFSR, MISCREG_ITLBIALL, MISCREG_ITLBIASID, MISCREG_ITLBIMVA, MISCREG_MAIR0, MISCREG_MAIR1, MISCREG_NMRR, MISCREG_PMCR, MISCREG_PRRR, MISCREG_REVIDR, MISCREG_SCR, MISCREG_SCTLR, MISCREG_TCMTR, MISCREG_TLBIALL, MISCREG_TLBIALLIS, MISCREG_TLBIASID, MISCREG_TLBIASIDIS, MISCREG_TLBIMVA, MISCREG_TLBIMVAA, MISCREG_TLBIMVAAIS, MISCREG_TLBIMVAAL, MISCREG_TLBIMVAALIS, MISCREG_TLBIMVAIS, MISCREG_TLBIMVAL, MISCREG_TLBIMVALIS, MISCREG_TLBTR, MISCREG_TTBCR, MISCREG_TTBR0, MISCREG_TTBR1, MODE_HYP, opc2, ThreadContext::readMiscReg(), rt, and unflattenMiscReg().

Referenced by McrMrcMiscInst::execute(), McrMrcImplDefined::execute(), and mcrMrc15Trap().

◆ mcrMrcIssBuild()

static uint32_t ArmISA::mcrMrcIssBuild ( bool  isRead,
uint32_t  crm,
IntRegIndex  rt,
uint32_t  crn,
uint32_t  opc1,
uint32_t  opc2 
)
inlinestatic

Definition at line 278 of file utility.hh.

References opc2, and rt.

◆ mcrMrcIssExtract()

static void ArmISA::mcrMrcIssExtract ( uint32_t  iss,
bool &  isRead,
uint32_t &  crm,
IntRegIndex rt,
uint32_t &  crn,
uint32_t &  opc1,
uint32_t &  opc2 
)
inlinestatic

Definition at line 290 of file utility.hh.

References opc2, and rt.

Referenced by mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), and mcrrMrrc15TrapToHyp().

◆ mcrrMrrc15Trap()

Fault ArmISA::mcrrMrrc15Trap ( const MiscRegIndex  miscReg,
ExtMachInst  machInst,
ThreadContext tc,
uint32_t  imm 
)

◆ mcrrMrrc15TrapToHyp()

bool ArmISA::mcrrMrrc15TrapToHyp ( const MiscRegIndex  miscReg,
ThreadContext tc,
uint32_t  iss,
ExceptionClass ec 
)

◆ mcrrMrrcIssBuild()

static uint32_t ArmISA::mcrrMrrcIssBuild ( bool  isRead,
uint32_t  crm,
IntRegIndex  rt,
IntRegIndex  rt2,
uint32_t  opc1 
)
inlinestatic

Definition at line 302 of file utility.hh.

References rt.

◆ modeConv()

static int ArmISA::modeConv ( FPSCR  fpscr)
static

◆ modified_imm()

static uint32_t ArmISA::modified_imm ( uint8_t  ctrlImm,
uint8_t  dataImm 
)
inlinestatic

Definition at line 59 of file pred_inst.hh.

◆ msrMrs64IssBuild()

static uint32_t ArmISA::msrMrs64IssBuild ( bool  isRead,
uint32_t  op0,
uint32_t  op1,
uint32_t  crn,
uint32_t  crm,
uint32_t  op2,
IntRegIndex  rt 
)
inlinestatic

Definition at line 313 of file utility.hh.

References rt.

◆ mul62x62()

static void ArmISA::mul62x62 ( uint64_t *  x0,
uint64_t *  x1,
uint64_t  a,
uint64_t  b 
)
inlinestatic

Definition at line 167 of file fplib.cc.

References a, MipsISA::a0, a1, b, QARMA::b0, QARMA::b1, and mask.

Referenced by fp64_div(), fp64_mul(), fp64_muladd(), and fp64_sqrt().

◆ mul64x32()

static void ArmISA::mul64x32 ( uint64_t *  x0,
uint64_t *  x1,
uint64_t  a,
uint32_t  b 
)
inlinestatic

Definition at line 185 of file fplib.cc.

References a, b, t0, and t1.

Referenced by fp64_div(), and fp64_sqrt().

◆ number_of_ones()

static unsigned int ArmISA::number_of_ones ( int32_t  val)
inlinestatic

Definition at line 51 of file macromem.hh.

References i, and X86ISA::val.

Referenced by ArmISA::MacroMemOp::MacroMemOp().

◆ opModeIsH()

static bool ArmISA::opModeIsH ( OperatingMode  mode)
inlinestatic

Definition at line 723 of file types.hh.

References mode, MODE_EL1H, MODE_EL2H, and MODE_EL3H.

◆ opModeIsT()

static bool ArmISA::opModeIsT ( OperatingMode  mode)
inlinestatic

Definition at line 729 of file types.hh.

References mode, MODE_EL0T, MODE_EL1T, MODE_EL2T, and MODE_EL3T.

Referenced by ArmISA::ArmFaultVals< FastInterrupt >::offset64().

◆ opModeToEL()

static ExceptionLevel ArmISA::opModeToEL ( OperatingMode  mode)
inlinestatic

◆ prepFpState()

VfpSavedState ArmISA::prepFpState ( uint32_t  rMode)

◆ preUnflattenMiscReg()

void ArmISA::preUnflattenMiscReg ( )

◆ purifyTaggedAddr() [1/2]

Addr ArmISA::purifyTaggedAddr ( Addr  addr,
ThreadContext tc,
ExceptionLevel  el,
bool  isInstr 
)

Definition at line 576 of file utility.cc.

References addr, el, MISCREG_TCR_EL1, purifyTaggedAddr(), and ThreadContext::readMiscReg().

◆ purifyTaggedAddr() [2/2]

Addr ArmISA::purifyTaggedAddr ( Addr  addr,
ThreadContext tc,
ExceptionLevel  el,
TCR  tcr,
bool  isInstr 
)

Removes the tag from tagged addresses if that mode is enabled.

Parameters
addrThe address to be purified.
tcThe thread context.
elThe controlled exception level.
Returns
The purified address.

Definition at line 558 of file utility.cc.

References addr, bits(), computeAddrTop(), el, EL0, EL1, ELIsInHost(), and mask.

Referenced by ArmISA::TLB::checkPermissions64(), ArmISA::TLB::getTE(), ArmISA::ArmFault::invoke64(), purifyTaggedAddr(), ArmISA::TLB::translateFs(), ArmISA::TLB::translateSe(), and ArmISA::TableWalker::walk().

◆ readMPIDR()

RegVal ArmISA::readMPIDR ( ArmSystem arm_sys,
ThreadContext tc 
)

This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR), or it is issuing a read to VMPIDR_EL2 (as it happens in virtualized systems)

Definition at line 236 of file utility.cc.

References currEL(), EL0, EL1, EL2, EL3, getMPIDR(), ArmSystem::haveEL(), isSecureBelowEL3(), M5_FALLTHROUGH, MISCREG_VMPIDR_EL2, panic, ThreadContext::readMiscReg(), and warn_once.

Referenced by ArmISA::ISA::readMiscReg().

◆ readVecElem()

XReg ArmISA::readVecElem ( VReg  src,
int  index,
int  eSize 
)
inline

Read a single NEON vector element.

Definition at line 91 of file neon64_mem.hh.

References data, ArmISA::VReg::hi, MipsISA::index, and ArmISA::VReg::lo.

Referenced by FullO3CPU< O3CPUImpl >::readArchVecElem().

◆ recipEstimate()

static double ArmISA::recipEstimate ( double  a)
static

Definition at line 837 of file vfp.cc.

References a, q, MipsISA::r, and s.

Referenced by fpRecipEstimate(), and unsignedRecipEstimate().

◆ recipSqrtEstimate()

static double ArmISA::recipSqrtEstimate ( double  a)
static

Definition at line 750 of file vfp.cc.

References a, MipsISA::r, and s.

Referenced by fprSqrtEstimate(), and unsignedRSqrtEstimate().

◆ rotate_imm()

static uint32_t ArmISA::rotate_imm ( uint32_t  immValue,
uint32_t  rotateValue 
)
inlinestatic

Definition at line 51 of file pred_inst.hh.

Referenced by ArmISA::PredImmOp::PredImmOp().

◆ roundNEven()

template<typename T >
static T ArmISA::roundNEven ( a)
inlinestatic

Definition at line 763 of file vfp.hh.

References a, and X86ISA::val.

◆ roundPage()

Addr ArmISA::roundPage ( Addr  addr)

Definition at line 591 of file utility.cc.

References addr, and PageBytes.

◆ s1TranslationRegime()

ExceptionLevel ArmISA::s1TranslationRegime ( ThreadContext tc,
ExceptionLevel  el 
)

◆ sendEvent()

void ArmISA::sendEvent ( ThreadContext tc)

◆ set_fpscr()

static void ArmISA::set_fpscr ( FPSCR &  fpscr,
int  flags 
)
static

◆ set_fpscr0()

static void ArmISA::set_fpscr0 ( FPSCR &  fpscr,
int  flags 
)
static

◆ setFPExceptions()

static void ArmISA::setFPExceptions ( int  exceptions)
inlinestatic

Definition at line 256 of file vfp.hh.

References FeAllExceptions.

Referenced by vfpFpToFixed().

◆ setVfpMicroFlags()

template<class T >
static void ArmISA::setVfpMicroFlags ( VfpMicroMode  mode,
T &  flags 
)
inlinestatic

◆ simd_modified_imm()

static uint64_t ArmISA::simd_modified_imm ( bool  op,
uint8_t  cmode,
uint8_t  data,
bool &  immValid,
bool  isAarch64 = false 
)
inlinestatic

Definition at line 82 of file pred_inst.hh.

References bits(), data, i, M5_FALLTHROUGH, X86ISA::op, and ULL.

◆ snsBankedIndex() [1/2]

int ArmISA::snsBankedIndex ( MiscRegIndex  reg,
ThreadContext tc 
)

◆ snsBankedIndex() [2/2]

int ArmISA::snsBankedIndex ( MiscRegIndex  reg,
ThreadContext tc,
bool  ns 
)

◆ snsBankedIndex64()

int ArmISA::snsBankedIndex64 ( MiscRegIndex  reg,
ThreadContext tc 
)

◆ SPAlignmentCheckEnabled()

bool ArmISA::SPAlignmentCheckEnabled ( ThreadContext tc)

◆ stripPAC()

Fault ArmISA::stripPAC ( ThreadContext tc,
uint64_t  A,
bool  data,
uint64_t *  out 
)

◆ sub128()

static void ArmISA::sub128 ( uint64_t *  x0,
uint64_t *  x1,
uint64_t  a0,
uint64_t  a1,
uint64_t  b0,
uint64_t  b1 
)
inlinestatic

Definition at line 202 of file fplib.cc.

References MipsISA::a0, a1, QARMA::b0, and QARMA::b1.

Referenced by fp64_div(), and fp64_muladd().

◆ SubBitUnion()

ArmISA::SubBitUnion ( puswl  ,
24  ,
20   
)

◆ sveDecodePredCount()

unsigned int ArmISA::sveDecodePredCount ( uint8_t  imm,
unsigned int  num_elems 
)

Returns the actual number of elements active for PTRUE(S) instructions.

Parameters
imm5-bit immediate encoding the predicate pattern.
num_elemsCurrent number of elements per vector (depending on current vector length and element size).

Definition at line 864 of file sve.cc.

References imm.

◆ sveDisasmPredCountImm()

std::string ArmISA::sveDisasmPredCountImm ( uint8_t  imm)

Returns the symbolic name associated with pattern imm for PTRUE(S) instructions.

Definition at line 832 of file sve.cc.

References imm, and sc_dt::to_string().

Referenced by ArmISA::SvePtrueOp::generateDisassembly(), and ArmISA::SveElemCountOp::generateDisassembly().

◆ sveExpandFpImmAddSub()

uint64_t ArmISA::sveExpandFpImmAddSub ( uint8_t  imm,
uint8_t  size 
)

Expand 1-bit floating-point immediate to 0.5 or 1.0 (FADD, FSUB, FSUBR).

Parameters
imm1-bit immediate.
sizeEncoding of the vector element size.
Returns
Encoding of the expanded value.

Definition at line 907 of file sve.cc.

References imm, and panic.

◆ sveExpandFpImmMaxMin()

uint64_t ArmISA::sveExpandFpImmMaxMin ( uint8_t  imm,
uint8_t  size 
)

Expand 1-bit floating-point immediate to 0.0 or 1.0 (FMAX, FMAXNM, FMIN, FMINNM).

Parameters
imm1-bit immediate.
sizeEncoding of the vector element size.
Returns
Encoding of the expanded value.

Definition at line 929 of file sve.cc.

References imm, and panic.

◆ sveExpandFpImmMul()

uint64_t ArmISA::sveExpandFpImmMul ( uint8_t  imm,
uint8_t  size 
)

Expand 1-bit floating-point immediate to 0.5 or 2.0 (FMUL).

Parameters
imm1-bit immediate.
sizeEncoding of the vector element size.
Returns
Encoding of the expanded value.

Definition at line 948 of file sve.cc.

References imm, and panic.

◆ svePredTypeToStr()

const char * ArmISA::svePredTypeToStr ( SvePredType  pt)

Returns the specifier for the predication type pt as a string.

Definition at line 45 of file sve.cc.

References MERGE, and ZERO.

Referenced by ArmISA::SveBinConstrPredOp::generateDisassembly().

◆ testPredicate()

bool ArmISA::testPredicate ( uint32_t  nz,
uint32_t  c,
uint32_t  v,
ConditionCode  code 
)
inline

Definition at line 67 of file utility.hh.

References c, COND_AL, COND_CC, COND_CS, COND_EQ, COND_GE, COND_GT, COND_HI, COND_LE, COND_LS, COND_LT, COND_MI, COND_NE, COND_PL, COND_UC, COND_VC, COND_VS, n, nz, panic, v, and z.

◆ trapPACUse()

Fault ArmISA::trapPACUse ( ThreadContext tc,
ExceptionLevel  el 
)

◆ truncPage()

Addr ArmISA::truncPage ( Addr  addr)

Definition at line 585 of file utility.cc.

References addr, and PageBytes.

◆ unflattenMiscReg()

int ArmISA::unflattenMiscReg ( int  reg)

◆ unknownMode()

static bool ArmISA::unknownMode ( OperatingMode  mode)
inlinestatic

◆ unknownMode32()

static bool ArmISA::unknownMode32 ( OperatingMode  mode)
inlinestatic

◆ unsignedRecipEstimate()

uint32_t ArmISA::unsignedRecipEstimate ( uint32_t  op)

Definition at line 886 of file vfp.cc.

References bits(), bitsToFp(), fpToBits(), X86ISA::op, recipEstimate(), and ULL.

◆ unsignedRSqrtEstimate()

uint32_t ArmISA::unsignedRSqrtEstimate ( uint32_t  op)

Definition at line 811 of file vfp.cc.

References bits(), bitsToFp(), fpToBits(), X86ISA::op, recipSqrtEstimate(), and ULL.

◆ upperAndLowerRange()

bool ArmISA::upperAndLowerRange ( ThreadContext tc,
ExceptionLevel  el 
)
inline

Definition at line 53 of file pauth_helpers.hh.

References el, EL0, EL1, EL2, MISCREG_HCR_EL2, and ThreadContext::readMiscReg().

Referenced by addPAC(), calculateBottomPACBit(), and calculateTBI().

◆ vcvtFpDFpH()

uint16_t ArmISA::vcvtFpDFpH ( FPSCR &  fpscr,
bool  flush,
bool  defaultNan,
uint32_t  rMode,
bool  ahp,
double  op 
)

Definition at line 582 of file vfp.cc.

References ahp, fpToBits(), X86ISA::op, rMode, and vcvtFpFpH().

◆ vcvtFpFpH()

static uint16_t ArmISA::vcvtFpFpH ( FPSCR &  fpscr,
bool  flush,
bool  defaultNan,
uint32_t  rMode,
bool  ahp,
uint64_t  opBits,
bool  isDouble 
)
inlinestatic

Definition at line 402 of file vfp.cc.

References ahp, bits(), mask, mode, sc_dt::neg(), replaceBits(), rMode, VfpRoundDown, VfpRoundNearest, and VfpRoundUpward.

Referenced by vcvtFpDFpH(), and vcvtFpSFpH().

◆ vcvtFpHFp()

static uint64_t ArmISA::vcvtFpHFp ( FPSCR &  fpscr,
bool  defaultNan,
bool  ahp,
uint16_t  op,
bool  isDouble 
)
inlinestatic

Definition at line 590 of file vfp.cc.

References ahp, bits(), mask, sc_dt::neg(), X86ISA::op, and replaceBits().

Referenced by vcvtFpHFpD(), and vcvtFpHFpS().

◆ vcvtFpHFpD()

double ArmISA::vcvtFpHFpD ( FPSCR &  fpscr,
bool  defaultNan,
bool  ahp,
uint16_t  op 
)

Definition at line 652 of file vfp.cc.

References ahp, bitsToFp(), X86ISA::op, and vcvtFpHFp().

◆ vcvtFpHFpS()

float ArmISA::vcvtFpHFpS ( FPSCR &  fpscr,
bool  defaultNan,
bool  ahp,
uint16_t  op 
)

Definition at line 662 of file vfp.cc.

References ahp, bitsToFp(), X86ISA::op, and vcvtFpHFp().

◆ vcvtFpSFpH()

uint16_t ArmISA::vcvtFpSFpH ( FPSCR &  fpscr,
bool  flush,
bool  defaultNan,
uint32_t  rMode,
bool  ahp,
float  op 
)

Definition at line 574 of file vfp.cc.

References ahp, fpToBits(), X86ISA::op, rMode, and vcvtFpFpH().

◆ vfp_modified_imm()

static uint64_t ArmISA::vfp_modified_imm ( uint8_t  data,
FpDataType  dtype 
)
inlinestatic

Definition at line 165 of file pred_inst.hh.

References bits(), data, Fp16, Fp32, Fp64, and panic.

◆ vfpFlushToZero() [1/2]

template<class fpType >
static void ArmISA::vfpFlushToZero ( FPSCR &  fpscr,
fpType &  op 
)
inlinestatic

Definition at line 138 of file vfp.hh.

References flushToZero, and X86ISA::op.

Referenced by vfpFlushToZero().

◆ vfpFlushToZero() [2/2]

template<class fpType >
static void ArmISA::vfpFlushToZero ( FPSCR &  fpscr,
fpType &  op1,
fpType &  op2 
)
inlinestatic

Definition at line 147 of file vfp.hh.

References vfpFlushToZero().

◆ vfpFpToFixed()

template<typename T >
uint64_t ArmISA::vfpFpToFixed ( val,
bool  isSigned,
uint8_t  width,
uint8_t  imm,
bool  useRmode = true,
VfpRoundingMode  roundMode = VfpRoundZero,
bool  aarch64 = false 
)

◆ vfpSFixedToFpD()

double ArmISA::vfpSFixedToFpD ( bool  flush,
bool  defaultNan,
int64_t  val,
uint8_t  width,
uint8_t  imm 
)

Definition at line 729 of file vfp.cc.

References FeAllExceptions, FeRoundNearest, fixDivDest(), imm, mask, panic, X86ISA::scale, X86ISA::val, and width.

◆ vfpSFixedToFpS()

float ArmISA::vfpSFixedToFpS ( bool  flush,
bool  defaultNan,
int64_t  val,
uint8_t  width,
uint8_t  imm 
)

Definition at line 690 of file vfp.cc.

References FeAllExceptions, FeRoundNearest, fixDivDest(), imm, mask, panic, X86ISA::scale, X86ISA::val, and width.

◆ vfpUFixedToFpD()

double ArmISA::vfpUFixedToFpD ( bool  flush,
bool  defaultNan,
uint64_t  val,
uint8_t  width,
uint8_t  imm 
)

Definition at line 710 of file vfp.cc.

References FeAllExceptions, FeRoundNearest, fixDivDest(), imm, panic, X86ISA::scale, X86ISA::val, and width.

◆ vfpUFixedToFpS()

float ArmISA::vfpUFixedToFpS ( bool  flush,
bool  defaultNan,
uint64_t  val,
uint8_t  width,
uint8_t  imm 
)

Definition at line 672 of file vfp.cc.

References FeAllExceptions, FeRoundNearest, fixDivDest(), imm, panic, X86ISA::scale, X86ISA::val, and width.

◆ writeVecElem()

void ArmISA::writeVecElem ( VReg dest,
XReg  src,
int  index,
int  eSize 
)
inline

Write a single NEON vector element leaving the others untouched.

Definition at line 57 of file neon64_mem.hh.

References ArmISA::VReg::hi, MipsISA::index, and ArmISA::VReg::lo.

Variable Documentation

◆ a

Bitfield< 1 > ArmISA::a

Definition at line 62 of file miscregs_types.hh.

Referenced by AddrRange::addIntlvBits(), ArmISA::Crypto::aesFFMul(), ArmISA::Crypto::aesFFMul2(), sc_dt::sc_uint_subref_r::and_reduce(), sc_dt::sc_int_subref_r::and_reduce(), sc_dt::and_reduce(), sc_dt::sc_proxy< sc_bv_base >::assign_(), sc_dt::assign_v_(), SMMUv3DeviceInterface::atsRecvAtomic(), sc_dt::b_and_assign_(), sc_dt::sc_bit::b_not(), sc_dt::b_not(), sc_dt::b_xor(), Prefetcher::Base::blockAddress(), Prefetcher::Base::blockIndex(), TAGE_SC_L_TAGE::calcDep(), sc_dt::sc_lv_base::clean_tail(), MuxingKvmGic::clearBankedDistRange(), MuxingKvmGic::clearDistRange(), sc_dt::sc_concref< X, Y >::clone(), SMMUTranslationProcess::completePrefetch(), SMMUTranslationProcess::completeTransaction(), IGbE::TxDescCache::completionWriteback(), sc_dt::concat(), VMA::contains(), ChannelAddrRange::contains(), AddrRange::contains(), sc_dt::convert_to_bin(), MuxingKvmGic::copyBankedDistRange(), MuxingKvmGic::copyDistRange(), divCeil(), SMMUProcess::doDelay(), SMMUProcess::doRead(), ItsProcess::doRead(), SMMUProcess::doSleep(), SMMUProcess::doWrite(), ItsProcess::doWrite(), sc_dt::equal(), sc_dt::scfx_ieee_double::exponent(), sc_dt::extend_sign_w_(), TAGE_SC_L_TAGE::F(), fp16_add(), fp16_compare_eq(), fp16_compare_ge(), fp16_compare_gt(), fp16_compare_un(), fp16_cvtf(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_process_NaN(), fp16_process_NaNs(), fp16_process_NaNs3(), fp16_scale(), fp16_sqrt(), fp32_add(), fp32_compare_eq(), fp32_compare_ge(), fp32_compare_gt(), fp32_compare_un(), fp32_cvtf(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_process_NaN(), fp32_process_NaNs(), fp32_process_NaNs3(), fp32_scale(), fp32_sqrt(), fp64_add(), fp64_compare_eq(), fp64_compare_ge(), fp64_compare_gt(), fp64_compare_un(), fp64_cvtf(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_process_NaN(), fp64_process_NaNs(), fp64_process_NaNs3(), fp64_scale(), fp64_sqrt(), fpAdd(), fpAddD(), fpAddS(), fpDiv(), fpDivD(), fpDivS(), fplibCompareEQ(), fplibCompareGE(), fplibCompareGT(), fplibCompareUN(), fpMax(), fpMaxNum(), fpMin(), fpMinNum(), fpMul(), fpMulD(), fpMulS(), fpMulX(), fpRecps(), fpRecpsS(), fpRIntX(), fpRSqrts(), fpRSqrtsS(), fpSub(), fpSubD(), fpSubS(), Gicv2m::frameFromAddr(), sc_dt::sc_bitref_r< T >::get_word(), MultiperspectivePerceptron::ACYCLIC::getHash(), MultiperspectivePerceptron::MODHIST::getHash(), MultiperspectivePerceptron::MODPATH::getHash(), MultiperspectivePerceptron::GHISTMODPATH::getHash(), MultiperspectivePerceptron::SGHISTPATH::getHash(), AddrRange::getOffset(), MPP_TAGE::handleAllocAndUReset(), MultiperspectivePerceptron::GHIST::hash(), MultiperspectivePerceptron::MPPBranchInfo::hash1(), KernelWorkload::initState(), sc_dt::scfx_rep::is_neg(), QTIsaac< ALPHA >::isaac(), KernelWorkload::KernelWorkload(), sc_dt::sc_proxy< sc_bv_base >::lrotate(), sc_dt::lrotate(), sc_dt::lshift(), PseudoInst::m5sum(), SMMUCommandExecProcess::main(), SMMUTranslationProcess::main(), ItsCommand::main(), PowerISA::IntOp::makeCRField(), PowerISA::FloatOp::makeCRField(), Loader::MemoryImage::mask(), MathExpr::MathExpr(), mul62x62(), mul64x32(), sc_dt::nand_reduce(), sc_dt::neg(), sc_dt::scfx_ieee_double::negative(), sc_dt::scfx_ieee_float::negative(), sc_dt::nor_reduce(), Loader::MemoryImage::offset(), sc_dt::sc_logic::operator delete(), sc_dt::sc_logic::operator new(), sc_dt::operator!=(), sc_dt::operator&(), sc_dt::operator&=(), sc_dt::sc_bitref< X >::operator&=(), SNHash::operator()(), std::hash< ChannelAddr >::operator()(), ConstProxyPtr< T, Proxy >::operator+(), operator+(), sc_core::operator+(), sc_dt::operator,(), ConstProxyPtr< T, Proxy >::operator-(), sc_core::operator-(), sc_dt::operator/(), sc_dt::operator<(), operator<<(), Net::operator<<(), sc_dt::operator<<(), sc_core::operator<<(), sc_dt::operator<=(), sc_dt::sc_fxcast_switch::operator=(), sc_dt::sc_fxtype_params::operator=(), sc_dt::sc_length_param::operator=(), sc_dt::sc_bv_base::operator=(), sc_dt::scfx_ieee_double::operator=(), sc_dt::sc_lv_base::operator=(), ConstProxyPtr< T, Proxy >::operator=(), sc_dt::sc_int< W >::operator=(), sc_dt::sc_uint< W >::operator=(), sc_dt::sc_uint_subref::operator=(), sc_dt::scfx_ieee_float::operator=(), sc_dt::sc_bitref< X >::operator=(), sc_dt::sc_int_subref::operator=(), sc_dt::sc_uint_base::operator=(), sc_dt::sc_int_base::operator=(), sc_dt::sc_unsigned_subref::operator=(), sc_dt::sc_subref< X >::operator=(), sc_dt::sc_signed_subref::operator=(), sc_dt::sc_unsigned::operator=(), sc_dt::sc_signed::operator=(), sc_dt::operator==(), sc_dt::operator>(), sc_dt::operator>=(), sc_dt::sc_proxy< sc_bv_base >::operator>>(), sc_dt::operator>>(), sc_dt::operator^=(), sc_dt::operator|(), sc_dt::operator|=(), sc_dt::sc_bitref< X >::operator|=(), sc_dt::operator~(), sc_dt::sc_uint_subref_r::or_reduce(), sc_dt::sc_int_subref_r::or_reduce(), sc_dt::or_reduce(), Prefetcher::Base::pageAddress(), EmulationPageTable::pageAlign(), EmulationPageTable::pageOffset(), Prefetcher::Base::pageOffset(), IGbE::DescCache< iGbReg::RxDesc >::pciToDma(), GarnetSyntheticTraffic::printAddr(), RequestPort::printAddr(), AtomicSimpleCPU::printAddr(), TimingSimpleCPU::printAddr(), StackDistCalc::printStack(), SMMUv3::processCommands(), QTIsaac< ALPHA >::QTIsaac(), QTIsaac< ALPHA >::randinit(), recipEstimate(), recipSqrtEstimate(), SMMUv3DeviceInterface::recvAtomic(), Gicv3Its::recvReqRetry(), SMMUv3::recvReqRetry(), AddrRange::removeIntlvBits(), QTIsaac< ALPHA >::rngstep(), roundNEven(), sc_dt::sc_proxy< sc_bv_base >::rrotate(), sc_dt::rsh_scfx_rep(), sc_dt::scfx_rep::rshift(), sc_dt::rshift(), Prefetcher::Base::samePage(), sc_dt::sc_abs(), sc_dt::sc_biguint< W >::sc_biguint(), sc_dt::sc_bitref< X >::sc_bitref(), sc_dt::sc_bv< W >::sc_bv(), sc_dt::sc_bv_base::sc_bv_base(), sc_dt::sc_fxval::sc_fxval(), sc_dt::sc_fxval_fast::sc_fxval_fast(), sc_dt::sc_int< W >::sc_int(), sc_dt::sc_int_base::sc_int_base(), sc_dt::sc_lv< W >::sc_lv(), sc_dt::sc_lv_base::sc_lv_base(), sc_dt::sc_max(), sc_dt::sc_min(), SC_MODULE(), sc_dt::sc_uint< W >::sc_uint(), sc_dt::sc_uint_base::sc_uint_base(), sc_dt::sc_bitref< X >::scan(), sc_dt::sc_subref< X >::scan(), sc_dt::sc_concref< X, Y >::scan(), sc_dt::scfx_ieee_double::scfx_ieee_double(), sc_dt::scfx_ieee_float::scfx_ieee_float(), sc_dt::scfx_pow2(), sc_dt::scfx_rep::scfx_rep(), sc_dt::sc_lv_base::set_bit(), sc_dt::sc_bitref< X >::set_cword(), sc_dt::scfx_rep::set_inf(), Trace::InstRecord::setMem(), QTIsaac< ALPHA >::shuffle(), QTIsaac< ALPHA >::srand(), swap_byte(), SMMUv3::tableWalkRecvReqRetry(), ItsProcess::terminate(), TEST(), test2DVoid(), testIntVoid(), testPrepareInt(), testPrepareVoid(), testTcInit(), sc_dt::sc_proxy< sc_bv_base >::to_anything_signed(), sc_dt::sc_uint_subref_r::to_double(), sc_dt::sc_uint_subref_r::to_int(), sc_dt::sc_uint_subref_r::to_int64(), sc_dt::sc_uint_subref_r::to_long(), sc_dt::scfx_rep::to_string(), sc_dt::sc_uint_subref_r::to_string(), sc_dt::sc_int_subref_r::to_string(), sc_dt::sc_uint_subref_r::to_uint(), sc_dt::sc_uint_subref_r::to_uint64(), sc_dt::sc_uint_subref_r::to_ulong(), Trace::InstPBTrace::traceMem(), MultiperspectivePerceptron::update(), StackDistCalc::verifyStackDist(), SparcISA::TLB::writeSfsr(), sc_dt::xnor_reduce(), sc_dt::sc_uint_subref_r::xor_reduce(), sc_dt::sc_int_subref_r::xor_reduce(), sc_dt::xor_reduce(), and sc_dt::sc_lv_base::~sc_lv_base().

◆ a1

Bitfield< 22 > ArmISA::a1

Definition at line 495 of file miscregs_types.hh.

Referenced by add128(), TAGE_SC_L_TAGE::F(), mul62x62(), SC_MODULE(), and sub128().

◆ aarch64

Bitfield<34> ArmISA::aarch64

Definition at line 90 of file types.hh.

Referenced by ArmSemihosting::gatherHeapInfo(), and vfpFpToFixed().

◆ advsimd

Bitfield<23, 20> ArmISA::advsimd

Definition at line 172 of file miscregs_types.hh.

Referenced by ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32().

◆ advSimdHalfPrecision

Bitfield<23, 20> ArmISA::advSimdHalfPrecision

Definition at line 476 of file miscregs_types.hh.

◆ advSimdInteger

Bitfield<15, 12> ArmISA::advSimdInteger

Definition at line 474 of file miscregs_types.hh.

◆ advSimdLoadStore

Bitfield<11, 8> ArmISA::advSimdLoadStore

Definition at line 473 of file miscregs_types.hh.

◆ advSimdRegisters

ArmISA::advSimdRegisters

Definition at line 460 of file miscregs_types.hh.

◆ advSimdSinglePrecision

Bitfield<19, 16> ArmISA::advSimdSinglePrecision

Definition at line 475 of file miscregs_types.hh.

◆ aes

Bitfield<3, 0> ArmISA::aes

Definition at line 100 of file miscregs_types.hh.

◆ afe

Bitfield<29> ArmISA::afe

Definition at line 335 of file miscregs_types.hh.

◆ ahp

Bitfield<26> ArmISA::ahp

Definition at line 445 of file miscregs_types.hh.

Referenced by vcvtFpDFpH(), vcvtFpFpH(), vcvtFpHFp(), vcvtFpHFpD(), vcvtFpHFpS(), and vcvtFpSFpH().

◆ aif

Bitfield<8, 6> ArmISA::aif

Definition at line 65 of file miscregs_types.hh.

◆ amo

Bitfield<5> ArmISA::amo

◆ amu

Bitfield<47, 44> ArmISA::amu

Definition at line 166 of file miscregs_types.hh.

◆ apa

Bitfield<7, 4> ArmISA::apa

Definition at line 113 of file miscregs_types.hh.

◆ api

Bitfield< 17 > ArmISA::api

Definition at line 112 of file miscregs_types.hh.

◆ apk

Bitfield< 16 > ArmISA::apk

Definition at line 241 of file miscregs_types.hh.

◆ ApsrMask

const uint32_t ArmISA::ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0
static

Definition at line 2183 of file miscregs.hh.

◆ ArgumentReg0

const int ArmISA::ArgumentReg0 = 0

Definition at line 109 of file registers.hh.

Referenced by ArmProcess::argsInit().

◆ ArgumentReg1

const int ArmISA::ArgumentReg1 = 1

Definition at line 110 of file registers.hh.

Referenced by ArmProcess::argsInit().

◆ ArgumentReg2

const int ArmISA::ArgumentReg2 = 2

Definition at line 111 of file registers.hh.

Referenced by ArmProcess::argsInit().

◆ ArgumentReg3

const int ArmISA::ArgumentReg3 = 3

Definition at line 112 of file registers.hh.

◆ as

Bitfield< 36 > ArmISA::as

Definition at line 502 of file miscregs_types.hh.

◆ asedis

Bitfield<31> ArmISA::asedis

Definition at line 412 of file miscregs_types.hh.

◆ asid

ArmISA::asid

◆ asidbits

Bitfield<7, 4> ArmISA::asidbits

Definition at line 129 of file miscregs_types.hh.

◆ at

Bitfield< 44 > ArmISA::at

Definition at line 151 of file miscregs_types.hh.

Referenced by X86KvmCPU::updateThreadContextMSRs().

◆ atomic

Bitfield<23, 20> ArmISA::atomic

◆ attr

ArmISA::attr

◆ auxregs

Bitfield<27,24> ArmISA::auxregs

Definition at line 777 of file miscregs_types.hh.

◆ aw

Bitfield<5> ArmISA::aw

Definition at line 323 of file miscregs_types.hh.

◆ b

Bitfield<7> ArmISA::b

Definition at line 376 of file miscregs_types.hh.

Referenced by ArmISA::Crypto::aesFFMul(), sc_dt::sc_proxy< sc_bv_base >::assign_(), sc_dt::b_and_assign_(), sc_dt::sc_bit::b_not(), sc_dt::b_not(), sc_dt::concat(), StatisticalCorrector::condBranchUpdate(), divCeil(), MipsISA::dspAdd(), MipsISA::dspAddh(), MipsISA::dspCmp(), MipsISA::dspCmpg(), MipsISA::dspCmpgd(), MipsISA::dspDpa(), MipsISA::dspDpaq(), MipsISA::dspDps(), MipsISA::dspDpsq(), MipsISA::dspMaq(), MipsISA::dspMul(), MipsISA::dspMuleq(), MipsISA::dspMuleu(), MipsISA::dspMulq(), MipsISA::dspMulsa(), MipsISA::dspMulsaq(), MipsISA::dspPack(), MipsISA::dspPick(), MipsISA::dspPrecrq(), MipsISA::dspPrecrqu(), MipsISA::dspPrecrSra(), MipsISA::dspSub(), MipsISA::dspSubh(), BaseDynInst< Impl >::effAddrValid(), sc_gem5::Scheduler::elaborationDone(), sc_dt::equal(), AtomicOpCAS< T >::execute(), AtomicGeneric2Op< T >::execute(), AtomicGeneric3Op< T >::execute(), AtomicGenericPair3Op< T >::execute(), RiscvISA::AtomicGenericOp< T >::execute(), AtomicOpAnd< T >::execute(), AtomicOpOr< T >::execute(), AtomicOpXor< T >::execute(), AtomicOpExch< T >::execute(), AtomicOpAdd< T >::execute(), AtomicOpSub< T >::execute(), AtomicOpInc< T >::execute(), AtomicOpDec< T >::execute(), AtomicOpMax< T >::execute(), AtomicOpMin< T >::execute(), execveFunc(), sc_gem5::Port::finalize(), fp16_add(), fp16_compare_eq(), fp16_compare_ge(), fp16_compare_gt(), fp16_compare_un(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_process_NaNs(), fp16_process_NaNs3(), fp16_scale(), fp32_add(), fp32_compare_eq(), fp32_compare_ge(), fp32_compare_gt(), fp32_compare_un(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_process_NaNs(), fp32_process_NaNs3(), fp32_scale(), fp64_add(), fp64_compare_eq(), fp64_compare_ge(), fp64_compare_gt(), fp64_compare_un(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_process_NaNs(), fp64_process_NaNs3(), fp64_scale(), fpAdd(), fpAddD(), fpAddS(), fpDiv(), fpDivD(), fpDivS(), fplibCompareEQ(), fplibCompareGE(), fplibCompareGT(), fplibCompareUN(), fpMax(), fpMaxNum(), fpMin(), fpMinNum(), fpMul(), fpMulD(), fpMulS(), fpMulX(), fpRecps(), fpRecpsS(), fpRSqrts(), fpRSqrtsS(), fpSub(), fpSubD(), fpSubS(), sc_dt::sc_bitref_r< T >::get_word(), PciDevice::getBAR(), BaseRemoteGDB::getbyte(), MultiperspectivePerceptron::MODHIST::getHash(), MultiperspectivePerceptron::SGHISTPATH::getHash(), MultiperspectivePerceptron::GHIST::hash(), sc_core::sc_inout< bool >::initialize(), MultiperspectivePerceptron::ThreadData::insertRecency(), sc_dt::sc_bit::invalid_value(), QTIsaac< ALPHA >::isaac(), sc_dt::sc_proxy< sc_bv_base >::lrotate(), sc_dt::lshift(), PseudoInst::m5sum(), PowerISA::IntOp::makeCRField(), PowerISA::FloatOp::makeCRField(), MathExpr::MathExpr(), mul62x62(), mul64x32(), sc_dt::sc_logic::operator delete(), sc_dt::sc_logic::operator new(), ChannelAddr::operator!=(), sc_dt::operator!=(), ChannelAddr::operator&(), sc_dt::operator&(), sc_dt::sc_uint_bitref::operator&=(), sc_dt::sc_int_bitref::operator&=(), ChannelAddr::operator*(), ChannelAddr::operator+(), Cycles::operator+(), sc_core::operator+(), sc_dt::operator,(), ChannelAddr::operator-(), Cycles::operator-(), sc_core::operator-(), ChannelAddr::operator/(), sc_dt::operator/(), sc_dt::operator<(), ChannelAddr::operator<(), sc_core::sc_sensitive::operator<<(), ChannelAddr::operator<<(), sc_dt::operator<<(), sc_dt::operator<=(), ChannelAddr::operator<=(), sc_dt::sc_bit::operator=(), sc_dt::sc_uint_bitref::operator=(), sc_dt::sc_int_bitref::operator=(), sc_core::sc_inout< bool >::operator=(), sc_dt::sc_subref< X >::operator=(), ChannelAddr::operator==(), sc_dt::operator==(), sc_dt::operator>(), ChannelAddr::operator>(), sc_dt::operator>=(), ChannelAddr::operator>=(), ChannelAddr::operator>>(), sc_dt::operator>>(), ChannelAddr::operator^(), sc_dt::sc_uint_bitref::operator^=(), sc_dt::sc_int_bitref::operator^=(), ChannelAddr::operator|(), sc_dt::operator|(), sc_dt::sc_uint_bitref::operator|=(), sc_dt::sc_int_bitref::operator|=(), sc_dt::operator~(), QARMA::PACInvSub(), QARMA::PACSub(), Gicv3Its::pageAddress(), TAGE::predict(), LTAGE::predict(), TAGE_SC_L::predict(), DRAMInterface::Rank::processRefreshEvent(), BaseRemoteGDB::putbyte(), QTIsaac< ALPHA >::QTIsaac(), QTIsaac< ALPHA >::randinit(), NVMInterface::Rank::Rank(), QTIsaac< ALPHA >::rngstep(), sc_dt::scfx_rep::rshift(), sc_dt::rshift(), Prefetcher::Base::samePage(), sc_dt::sc_bit::sc_bit(), sc_dt::sc_max(), sc_dt::sc_min(), SC_MODULE(), sc_dt::sc_fxnum_bitref::scan(), sc_dt::sc_uint_bitref::scan(), sc_dt::sc_int_bitref::scan(), sc_dt::sc_bitref< X >::scan(), sc_dt::sc_subref< X >::scan(), sc_dt::sc_concref< X, Y >::scan(), sc_dt::scfx_rep::scfx_rep(), DRAMInterface::Rank::scheduleWakeUpEvent(), ArmISA::SelfDebug::securityStateMatch(), sc_dt::sc_bitref< X >::set_cword(), Network::setFromNetQueue(), Network::setToNetQueue(), QTIsaac< ALPHA >::shuffle(), QTIsaac< ALPHA >::srand(), BitUnionData::templatedFunction(), TEST(), test2DVoid(), testIntVoid(), testPrepareInt(), testPrepareVoid(), to_number(), sc_dt::to_string(), sc_dt::scfx_rep::to_string(), sc_dt::vec_from_str(), NetworkInterface::wakeup(), and sc_core::sc_inout< bool >::write().

◆ bas

Bitfield< 12, 5 > ArmISA::bas

◆ bbm

Bitfield<55, 52> ArmISA::bbm

Definition at line 147 of file miscregs_types.hh.

◆ bigend

Bitfield<11, 8> ArmISA::bigend

Definition at line 128 of file miscregs_types.hh.

◆ bigendEL0

Bitfield<19, 16> ArmISA::bigendEL0

Definition at line 126 of file miscregs_types.hh.

◆ bigThumb

Bitfield<35> ArmISA::bigThumb

Definition at line 89 of file types.hh.

◆ bottom2

Bitfield<1, 0> ArmISA::bottom2

Definition at line 65 of file types.hh.

◆ bpaddremask

Bitfield<11,8> ArmISA::bpaddremask

Definition at line 781 of file miscregs_types.hh.

◆ brps

Bitfield<15, 12> ArmISA::brps

Definition at line 80 of file miscregs_types.hh.

◆ bsu

Bitfield<11, 10> ArmISA::bsu

Definition at line 270 of file miscregs_types.hh.

◆ bt

Bitfield<23, 20> ArmISA::bt

Definition at line 698 of file miscregs_types.hh.

◆ c

Bitfield< 29 > ArmISA::c

Definition at line 50 of file miscregs_types.hh.

Referenced by ThermalModel::addCapacitor(), Trace::TarmacParserRecord::advanceTrace(), sc_gem5::Scheduler::asyncRequestUpdate(), sc_core::sc_vector< svp_gicv3_comms::gicv3_comms_target_socket<> >::bind(), sc_core::sc_vector_assembly< T, MT >::bind(), BaseCache::CacheStats::CacheStats(), ArmSemihosting::callWriteC(), sc_gem5::Scheduler::clear(), SrcClockDomain::clockPeriod(), GPUCoalescer::coalescePacket(), Clocked::cyclesToTicks(), Trace::Logger::dump(), BaseRemoteGDB::encodeBinaryData(), AddrRangeMap< AbstractMemory *, 1 >::find(), fp16_muladd(), fp16_process_NaNs3(), fp32_muladd(), fp32_process_NaNs3(), fp64_div(), fp64_muladd(), fp64_process_NaNs3(), fp64_sqrt(), FUPool::FUPool(), BloomFilter::Bulk::hash(), PS2Device::hostRegDataAvailable(), PS2Device::hostWrite(), sc_gem5::Kernel::init(), sc_dt::sc_lv_base::init(), sc_dt::scfx_rep::is_neg(), PS2Keyboard::keyPress(), sc_dt::sc_fxnum::lock_observer(), sc_dt::lshift(), PseudoInst::m5sum(), PowerISA::IntOp::makeCRField(), PowerISA::FloatOp::makeCRField(), sc_dt::neg(), sc_core::sc_vector< svp_gicv3_comms::gicv3_comms_target_socket<> >::operator()(), sc_core::sc_vector_assembly< T, MT >::operator()(), LinearEquation::operator*=(), sc_dt::sc_fxval::operator++(), sc_dt::sc_fxval_fast::operator++(), sc_dt::sc_fxnum::operator++(), sc_dt::sc_fxnum_fast::operator++(), sc_dt::sc_fxval::operator--(), sc_dt::sc_fxval_fast::operator--(), sc_dt::sc_fxnum::operator--(), sc_dt::sc_fxnum_fast::operator--(), sc_core::sc_out< bool >::operator=(), sc_dt::scfx_string::operator[](), MathExpr::parse(), tlm::tlm_endian_context_pool::pop(), Linux::printk(), QTIsaac< ALPHA >::QTIsaac(), QTIsaac< ALPHA >::randinit(), Terminal::read(), Terminal::readData(), BaseRemoteGDB::recv(), ClockDomain::registerWithClockDomain(), sc_gem5::Kernel::regStats(), ExecStage::regStats(), sc_gem5::Scheduler::requestUpdate(), sc_dt::rsh_scfx_rep(), sc_dt::rshift(), sc_dt::sc_abs(), SC_MODULE(), sc_dt::scfx_exp_start(), sc_dt::scfx_is_equal(), sc_dt::scfx_rep::scfx_rep(), BaseRemoteGDB::send(), sc_dt::scfx_rep::set_inf(), IdeDisk::setController(), Message::setMsgCounter(), QTIsaac< ALPHA >::shuffle(), split_first(), split_last(), QTIsaac< ALPHA >::srand(), sc_gem5::Kernel::startup(), sc_gem5::Kernel::stopWork(), GuestABI::Result< Aapcs64, Composite, typename std::enable_if< IsAapcs64Composite< Composite >::value &&!IsAapcs64Hxa< Composite >::value >::type >::store(), TEST(), test2DVoid(), testIntVoid(), testPredicate(), to_lower(), to_number(), sc_dt::to_string(), PortProxy::tryReadString(), PS2Device::unserialize(), DerivedClockDomain::updateClockPeriod(), MultiperspectivePerceptronTAGE::updatePartial(), Stats::validateStatName(), Terminal::write(), and Terminal::writeData().

◆ ccidx

Bitfield<23, 20> ArmISA::ccidx

Definition at line 154 of file miscregs_types.hh.

◆ ccRegName

const char* const ArmISA::ccRegName[NUM_CCREGS]
Initial value:
= {
"nz",
"c",
"v",
"ge",
"fp",
"zero"
}

Definition at line 54 of file ccregs.hh.

Referenced by ArmISA::ArmStaticInst::printCCReg(), and Trace::TarmacTracerRecord::TraceRegEntry::updateCC().

◆ cd

Bitfield<32> ArmISA::cd

◆ cidmask

ArmISA::cidmask

Definition at line 776 of file miscregs_types.hh.

◆ cm

Bitfield<13> ArmISA::cm

◆ cnp

Bitfield<3, 0> ArmISA::cnp

Definition at line 159 of file miscregs_types.hh.

◆ cond

ArmISA::cond

◆ condCode

Bitfield<31, 28> ArmISA::condCode

Definition at line 120 of file types.hh.

Referenced by ArmISA::ArmFault::setSyndrome().

◆ CondCodesMask

const uint32_t ArmISA::CondCodesMask = 0xF00F0000
static

Definition at line 2174 of file miscregs.hh.

◆ cp0

ArmISA::cp0

Definition at line 302 of file miscregs_types.hh.

◆ cp1

Bitfield< 3, 2 > ArmISA::cp1

Definition at line 301 of file miscregs_types.hh.

◆ cp10

Bitfield< 21, 20 > ArmISA::cp10

Definition at line 292 of file miscregs_types.hh.

◆ cp11

Bitfield< 23, 22 > ArmISA::cp11

Definition at line 291 of file miscregs_types.hh.

◆ cp12

Bitfield< 25, 24 > ArmISA::cp12

Definition at line 290 of file miscregs_types.hh.

◆ cp13

Bitfield< 27, 26 > ArmISA::cp13

Definition at line 289 of file miscregs_types.hh.

◆ cp15ben

Bitfield<5> ArmISA::cp15ben

Definition at line 382 of file miscregs_types.hh.

◆ cp2

Bitfield< 5, 4 > ArmISA::cp2

Definition at line 300 of file miscregs_types.hh.

◆ cp3

Bitfield< 7, 6 > ArmISA::cp3

Definition at line 299 of file miscregs_types.hh.

◆ cp4

Bitfield< 9, 8 > ArmISA::cp4

Definition at line 298 of file miscregs_types.hh.

◆ cp5

Bitfield< 11, 10 > ArmISA::cp5

Definition at line 297 of file miscregs_types.hh.

◆ cp6

Bitfield< 13, 12 > ArmISA::cp6

Definition at line 296 of file miscregs_types.hh.

◆ cp7

Bitfield< 15, 14 > ArmISA::cp7

Definition at line 295 of file miscregs_types.hh.

◆ cp8

Bitfield< 17, 16 > ArmISA::cp8

Definition at line 294 of file miscregs_types.hh.

◆ cp9

Bitfield< 19, 18 > ArmISA::cp9

Definition at line 293 of file miscregs_types.hh.

◆ cpNum

Bitfield<11, 8> ArmISA::cpNum

Definition at line 157 of file types.hh.

◆ CpsrMask

const uint32_t ArmISA::CpsrMask = ApsrMask | 0x00F003DF
static

Definition at line 2186 of file miscregs.hh.

◆ CpsrMaskQ

const uint32_t ArmISA::CpsrMaskQ = 0x08000000
static

Definition at line 2175 of file miscregs.hh.

Referenced by ArmISA::ISA::setMiscReg().

◆ crc32

Bitfield<19, 16> ArmISA::crc32

Definition at line 97 of file miscregs_types.hh.

◆ csv2

Bitfield<59, 56> ArmISA::csv2

Definition at line 164 of file miscregs_types.hh.

◆ csv3

ArmISA::csv3

Definition at line 163 of file miscregs_types.hh.

◆ ctx_cmps

Bitfield<31, 28> ArmISA::ctx_cmps

Definition at line 78 of file miscregs_types.hh.

◆ cwg

Bitfield<27,24> ArmISA::cwg

Definition at line 638 of file miscregs_types.hh.

◆ d

Bitfield<9> ArmISA::d

Definition at line 60 of file miscregs_types.hh.

Referenced by Stats::DistBase< Distribution, DistStor >::add(), sc_dt::add_on_help(), ThermalModel::addDomain(), Prefetcher::Tagged::calculatePrefetch(), Prefetcher::IrregularStreamBuffer::calculatePrefetch(), Prefetcher::Stride::calculatePrefetch(), sc_dt::check_for_zero(), DVFSHandler::clkPeriodAtPerfLevel(), sc_dt::compare_unsigned(), Wavefront::computeActualWgSz(), VirtQueue::consumeDescriptor(), sc_dt::convert_signed_2C_to_SM(), sc_dt::convert_signed_SM_to_2C(), sc_dt::convert_signed_SM_to_2C_trimmed(), sc_dt::convert_SM_to_2C(), RefCountingPtr< MinorDynInst >::copy(), sc_dt::sc_unsigned::copy_digits(), sc_dt::sc_signed::copy_digits(), sc_dt::copy_digits_signed(), Trace::Logger::dump(), VirtQueue::dump(), DVFSHandler::DVFSHandler(), iGbReg::TxdOp::eop(), Process::findDriver(), sc_core::sc_time::from_seconds(), sc_core::sc_time::from_string(), iGbReg::TxdOp::getBuf(), iGbReg::TxdOp::getCso(), iGbReg::TxdOp::getCss(), iGbReg::TxdOp::getLen(), iGbReg::TxdOp::getTsoLen(), iGbReg::TxdOp::getType(), LSQ< Impl >::SplitDataRequest::handleLocalAccess(), ComputeUnit::hasDispResources(), iGbReg::TxdOp::hdrlen(), I2CBus::I2CBus(), iGbReg::TxdOp::ic(), iGbReg::TxdOp::ide(), iGbReg::TxdOp::ifcs(), SparcISA::TlbMap::insert(), AddrRangeMap< AbstractMemory *, 1 >::insert(), iGbReg::TxdOp::ip(), iGbReg::TxdOp::ipcse(), iGbReg::TxdOp::ipcso(), iGbReg::TxdOp::ipcss(), iGbReg::TxdOp::isAdvDesc(), iGbReg::TxdOp::isContext(), iGbReg::TxdOp::isData(), iGbReg::TxdOp::isLegacy(), iGbReg::TxdOp::isType(), iGbReg::TxdOp::isTypes(), sc_dt::sc_unsigned::iszero(), iGbReg::TxdOp::ixsm(), PseudoInst::m5sum(), iGbReg::TxdOp::mss(), sc_core::sc_prim_channel::next_trigger(), sc_core::sc_module::next_trigger(), sc_core::next_trigger(), sc_core::sc_event_queue::notify(), sc_gem5::Event::notify(), sc_core::sc_event::notify(), VirtQueue::onNotify(), CopyEngineReg::Reg< uint64_t >::operator()(), iGbReg::Regs::Reg< uint64_t >::operator()(), sc_core::operator*(), sc_core::sc_time::operator*=(), sc_core::operator/(), sc_core::sc_time::operator/=(), operator<<(), CopyEngineReg::Reg< uint64_t >::operator=(), iGbReg::Regs::Reg< uint64_t >::operator=(), CopyEngineReg::Reg< uint64_t >::operator==(), iGbReg::Regs::Reg< uint64_t >::operator==(), DVFSHandler::perfLevel(), QTIsaac< ALPHA >::randinit(), DistIface::RecvScheduler::resumeRecvTicks(), iGbReg::TxdOp::rs(), VoltageDomain::sanitiseVoltages(), SC_MODULE(), sc_core::sc_set_default_time_unit(), sc_core::sc_set_time_resolution(), sc_core::sc_start(), sc_core::sc_time::sc_time(), RefCountingPtr< MinorDynInst >::set(), sc_gem5::TraceFile::set_time_unit(), Trace::InstRecord::setData(), iGbReg::TxdOp::setDd(), OutputDirectory::setDirectory(), Topology::shortest_path_to_node(), QTIsaac< ALPHA >::shuffle(), iGbReg::TxdOp::tcp(), TEST(), test2DVoid(), testIntVoid(), tlm::tlm_from_hostendian_word(), tlm::tlm_to_hostendian_word(), ArmISA::SelfDebug::triggerWatchpointException(), sc_dt::trim(), sc_dt::trim_unsigned(), VirtIOConsole::TermRecvQueue::trySend(), iGbReg::TxdOp::tse(), iGbReg::TxdOp::tucse(), iGbReg::TxdOp::tucso(), iGbReg::TxdOp::tucss(), iGbReg::TxdOp::txsm(), DVFSHandler::UpdateEvent::updatePerfLevel(), iGbReg::TxdOp::utcmd(), iGbReg::TxdOp::vle(), DVFSHandler::voltageAtPerfLevel(), sc_core::sc_prim_channel::wait(), sc_core::sc_module::wait(), sc_core::wait(), I2CBus::write(), and VGic::writeCtrl().

◆ d32dis

Bitfield<30> ArmISA::d32dis

Definition at line 411 of file miscregs_types.hh.

◆ daif

Bitfield<9, 6> ArmISA::daif

◆ dataRAMSetup

Bitfield<5> ArmISA::dataRAMSetup

Definition at line 618 of file miscregs_types.hh.

◆ dataRAMSlice

Bitfield<11,10> ArmISA::dataRAMSlice

Definition at line 621 of file miscregs_types.hh.

◆ dc

Bitfield<12> ArmISA::dc

Definition at line 269 of file miscregs_types.hh.

Referenced by ArmISA::TLB::translateMmuOff().

◆ dCacheLineSize

Bitfield<19,16> ArmISA::dCacheLineSize

Definition at line 636 of file miscregs_types.hh.

◆ debugStep

Bitfield<60> ArmISA::debugStep

Definition at line 72 of file types.hh.

◆ debugver

Bitfield<3, 0> ArmISA::debugver

Definition at line 83 of file miscregs_types.hh.

◆ decoderFault

ArmISA::decoderFault

Definition at line 70 of file types.hh.

◆ defaultNaN

Bitfield<7, 4> ArmISA::defaultNaN

Definition at line 472 of file miscregs_types.hh.

◆ dit

Bitfield<51, 48> ArmISA::dit

Definition at line 165 of file miscregs_types.hh.

Referenced by DVFSHandler::DVFSHandler(), and VoltageDomain::sanitiseVoltages().

◆ divide

Bitfield<19, 16> ArmISA::divide

Definition at line 464 of file miscregs_types.hh.

Referenced by SC_MODULE().

◆ dn

Bitfield<25> ArmISA::dn

Definition at line 444 of file miscregs_types.hh.

◆ domain

Bitfield<7, 4> ArmISA::domain

◆ doublelock

Bitfield< 23, 20 > ArmISA::doublelock

Definition at line 76 of file miscregs_types.hh.

◆ doublePrecision

Bitfield<11, 8> ArmISA::doublePrecision

Definition at line 462 of file miscregs_types.hh.

◆ dp

Bitfield<47, 44> ArmISA::dp

◆ dpb

Bitfield<3, 0> ArmISA::dpb

Definition at line 114 of file miscregs_types.hh.

◆ ds0

Bitfield<16> ArmISA::ds0

Definition at line 577 of file miscregs_types.hh.

◆ ds1

Bitfield<17> ArmISA::ds1

Definition at line 578 of file miscregs_types.hh.

◆ dz

Bitfield<19> ArmISA::dz

Definition at line 353 of file miscregs_types.hh.

◆ dzc

Bitfield<1> ArmISA::dzc

Definition at line 428 of file miscregs_types.hh.

◆ dze

Bitfield< 9 > ArmISA::dze

Definition at line 365 of file miscregs_types.hh.

◆ e

Bitfield< 0 > ArmISA::e

Definition at line 61 of file miscregs_types.hh.

Referenced by sc_gem5::Object::addChildEvent(), Workload::addFuncEventOrPanic(), KernelWorkload::addKernelFuncEventOrPanic(), sc_gem5::DynamicSensitivity::addToEvent(), sc_gem5::StaticSensitivity::addToEvent(), ARMArchTLB::ARMArchTLB(), Iris::BaseCPU::BaseCPU(), sc_gem5::Module::beforeEndOfElaboration(), Stats::Hdf5::beginGroup(), Iris::ThreadContext::breakpointHit(), tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::bw_process::bw_process(), SwitchingFiber::checkExpected(), BaseRemoteGDB::cmd_query_var(), ConfigCache::ConfigCache(), SMMUTranslationProcess::configCacheLookup(), SMMUTranslationProcess::configCacheUpdate(), countBoolVec(), sc_gem5::Object::delChildEvent(), sc_gem5::DynamicSensitivity::delFromEvent(), sc_gem5::StaticSensitivity::delFromEvent(), DmaReadFifo::DmaReadFifo(), ThermalModel::doStep(), RiscvISA::TLB::doTranslate(), PCEventQueue::dump(), dumpDmesgEntry(), LSQUnit< Impl >::dumpInsts(), X86KvmCPU::dumpMSRs(), tlm_utils::time_ordered_list< PAYLOAD >::element::element(), sc_gem5::Module::endOfElaboration(), sc_gem5::Module::endOfSimulation(), RubySystem::enqueueRubyEvent(), ExtensionPool< T >::entry::entry(), ExtensionPool< MultiSocketSimpleSwitchAT::ConnectionInfo >::ExtensionPool(), sc_gem5::Event::getFromScEvent(), SMMUTranslationProcess::ifcTLBLookup(), SMMUTranslationProcess::ifcTLBUpdate(), sc_core::sc_event_and_list::insert(), sc_core::sc_event_or_list::insert(), sc_core::sc_event_and_expr::insert(), sc_core::sc_event_or_expr::insert(), SMMUTLB::invalidateASID(), ARMArchTLB::invalidateASID(), WalkCache::invalidateASID(), IPACache::invalidateIPA(), IPACache::invalidateIPAA(), SMMUTLB::invalidateSID(), ConfigCache::invalidateSID(), SMMUTLB::invalidateSSID(), ConfigCache::invalidateSSID(), SMMUTLB::invalidateVA(), ARMArchTLB::invalidateVA(), WalkCache::invalidateVA(), SMMUTLB::invalidateVAA(), ARMArchTLB::invalidateVAA(), WalkCache::invalidateVAA(), SMMUTLB::invalidateVMID(), ARMArchTLB::invalidateVMID(), IPACache::invalidateVMID(), WalkCache::invalidateVMID(), IPACache::IPACache(), SMMUTLB::lookup(), ARMArchTLB::lookup(), IPACache::lookup(), ConfigCache::lookup(), WalkCache::lookup(), SMMUTLB::lookupAnyVA(), PseudoInst::m5sum(), makeKvmCpuid(), SMMUTranslationProcess::microTLBLookup(), SMMUTranslationProcess::microTLBUpdate(), sc_gem5::newDynamicSensitivityEvent(), sc_gem5::newStaticSensitivityEvent(), sc_core::sc_prim_channel::next_trigger(), sc_core::sc_module::next_trigger(), sc_core::next_trigger(), sc_gem5::Sensitivity::notify(), sc_gem5::DynamicSensitivityEventOrList::notifyWork(), sc_gem5::DynamicSensitivityEventAndList::notifyWork(), Time::operator double(), sc_core::sc_event_and_list::operator&(), sc_core::sc_event::operator&(), sc_core::operator&(), sc_core::sc_event_and_list::operator&=(), operator<<(), sc_core::sc_sensitive::operator<<(), SparcISA::TteTag::operator=(), SparcISA::PageTableEntry::operator=(), sc_core::sc_event_or_list::operator|(), sc_core::sc_event::operator|(), sc_core::operator|(), sc_core::sc_event_or_list::operator|=(), SparcISA::SparcStaticInst::passesFpCondition(), SparcISA::PageTableEntry::populate(), power(), QoS::MemSinkCtrl::processNextReqEvent(), VirtQueue::produceDescriptor(), pybind_init_event(), QTIsaac< ALPHA >::randinit(), tlm_utils::simple_target_socket_b< SimpleLTTarget_ext, BUSWIDTH, my_extended_payload_types >::register_transport_dbg(), System::registerThreadContext(), O3ThreadContext< Impl >::remove(), CheckerThreadContext< TC >::remove(), Iris::ThreadContext::remove(), SimpleThread::remove(), System::replaceThreadContext(), sc_gem5::reportifyException(), DmaReadFifo::resumeFillTiming(), ArmSemihosting::retError(), sc_core::sc_event_and_expr::sc_event_and_expr(), sc_core::sc_event_and_list::sc_event_and_list(), sc_core::sc_event_or_expr::sc_event_or_expr(), sc_core::sc_event_or_list::sc_event_or_list(), O3ThreadContext< Impl >::schedule(), CheckerThreadContext< TC >::schedule(), Iris::ThreadContext::schedule(), SimpleThread::schedule(), sc_core::sc_spawn_options::set_sensitivity(), FullO3CPU< O3CPUImpl >::setVectorsAsReady(), QTIsaac< ALPHA >::shuffle(), SMMUTLB::SMMUTLB(), SMMUTranslationProcess::smmuTLBLookup(), SMMUTranslationProcess::smmuTLBUpdate(), sc_gem5::spawnWork(), tlm_utils::simple_target_socket_tagged_b< SimpleBusLT, 32, tlm::tlm_base_protocol_types >::start_of_simulation(), sc_gem5::Module::startOfSimulation(), SparcISA::TLB::translateData(), ArmISA::TLB::translateFunctional(), SparcISA::TLB::translateInst(), SMMUTranslationProcess::translateStage2(), RiscvISA::TLB::translateWithTLB(), BaseRemoteGDB::trap(), Prefetcher::STeMS::ActiveGenerationTableEntry::update(), X86KvmCPU::updateKvmStateMSRs(), sc_core::sc_prim_channel::wait(), sc_core::sc_module::wait(), sc_core::wait(), WalkCache::WalkCache(), SMMUTranslationProcess::walkCacheUpdate(), and DmaReadFifo::~DmaReadFifo().

◆ e0e

Bitfield<24> ArmISA::e0e

Definition at line 343 of file miscregs_types.hh.

◆ e0pd

ArmISA::e0pd

Definition at line 145 of file miscregs_types.hh.

◆ e2h

Bitfield<34> ArmISA::e2h

Definition at line 246 of file miscregs_types.hh.

◆ ea

Bitfield<3> ArmISA::ea

◆ eae

Bitfield<31> ArmISA::eae

Definition at line 506 of file miscregs_types.hh.

◆ ease

Bitfield<19> ArmISA::ease

Definition at line 308 of file miscregs_types.hh.

◆ ec

ArmISA::ec

◆ eccandParityEnable

Bitfield<21> ArmISA::eccandParityEnable

Definition at line 624 of file miscregs_types.hh.

◆ ecv

Bitfield< 12 > ArmISA::ecv

Definition at line 118 of file miscregs_types.hh.

◆ ee

Bitfield<25> ArmISA::ee

Definition at line 342 of file miscregs_types.hh.

◆ eel2

Bitfield<18> ArmISA::eel2

Definition at line 309 of file miscregs_types.hh.

◆ el

Bitfield< 3, 2 > ArmISA::el

Definition at line 69 of file miscregs_types.hh.

Referenced by addPAC(), addPACDA(), addPACDB(), addPACGA(), addPACIA(), addPACIB(), ArmISA::VectorCatch::addressMatching(), ArmISA::ArmStaticInst::advSIMDFPAccessTrap64(), auth(), authDA(), authDB(), authIA(), authIB(), calculateBottomPACBit(), calculateTBI(), canWriteAArch64SysReg(), MiscRegOp64::checkEL1Trap(), MiscRegOp64::checkEL2Trap(), MiscRegOp64::checkEL3Trap(), ArmISA::ArmStaticInst::checkFPAdvSIMDEnabled64(), ArmISA::ArmStaticInst::checkSveEnabled(), computeAddrTop(), ELIs32(), ELIs64(), ELIsInHost(), ELStateUsingAArch32(), ELStateUsingAArch32K(), ELUsingAArch32K(), ArmISA::VectorCatch::exceptionTrapping(), MiscRegImplDefined64::execute(), ArmISA::ISA::flattenIntIndex(), ArmISA::ISA::getCurSveVecLenInBits(), getRestoredITBits(), haveAArch32EL(), ArmSystem::haveEL(), Gicv3CPUInterface::haveEL(), ArmISA::TLB::insert(), ArmISA::SelfDebug::isDebugEnabled(), ArmISA::SelfDebug::isDebugEnabledForEL32(), ArmISA::SelfDebug::isDebugEnabledForEL64(), ArmISA::BrkPoint::isEnabled(), ArmISA::WatchPoint::isEnabled(), ArmISA::PMU::CounterState::isFiltered(), purifyTaggedAddr(), s1TranslationRegime(), ArmISA::ISA::setMiscReg(), stripPAC(), ArmISA::ArmStaticInst::sveAccessTrap(), ArmISA::Interrupts::takeInt(), ArmISA::BrkPoint::test(), ArmISA::WatchPoint::test(), ArmISA::SelfDebug::testBreakPoints(), ArmISA::BrkPoint::testContextMatch(), ArmISA::BrkPoint::testLinkedBk(), ArmISA::SelfDebug::testVectorCatch(), ArmISA::BrkPoint::testVMIDMatch(), ArmISA::SelfDebug::testWatchPoints(), MiscRegOp64::trap(), and upperAndLowerRange().

◆ el0

Bitfield<3, 0> ArmISA::el0

Definition at line 177 of file miscregs_types.hh.

◆ el0pcten

Bitfield< 0 > ArmISA::el0pcten

Definition at line 55 of file generic_timer_miscregs_types.hh.

◆ el0pten

Bitfield< 9 > ArmISA::el0pten

Definition at line 49 of file generic_timer_miscregs_types.hh.

◆ el0vcten

Bitfield< 1 > ArmISA::el0vcten

Definition at line 54 of file generic_timer_miscregs_types.hh.

◆ el0vten

Bitfield< 8 > ArmISA::el0vten

Definition at line 50 of file generic_timer_miscregs_types.hh.

◆ el1

Bitfield<7, 4> ArmISA::el1

Definition at line 176 of file miscregs_types.hh.

◆ el1nvpct

Bitfield< 15 > ArmISA::el1nvpct

Definition at line 62 of file generic_timer_miscregs_types.hh.

◆ el1nvvct

Bitfield< 16 > ArmISA::el1nvvct

Definition at line 61 of file generic_timer_miscregs_types.hh.

◆ el1pcen

Bitfield<1> ArmISA::el1pcen

Definition at line 70 of file generic_timer_miscregs_types.hh.

◆ el1pcten

Bitfield< 10 > ArmISA::el1pcten

Definition at line 71 of file generic_timer_miscregs_types.hh.

◆ el1pten

Bitfield<11> ArmISA::el1pten

Definition at line 83 of file generic_timer_miscregs_types.hh.

◆ el1tvct

Bitfield< 14 > ArmISA::el1tvct

Definition at line 63 of file generic_timer_miscregs_types.hh.

◆ el1tvt

Bitfield< 13 > ArmISA::el1tvt

Definition at line 64 of file generic_timer_miscregs_types.hh.

◆ el2

Bitfield<11, 8> ArmISA::el2

Definition at line 175 of file miscregs_types.hh.

◆ el3

Bitfield<15, 12> ArmISA::el3

Definition at line 174 of file miscregs_types.hh.

◆ en

Bitfield<30> ArmISA::en

◆ encoding

Bitfield<27, 25> ArmISA::encoding

◆ enda

Bitfield<27> ArmISA::enda

Definition at line 338 of file miscregs_types.hh.

◆ endb

Bitfield<13> ArmISA::endb

Definition at line 368 of file miscregs_types.hh.

◆ enib

Bitfield<30> ArmISA::enib

Definition at line 333 of file miscregs_types.hh.

◆ epd0

Bitfield< 7 > ArmISA::epd0

Definition at line 489 of file miscregs_types.hh.

◆ epd1

Bitfield< 23 > ArmISA::epd1

Definition at line 496 of file miscregs_types.hh.

◆ erg

Bitfield<23,20> ArmISA::erg

Definition at line 637 of file miscregs_types.hh.

◆ err

Bitfield<6> ArmISA::err

◆ evntdir

Bitfield< 3 > ArmISA::evntdir

Definition at line 52 of file generic_timer_miscregs_types.hh.

◆ evnten

Bitfield< 2 > ArmISA::evnten

Definition at line 53 of file generic_timer_miscregs_types.hh.

Referenced by GenericTimer::handleStream().

◆ evnti

Bitfield< 7, 4 > ArmISA::evnti

Definition at line 51 of file generic_timer_miscregs_types.hh.

◆ evt

Bitfield<59, 56> ArmISA::evt

Definition at line 146 of file miscregs_types.hh.

Referenced by Consumer::scheduleEventAbsolute().

◆ exs

Bitfield<47, 44> ArmISA::exs

Definition at line 119 of file miscregs_types.hh.

◆ ext

Bitfield<12> ArmISA::ext

◆ ez

Bitfield<8> ArmISA::ez

Definition at line 679 of file miscregs_types.hh.

◆ f

Bitfield< 0 > ArmISA::f

Definition at line 64 of file miscregs_types.hh.

Referenced by __nan(), BaseRemoteGDB::attach(), BaseGlobalEventTemplate< GlobalSyncEvent >::BaseGlobalEventTemplate(), bitsToFloat32(), bitsToFloat64(), Debug::changeFlag(), dumpDebugFlags(), Event::Event(), MemBackdoor::flags(), floatToBits32(), floatToBits64(), PowerModel::getDynamicPower(), PowerModel::getStaticPower(), ArmSemihosting::getSTDIO(), flitBuffer::getTopFlit(), BaseDynInst< Impl >::hitExternalSnoop(), MultiperspectivePerceptron::lookup(), PseudoInst::m5sum(), BaseDynInst< Impl >::memOpDone(), sc_gem5::newStaticSensitivityFinder(), Linux::openSpecialFile(), sc_core::sc_sensitive::operator()(), sc_core::sc_sensitive::operator<<(), sc_core::operator<<(), BaseDynInst< Impl >::possibleLoadViolation(), CallbackQueue::process(), ArmISA::TableWalker::processWalk(), ArmISA::TableWalker::processWalkLPAE(), ArmISA::TableWalker::processWalkWrapper(), QTIsaac< ALPHA >::randinit(), BaseDynInst< Impl >::recordResult(), PybindSimObjectResolver::resolveSimObject(), sc_core::sc_bind(), Flags< FlagsType >< FlagsType >::set(), sc_core::sc_spawn_options::set_sensitivity(), StaticInst::setFlag(), Trace::InstRecord::setMem(), QTIsaac< ALPHA >::shuffle(), LinearSystem::solve(), sc_gem5::spawnWork(), GuestABI::Result< Aapcs32, Float, typename std::enable_if< std::is_floating_point< Float >::value >::type >::store(), GuestABI::Result< Aapcs32Vfp, Float, typename std::enable_if< std::is_floating_point< Float >::value >::type >::store(), TEST(), Trace::InstPBTrace::traceMem(), ArmISA::TLB::translateMmuOff(), BaseDynInst< Impl >::translationCompleted(), BaseDynInst< Impl >::translationStarted(), MultiperspectivePerceptron::update(), and OutputDirectory::~OutputDirectory().

◆ fb

Bitfield<9> ArmISA::fb

Definition at line 271 of file miscregs_types.hh.

Referenced by FrameBuffer::copyIn(), FrameBuffer::copyOut(), and createImgWriter().

◆ fcma

Bitfield<19, 16> ArmISA::fcma

Definition at line 110 of file miscregs_types.hh.

◆ fd

Bitfield<14, 12> ArmISA::fd

◆ fhm

Bitfield<51, 48> ArmISA::fhm

Definition at line 90 of file miscregs_types.hh.

◆ fi

Bitfield<21> ArmISA::fi

Definition at line 349 of file miscregs_types.hh.

Referenced by MathExprPowerModel::getStatValue().

◆ fiq

Bitfield<2> ArmISA::fiq

Definition at line 326 of file miscregs_types.hh.

◆ flushToZero

ArmISA::flushToZero

◆ fm

Bitfield<3, 0> ArmISA::fm

Definition at line 161 of file types.hh.

◆ fmo

Bitfield<3> ArmISA::fmo

◆ fn

Bitfield<18, 16> ArmISA::fn

Definition at line 158 of file types.hh.

Referenced by MathExpr::eval().

◆ format

Bitfield<31,29> ArmISA::format

◆ fp

Bitfield<19, 16> ArmISA::fp

◆ FpCondCodesMask

const uint32_t ArmISA::FpCondCodesMask = 0xF0000000
static

Definition at line 2190 of file miscregs.hh.

◆ fpen

Bitfield< 21, 20 > ArmISA::fpen

Definition at line 405 of file miscregs_types.hh.

◆ fpImm

Bitfield<2, 0> ArmISA::fpImm

Definition at line 162 of file types.hh.

◆ fpRegImm

Bitfield<3> ArmISA::fpRegImm

Definition at line 160 of file types.hh.

◆ FpscrAhpMask

const uint32_t ArmISA::FpscrAhpMask = 0x04000000
static

Definition at line 2194 of file miscregs.hh.

◆ FpscrExcMask

const uint32_t ArmISA::FpscrExcMask = 0x0000009F
static

Definition at line 2196 of file miscregs.hh.

Referenced by ArmISA::ISA::readMiscReg(), and ArmISA::ISA::setMiscReg().

◆ fpscrLen

Bitfield<39, 37> ArmISA::fpscrLen

Definition at line 85 of file types.hh.

◆ FpscrQcMask

const uint32_t ArmISA::FpscrQcMask = 0x08000000
static

Definition at line 2192 of file miscregs.hh.

Referenced by ArmISA::ISA::readMiscReg(), and ArmISA::ISA::setMiscReg().

◆ fpscrStride

Bitfield<41, 40> ArmISA::fpscrStride

Definition at line 84 of file types.hh.

◆ FramePointerReg

const int ArmISA::FramePointerReg = 11

◆ frintts

Bitfield<35, 32> ArmISA::frintts

Definition at line 106 of file miscregs_types.hh.

◆ fs4_0

Bitfield<5, 1> ArmISA::fs4_0

Definition at line 658 of file miscregs_types.hh.

◆ fs5

Bitfield<6> ArmISA::fs5

Definition at line 657 of file miscregs_types.hh.

◆ fsHigh

Bitfield<10> ArmISA::fsHigh

Definition at line 420 of file miscregs_types.hh.

◆ fsLow

ArmISA::fsLow

Definition at line 416 of file miscregs_types.hh.

◆ fst

Bitfield<6, 1> ArmISA::fst

Definition at line 656 of file miscregs_types.hh.

◆ fw

Bitfield<4> ArmISA::fw

Definition at line 324 of file miscregs_types.hh.

◆ fwb

Bitfield< 46 > ArmISA::fwb

Definition at line 149 of file miscregs_types.hh.

◆ fz

Bitfield<24> ArmISA::fz

Definition at line 443 of file miscregs_types.hh.

◆ fz16

Bitfield<19> ArmISA::fz16

Definition at line 440 of file miscregs_types.hh.

◆ ge

Bitfield<19, 16> ArmISA::ge

Definition at line 58 of file miscregs_types.hh.

◆ gic

Bitfield<27, 24> ArmISA::gic

Definition at line 171 of file miscregs_types.hh.

Referenced by ArmSystem::setGIC().

◆ gpa

Bitfield<27, 24> ArmISA::gpa

Definition at line 108 of file miscregs_types.hh.

◆ gpi

Bitfield<31, 28> ArmISA::gpi

Definition at line 107 of file miscregs_types.hh.

◆ GuestByteOrder

const ByteOrder ArmISA::GuestByteOrder = ByteOrder::little

◆ ha

Bitfield< 21 > ArmISA::ha

◆ hafdbs

Bitfield<3, 0> ArmISA::hafdbs

Definition at line 141 of file miscregs_types.hh.

◆ hcd

Bitfield<29> ArmISA::hcd

Definition at line 251 of file miscregs_types.hh.

◆ hce

Bitfield<8> ArmISA::hce

Definition at line 319 of file miscregs_types.hh.

◆ hd

Bitfield< 22 > ArmISA::hd

Definition at line 539 of file miscregs_types.hh.

◆ hde

Bitfield<14> ArmISA::hde

Definition at line 739 of file miscregs_types.hh.

◆ HighVecs

const uint32_t ArmISA::HighVecs = 0xFFFF0000

Definition at line 60 of file faults.cc.

Referenced by ArmISA::ArmFault::getVector().

◆ hmc

Bitfield< 13 > ArmISA::hmc

◆ hpd

Bitfield< 24 > ArmISA::hpd

Definition at line 528 of file miscregs_types.hh.

◆ hpd0

Bitfield< 41 > ArmISA::hpd0

Definition at line 510 of file miscregs_types.hh.

◆ hpd1

Bitfield< 42 > ArmISA::hpd1

Definition at line 511 of file miscregs_types.hh.

◆ hpds

Bitfield<15, 12> ArmISA::hpds

Definition at line 138 of file miscregs_types.hh.

◆ hpme

Bitfield<7> ArmISA::hpme

Definition at line 185 of file miscregs_types.hh.

◆ hpmn

Bitfield<4, 0> ArmISA::hpmn

Definition at line 188 of file miscregs_types.hh.

◆ htopcode10_9

Bitfield<26, 25> ArmISA::htopcode10_9

Definition at line 185 of file types.hh.

◆ htopcode12_11

Bitfield<28, 27> ArmISA::htopcode12_11

Definition at line 184 of file types.hh.

◆ htopcode4

Bitfield<20> ArmISA::htopcode4

Definition at line 199 of file types.hh.

◆ htopcode5_4

Bitfield<21, 20> ArmISA::htopcode5_4

Definition at line 198 of file types.hh.

◆ htopcode6

Bitfield<22> ArmISA::htopcode6

Definition at line 196 of file types.hh.

◆ htopcode6_5

Bitfield<22, 21> ArmISA::htopcode6_5

Definition at line 197 of file types.hh.

◆ htopcode7

Bitfield<23> ArmISA::htopcode7

Definition at line 194 of file types.hh.

◆ htopcode7_5

Bitfield<23, 21> ArmISA::htopcode7_5

Definition at line 195 of file types.hh.

◆ htopcode8

Bitfield<24> ArmISA::htopcode8

Definition at line 190 of file types.hh.

◆ htopcode8_5

Bitfield<24, 21> ArmISA::htopcode8_5

Definition at line 193 of file types.hh.

◆ htopcode8_6

Bitfield<24, 22> ArmISA::htopcode8_6

Definition at line 192 of file types.hh.

◆ htopcode8_7

Bitfield<24, 23> ArmISA::htopcode8_7

Definition at line 191 of file types.hh.

◆ htopcode9

Bitfield<25> ArmISA::htopcode9

Definition at line 186 of file types.hh.

◆ htopcode9_4

Bitfield<25, 20> ArmISA::htopcode9_4

Definition at line 189 of file types.hh.

◆ htopcode9_5

Bitfield<25, 21> ArmISA::htopcode9_5

Definition at line 188 of file types.hh.

◆ htopcode9_8

Bitfield<25, 24> ArmISA::htopcode9_8

Definition at line 187 of file types.hh.

◆ htrn

Bitfield<19, 16> ArmISA::htrn

Definition at line 201 of file types.hh.

◆ hts

Bitfield<20> ArmISA::hts

Definition at line 202 of file types.hh.

◆ i

Bitfield< 12 > ArmISA::i

Definition at line 63 of file miscregs_types.hh.

Referenced by sc_core::sc_port_b< tlm_nonblocking_put_if< T > >::_gem5AddInterface(), System::_getRequestorId(), ArmISA::Crypto::_sha1Op(), MemChecker::abortWrite(), ListenSocket::accept(), Terminal::accept(), TCPIface::accept(), RubyPrefetcher::accessNonunitFilter(), RubyPrefetcher::accessUnitFilter(), DRAMInterface::activateBank(), Histogram::add(), Stats::HistStor::add(), CheckTable::addCheck(), PerfectSwitch::addInPort(), sc_gem5::Port::addInterfaces(), AddrRange::addIntlvBits(), Stats::Hdf5::addMetaData(), NetDest::addNetDest(), NetworkInterface::addOutPort(), Switch::addOutPort(), DRAMInterface::addRankToRankDelay(), NVMInterface::addRankToRankDelay(), AddrRange::AddrRange(), IniFile::addSection(), Queue< WriteQueueEntry >::addToReadyList(), Trace::TarmacParserRecord::advanceTrace(), ArmISA::Crypto::aesAddRoundKey(), ArmISA::Crypto::aesInvMixColumns(), ArmISA::Crypto::aesInvShiftRows(), ArmISA::Crypto::aesInvSubBytes(), ArmISA::Crypto::aesShiftRows(), ArmISA::Crypto::aesSubBytes(), CacheRecorder::aggregateRecords(), sc_dt::scfx_mant::alloc(), CacheMemory::allocate(), Aapcs32Vfp::State::allocate(), FetchUnit::FetchBufDesc::allocateBuf(), FDArray::allocFD(), NetDest::AND(), sc_dt::sc_unsigned_subref_r::and_reduce(), sc_dt::sc_signed_subref_r::and_reduce(), sc_dt::sc_unsigned::and_reduce(), sc_dt::sc_signed::and_reduce(), FALRU::anyBlk(), ScheduleStage::arbitrateVrfToLdsBus(), MipsProcess::argsInit(), PowerProcess::argsInit(), SparcProcess::argsInit(), ArmProcess::argsInit(), X86ISA::X86Process::argsInit(), arrayParamIn(), arrayParamOut(), sc_dt::sc_proxy< sc_bv_base >::assign_(), sc_dt::assign_v_(), sc_core::sc_vector_assembly< T, MT >::at(), DataBlock::atomicPartial(), sc_dt::b_and_assign_(), sc_dt::b_xor_assign_(), BaseGlobalEventTemplate< GlobalSyncEvent >::BaseGlobalEventTemplate(), BaseIndexingPolicy::BaseIndexingPolicy(), BaseSimpleCPU::BaseSimpleCPU(), FastModel::ScxEvsCortexA76< Types >::before_end_of_elaboration(), sc_core::sc_export< tlm::tlm_fifo_get_if< RSP > >::bind(), sc_core::sc_in< sc_dt::sc_lv< W > >::bind(), sc_core::sc_port_base::bind(), sc_core::sc_port_b< tlm_nonblocking_put_if< T > >::bind(), sc_core::sc_in< bool >::bind(), sc_core::sc_in< sc_dt::sc_logic >::bind(), CxxConfigManager::bindAllPorts(), CxxConfigManager::bindObjectPorts(), sc_dt::sc_fxnum::bit(), sc_dt::sc_uint_base::bit(), sc_dt::sc_int_base::bit(), sc_core::sc_in< sc_dt::sc_int< W > >::bit(), sc_core::sc_in< sc_dt::sc_uint< W > >::bit(), sc_dt::sc_unsigned::bit(), sc_core::sc_in< sc_dt::sc_biguint< W > >::bit(), sc_core::sc_in< sc_dt::sc_bigint< W > >::bit(), sc_dt::sc_fxnum_fast::bit(), sc_core::sc_inout< sc_dt::sc_int< W > >::bit(), sc_dt::sc_signed::bit(), sc_core::sc_inout< sc_dt::sc_uint< W > >::bit(), sc_core::sc_inout< sc_dt::sc_biguint< W > >::bit(), sc_core::sc_inout< sc_dt::sc_bigint< W > >::bit(), bitsToFloat32(), bitsToFloat64(), BloomFilter::Block::Block(), broadcast(), NetDest::broadcast(), Net::EthAddr::broadcast(), TAGEBase::btbUpdate(), Minor::ForwardInstData::bubbleFill(), LSQ< Impl >::SplitDataRequest::buildPackets(), TAGE_SC_L_TAGE::buildTageTables(), TAGEBase::buildTageTables(), CacheMemory::cacheAvail(), CacheMemory::cacheProbe(), TAGE_SC_L_TAGE::calculateIndicesAndTags(), TAGEBase::calculateIndicesAndTags(), MPP_TAGE::calculateParameters(), TAGE_SC_L_TAGE::calculateParameters(), TAGEBase::calculateParameters(), Prefetcher::IndirectMemory::calculatePrefetch(), NetworkInterface::calculateVC(), Minor::LSQ::StoreBuffer::canForwardDataToLoad(), Trace::SparcNativeTrace::check(), Trace::ArmNativeTrace::check(), PacketFifo::check(), SwitchAllocator::check_for_wakeup(), sc_dt::sc_uint_base::check_index(), sc_dt::sc_int_base::check_index(), sc_dt::sc_unsigned::check_index(), sc_dt::sc_signed::check_index(), AbstractMemory::checkLockedAddrList(), CheckTable::CheckTable(), MemCtrl::chooseNext(), DRAMInterface::chooseNextFRFCFS(), NVMInterface::chooseNextFRFCFS(), NVMInterface::chooseRead(), X86ISA::GpuTLB::cleanup(), Histogram::clear(), NetDest::clear(), tlm::circular_buffer< RSP >::clear(), StoreSet::clear(), PacketFifo::clear(), sc_dt::scfx_rep::clear(), SwitchAllocator::clear_request_vector(), SparcISA::Interrupts::clearAll(), MaltaCChip::clearIntr(), CacheMemory::clearLockedAll(), SparcISA::TLB::clearUsedBits(), OutputDirectory::close(), WriteMask::cmpMask(), CoherentXBar::CoherentXBar(), SimpleNetwork::collateStats(), Profiler::collateStats(), GarnetNetwork::collateStats(), Router::collateStats(), DefaultCommit< Impl >::commitHead(), ThreadContext::compare(), ArmISA::WatchPoint::compareAddress(), GPUCoalescer::completeIssue(), MemChecker::completeRead(), MemChecker::completeWrite(), Compressor::Multi::compress(), Compressor::DictionaryCompressor< uint64_t >::compressValue(), MultiperspectivePerceptron::computeBits(), MultiperspectivePerceptron::computeOutput(), QARMA::computePAC(), MultiperspectivePerceptronTAGE::computePartialSum(), BaseTags::computeStats(), sc_dt::concat(), FunctionProfile::consume(), AddrRange::contains(), X86ISA::convX87TagsToXTags(), X86ISA::convX87XTagsToTags(), PollQueue::copy(), sc_dt::copy_digits_signed(), SparcISA::copyMiscRegs(), X86ISA::copyMiscRegs(), PacketFifo::copyout(), DataBlock::copyPartial(), PowerISA::copyRegs(), X86ISA::copyRegs(), copyRegs(), SparcISA::copyRegs(), Checker< O3CPUImpl >::copyResult(), copyStringArray(), FastModel::CortexA76Cluster::CortexA76Cluster(), NetDest::count(), LdsState::countBankConflicts(), GenericTimerMem::counterCtrlRead(), GenericTimerMem::counterCtrlWrite(), PacketFifo::countPacketsAfter(), PacketFifo::countPacketsBefore(), PersistentTable::countReadStarvingForAddress(), PersistentTable::countStarvingForAddress(), crc32(), Topology::createLinks(), GenericTimer::createTimers(), ArmISA::ArmStaticInst::cSwap(), DMASequencer::dataCallback(), FetchUnit::FetchBufDesc::decodeSplitInst(), Compressor::DictionaryCompressor< uint64_t >::decompress(), Compressor::DictionaryCompressor< T >::RepeatedValuePattern< RepT >::decompress(), DefaultBTB::DefaultBTB(), DefaultFetch< Impl >::DefaultFetch(), CxxConfigManager::deleteObjects(), SparcISA::TLB::demapPage(), BaseGlobalEvent::deschedule(), SkewedAssociative::deskew(), StaticInst::destRegIdx(), BaseDynInst< Impl >::destRegIdx(), Linux::devRandom(), ExecStage::dispStatusToStr(), ComputeUnit::dispWorkgroup(), Stats::DistPrint::DistPrint(), DRAMInterface::doBurstAccess(), NVMInterface::doBurstAccess(), Stats::VectorBase< Vector, StatStor >::doInit(), Stats::VectorDistBase< VectorAverageDeviation, AvgSampleStor >::doInit(), ObjectMatch::domatch(), PCEventQueue::doService(), ThermalModel::doStep(), Histogram::doubleBinSize(), FullO3CPU< O3CPUImpl >::drain(), ArmISA::TableWalker::drain(), DefaultFetch< Impl >::drainResume(), FullO3CPU< O3CPUImpl >::drainResume(), MemDepUnit< MemDepPred, Impl >::drainSanityCheck(), LSQUnit< Impl >::drainSanityCheck(), DefaultFetch< Impl >::drainSanityCheck(), DRAMInterface::DRAMInterface(), BaseStackTrace::dump(), Trace::Logger::dump(), ArmV8KvmCPU::dump(), ActivityRecorder::dump(), Trie< Key, Value >::Node::dump(), DependencyGraph< DynInstPtr >::dump(), PCEventQueue::dump(), RegisterFile::dump(), FUPool::dump(), BPredUnit::dump(), IniFile::dump(), sc_dt::scfx_rep::dump(), SparcISA::TLB::dumpAll(), dumpDebugFlags(), ExecStage::dumpDispList(), dumpFpuCommon(), dumpKvm(), InstructionQueue< Impl >::dumpLists(), dumpMainQueue(), X86KvmCPU::dumpMSRs(), BaseDynInst< Impl >::eaSrcsReady(), Loader::ElfObject::ElfObject(), DependencyGraph< DynInstPtr >::empty(), Minor::MinorBuffer< Minor::ForwardInstData >::empty(), sc_core::sc_in< sc_dt::sc_int< W > >::end_of_elaboration(), sc_core::sc_in< sc_dt::sc_uint< W > >::end_of_elaboration(), sc_core::sc_in< sc_dt::sc_biguint< W > >::end_of_elaboration(), sc_core::sc_in< sc_dt::sc_bigint< W > >::end_of_elaboration(), sc_core::sc_inout< sc_dt::sc_int< W > >::end_of_elaboration(), sc_core::sc_inout< sc_dt::sc_uint< W > >::end_of_elaboration(), sc_core::sc_inout< sc_dt::sc_biguint< W > >::end_of_elaboration(), sc_core::sc_inout< sc_dt::sc_bigint< W > >::end_of_elaboration(), SimpleLTInitiator2_dmi::end_of_simulation(), SimpleLTInitiator1_dmi::end_of_simulation(), SimpleLTInitiator_ext::end_of_simulation(), Net::EthAddr::EthAddr(), EtherSwitch::EtherSwitch(), Minor::Decode::evaluate(), Minor::Fetch2::evaluate(), Minor::Execute::evaluate(), eventqDump(), X86ISA::TLB::evictLRU(), Wavefront::exec(), Shader::execScheduledAdds(), Minor::Execute::Execute(), Gcn3ISA::Inst_SOPP__S_ENDPGM::execute(), Gcn3ISA::Inst_VOP3__V_PERM_B32::execute(), execveFunc(), X86ISA::GpuTLB::exitCallback(), exitImpl(), Topology::extend_shortest_path(), sc_dt::extend_sign_w_(), FaultModel::fault_prob(), FaultModel::fault_vector(), FaultModel::FaultModel(), WriteMask::fillMask(), sc_gem5::Port::finalizeFinder(), sc_gem5::Port::finalizePort(), SparcISA::TlbMap::find(), Loader::SymbolTable::find(), sc_gem5::StaticSensitivityFinder::find(), OutputDirectory::find(), AddrRangeMap< AbstractMemory *, 1 >::find(), SimObject::find(), MultiperspectivePerceptron::findBest(), Debug::findFlag(), VGic::findHighestPendingLR(), VGic::findLRForVIRQ(), Loader::SymbolTable::findNearest(), CxxConfigManager::findObject(), CxxConfigManager::findObjectParams(), BaseXBar::findPort(), IniFile::findSection(), PersistentTable::findSmallest(), Minor::FUPipeline::findTiming(), CxxConfigManager::findTraversalOrder(), LSQ< Impl >::SplitDataRequest::finish(), VecPredRegT< VecElem, NumElems, Packed, Const >::firstActive(), Gcn3ISA::firstOppositeSignBit(), AtagCore::flags(), NetworkBridge::flitisizeAndSend(), NetworkInterface::flitisizeMessage(), floatToBits32(), floatToBits64(), X86ISA::TLB::flushAll(), FetchUnit::FetchBufDesc::flushBuf(), X86ISA::TLB::flushNonGlobal(), BaseCPU::flushTLBs(), FALRU::forEachBlk(), CxxConfigManager::forEachObject(), formatParamList(), Gicv2m::frameFromAddr(), Wavefront::freeRegisterFile(), StaticRegisterManagerPolicy::freeRegisters(), Compressor::Base::fromChunks(), Compressor::DictionaryCompressor< uint64_t >::fromDictionaryEntry(), MessageBuffer::functionalAccess(), SimpleNetwork::functionalRead(), Switch::functionalRead(), SimpleNetwork::functionalWrite(), flitBuffer::functionalWrite(), Switch::functionalWrite(), GarnetNetwork::functionalWrite(), Router::functionalWrite(), RubyRequest::functionalWrite(), FuncUnit::FuncUnit(), Minor::FUPipeline::FUPipeline(), FUPool::FUPool(), GarnetNetwork::GarnetNetwork(), MrsOp::generateDisassembly(), ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), GarnetSyntheticTraffic::generatePkt(), Gicv3CPUInterface::generateSGI(), X86ISA::genX87Tags(), GuestABI::Argument< Aapcs64, HA, typename std::enable_if< IsAapcs64Hxa< HA >::value >::type >::get(), GuestABI::Argument< Aapcs32, Composite, typename std::enable_if< IsAapcs32Composite< Composite >::value >::type >::get(), GuestABI::Argument< Aapcs64, Composite, typename std::enable_if< IsAapcs64Composite< Composite >::value &&!IsAapcs64Hxa< Composite >::value >::type >::get(), GuestABI::Argument< Aapcs32Vfp, HA, typename std::enable_if< IsAapcs32HomogeneousAggregate< HA >::value >::type >::get(), tlm_utils::multi_passthrough_target_socket< MultiSocketSimpleSwitchAT >::get_base_export(), sc_dt::scfx_rep::get_bit(), sc_dt::sc_fxval::get_bit(), sc_dt::sc_subref_r< X >::get_bit(), sc_dt::sc_fxnum::get_bit(), VecPredRegContainer< TheISA::VecPredRegSizeBits, TheISA::VecPredRegHasPackedRepr >::get_bits(), sc_dt::sc_subref_r< X >::get_cword(), sc_dt::scfx_rep::get_slice(), sc_dt::sc_fxnum::get_slice(), NetworkInterface::get_vnet(), sc_dt::sc_lv_base::get_word(), sc_dt::sc_subref_r< X >::get_word(), Gicv2m::getAddrRanges(), RubyPort::PioResponsePort::getAddrRanges(), NetDest::getAllDest(), PciDevice::getBAR(), CheckTable::getCheck(), BloomFilter::MultiBitSel::getCount(), PowerModel::getDynamicPower(), TAGEBase::getGHR(), MultiperspectivePerceptron::ACYCLIC::getHash(), MultiperspectivePerceptron::MODHIST::getHash(), MultiperspectivePerceptron::RECENCY::getHash(), MultiperspectivePerceptron::PATH::getHash(), MultiperspectivePerceptron::MODPATH::getHash(), MultiperspectivePerceptron::GHISTPATH::getHash(), MultiperspectivePerceptron::GHISTMODPATH::getHash(), MultiperspectivePerceptron::BLURRYPATH::getHash(), MultiperspectivePerceptron::SGHISTPATH::getHash(), Gicv3CPUInterface::getHPPVILR(), sc_gem5::Port::getInterface(), LoopPredictor::getLoop(), RubyPrefetcher::getLRUindex(), WriteMask::getMask(), CxxIniFile::getObjectChildren(), X86ISA::getPackedMem(), Prefetcher::PIF::CompactorEntry::getPredictedAddresses(), RubyPrefetcher::getPrefetchEntry(), ArmKvmCPU::getRegList(), PowerISA::RemoteGDB::PowerGdbRegCache::getRegs(), SparcISA::RemoteGDB::SPARCGdbRegCache::getRegs(), ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), IniFile::getSectionNames(), SimpleIndirectPredictor::getSetIndex(), TAGEBase::getSizeInBits(), PowerModel::getStaticPower(), PowerState::getWeights(), Gicv2m::Gicv2m(), StatisticalCorrector::gIndex(), TAGE_SC_L_64KB_StatisticalCorrector::gIndexLogsSubstr(), MPP_StatisticalCorrector::gIndexLogsSubstr(), Debug::Flag::globalDisable(), Debug::Flag::globalEnable(), StatisticalCorrector::gPredict(), GPUDynInst::GPUDynInst(), Stats::HistStor::grow_convert(), Stats::HistStor::grow_out(), Stats::HistStor::grow_up(), MPP_StatisticalCorrector::gUpdate(), StatisticalCorrector::gUpdate(), TAGE_SC_L_TAGE_8KB::handleAllocAndUReset(), TAGE_SC_L_TAGE_64KB::handleAllocAndUReset(), MPP_TAGE::handleAllocAndUReset(), TAGEBase::handleAllocAndUReset(), X86KvmCPU::handleKvmExitIO(), MPP_TAGE::handleUReset(), TAGEBase::handleUReset(), GPUDynInst::hasDestinationSgpr(), GPUDynInst::hasDestinationVgpr(), ComputeUnit::hasDispResources(), BloomFilter::H3::hash(), BloomFilter::MultiBitSel::hash(), BloomFilter::Block::hash(), MultiperspectivePerceptron::MPPBranchInfo::hash(), MultiperspectivePerceptron::GHIST::hash(), MultiperspectivePerceptron::RECENCYPOS::hash(), InstructionQueue< Impl >::hasReadyInsts(), GPUDynInst::hasSgprRawDependence(), GPUDynInst::hasSourceSgpr(), GPUDynInst::hasSourceVgpr(), GPUDynInst::hasVgprRawDependence(), sc_dt::high_half(), HSAPacketProcessor::HSAPacketProcessor(), CacheMemory::htmAbortTransaction(), CacheMemory::htmCommitTransaction(), X86ISA::I8042::I8042(), X86ISA::I82094AA::I82094AA(), X86ISA::I8254::I8254(), X86ISA::I8259::I8259(), IdeController::IdeController(), Stats::InfoAccess::info(), SwitchAllocator::init(), FetchUnit::init(), GarnetNetwork::init(), DirectoryMemory::init(), PerfectSwitch::init(), StoreSet::init(), CacheMemory::init(), AbstractController::init(), RubyTester::init(), Gicv3::init(), sc_dt::sc_lv_base::init(), CpuLocalTimer::init(), BaseCPU::init(), ComputeUnit::init(), ArmISA::SelfDebug::init(), sc_core::sc_vector< svp_gicv3_comms::gicv3_comms_target_socket<> >::init(), MultiperspectivePerceptron::init(), Stats::Vector2dBase< Vector2d, StatStor >::init(), EmbeddedPython::initAll(), TAGE_SC_L_TAGE_8KB::initFoldedHistories(), TAGEBase::initFoldedHistories(), StatisticalCorrector::initGEHLTable(), sc_core::sc_inout< sc_dt::sc_lv< W > >::initialize(), sc_core::sc_inout< bool >::initialize(), sc_core::sc_inout< sc_dt::sc_logic >::initialize(), LSQ< Impl >::SplitDataRequest::initiateTranslation(), X86ISA::X86_64Process::initState(), X86ISA::I386Process::initState(), InputUnit::InputUnit(), SparcISA::TLB::insert(), Trie< Addr, TlbEntry >::insert(), ArmISA::TLB::insert(), MultiperspectivePerceptron::insert(), PowerISA::TLB::insertAt(), MultiperspectivePerceptron::ThreadData::insertRecency(), SparcISA::ISA::installGlobals(), SparcISA::ISA::installWindow(), InstResult::InstResult(), SubBlock::internalMergeFrom(), SubBlock::internalMergeTo(), SparcISA::TlbMap::intersect(), NetDest::intersectionIsNotEmpty(), sc_dt::sc_uint_base::invalid_index(), sc_dt::sc_int_base::invalid_index(), sc_dt::sc_unsigned::invalid_index(), sc_dt::sc_signed::invalid_index(), X86ISA::GpuTLB::invalidateAll(), SMMUTLB::invalidateAll(), ARMArchTLB::invalidateAll(), IPACache::invalidateAll(), ConfigCache::invalidateAll(), WalkCache::invalidateAll(), SMMUTLB::invalidateASID(), ARMArchTLB::invalidateASID(), WalkCache::invalidateASID(), IPACache::invalidateIPA(), IPACache::invalidateIPAA(), X86ISA::GpuTLB::invalidateNonGlobal(), SMMUTLB::invalidateSID(), ConfigCache::invalidateSID(), SMMUTLB::invalidateSSID(), ConfigCache::invalidateSSID(), SMMUTLB::invalidateVA(), ARMArchTLB::invalidateVA(), WalkCache::invalidateVA(), SMMUTLB::invalidateVAA(), ARMArchTLB::invalidateVAA(), WalkCache::invalidateVAA(), SMMUTLB::invalidateVMID(), ARMArchTLB::invalidateVMID(), IPACache::invalidateVMID(), WalkCache::invalidateVMID(), sc_dt::sc_unsigned::invert(), sc_dt::sc_signed::invert(), VIPERCoalescer::invTCP(), GPUComputeDriver::ioctl(), sc_dt::scfx_ieee_double::is_inf(), NetDest::isBroadcast(), ComputeUnit::isDone(), MemDepUnit< MemDepPred, Impl >::isDrained(), FUPool::isDrained(), DefaultFetch< Impl >::isDrained(), NetDest::isEmpty(), WriteMask::isEmpty(), NetDest::isEqual(), WriteMask::isFull(), AQLRingBuffer::isLastOutstandingPkt(), WriteMask::isOverlap(), Compressor::DictionaryCompressor< T >::RepeatedValuePattern< RepT >::isPattern(), DMASequencer::issueNext(), VIPERCoalescer::issueRequest(), NetDest::isSuperset(), MSHR::TargetList::isWholeLineWrite(), KvmVM::KvmVM(), VecPredRegT< VecElem, NumElems, Packed, Const >::lastActive(), Stats::Info::less(), LinearSystem::LinearSystem(), ListenSocket::listen(), ArmISA::Crypto::load2Reg(), ArmISA::Crypto::load3Reg(), CxxConfigManager::loadState(), QoS::MemCtrl::logRequest(), PowerISA::TLB::lookup(), SparcISA::TLB::lookup(), SMMUTLB::lookup(), ARMArchTLB::lookup(), ArmISA::TLB::lookup(), IPACache::lookup(), ConfigCache::lookup(), WalkCache::lookup(), SMMUTLB::lookupAnyVA(), System::lookupRequestorId(), lookupTraceForAddress(), LoopPredictor::loopUpdate(), sc_dt::low_half(), sc_dt::sc_proxy< sc_bv_base >::lrotate(), VGic::lrPending(), VGic::lrValid(), m5Main(), ArmISA::MacroVFPMemOp::MacroVFPMemOp(), SimpleNetwork::makeInternalLink(), Malta::Malta(), PersistentTable::markEntries(), AtagMem::memSize(), AtagMem::memStart(), BloomFilter::Multi::merge(), BloomFilter::Base::merge(), DRAMInterface::minBankPrep(), MinorCPU::MinorCPU(), MinorOpClassSet::MinorOpClassSet(), Minor::Scoreboard::minorTrace(), Minor::MinorBuffer< Minor::ForwardInstData >::minorTrace(), Minor::Execute::minorTrace(), Minor::LSQ::StoreBuffer::minorTrace(), FALRU::CacheTracking::moveBlockToHead(), FALRU::CacheTracking::moveBlockToTail(), sc_dt::scfx_ieee_double::msb(), Network::Network(), NetworkLink::NetworkLink(), sc_gem5::newStaticSensitivityInterface(), TrafficGen::nextState(), tlm::no_b1(), NoncoherentXBar::NoncoherentXBar(), VecPredRegT< VecElem, NumElems, Packed, Const >::noneActive(), number_of_ones(), GPUStaticInst::numDstVecDWORDs(), BaseCPU::numSimulatedInsts(), BaseCPU::numSimulatedOps(), GPUStaticInst::numSrcVecDWORDs(), sc_dt::scfx_rep::o_extend(), sc_dt::scfx_rep::o_set(), sc_dt::scfx_rep::o_set_high(), sc_dt::scfx_rep::o_zero_right(), PersistentTable::okToIssueStarving(), VirtIOConsole::TermTransQueue::onNotifyDescriptor(), CowDiskImage::open(), openatFunc(), VectorRegisterFile::operandsReady(), ScalarRegisterFile::operandsReady(), PerfectSwitch::operateMessageBuffer(), sc_dt::operator!=(), std::hash< FutexKey >::operator()(), sc_core::sc_export< tlm::tlm_fifo_get_if< RSP > >::operator()(), sc_core::sc_sensitive::operator()(), sc_core::sc_in< sc_dt::sc_lv< W > >::operator()(), sc_core::sc_port_b< tlm_nonblocking_put_if< T > >::operator()(), sc_core::sc_in< bool >::operator()(), Stats::VectorPrint::operator()(), sc_core::sc_in< sc_dt::sc_logic >::operator()(), Stats::DistPrint::operator()(), sc_dt::sc_fxnum::operator()(), sc_dt::sc_unsigned::operator()(), sc_dt::sc_fxnum_fast::operator()(), sc_dt::sc_signed::operator()(), LinearEquation::operator+(), TimeBuffer< T >::wire::operator++(), TimeBuffer< T >::wire::operator--(), sc_core::sc_sensitive::operator<<(), operator<<(), sc_core::sc_out_resolved::operator=(), sc_core::sc_inout_resolved::operator=(), sc_core::sc_out_rv< W >::operator=(), sc_core::sc_inout_rv< W >::operator=(), TimeBuffer< T >::wire::operator=(), sc_dt::scfx_mant::operator=(), sc_core::sc_inout< sc_dt::sc_lv< W > >::operator=(), Minor::ForwardInstData::operator=(), sc_core::sc_inout< bool >::operator=(), sc_dt::scfx_mant_ref::operator=(), sc_core::sc_inout< sc_dt::sc_logic >::operator=(), sc_dt::sc_uint_base::operator=(), sc_dt::sc_int_base::operator=(), Net::TcpPtr::operator=(), Net::UdpPtr::operator=(), sc_dt::sc_unsigned::operator=(), sc_dt::sc_signed::operator=(), sc_dt::scfx_mant::operator[](), TypedBufferArg< T >::operator[](), sc_core::sc_vector_assembly< T, MT >::operator[](), sc_dt::sc_fxnum::operator[](), sc_dt::sc_uint_base::operator[](), sc_dt::sc_int_base::operator[](), sc_core::sc_in< sc_dt::sc_int< W > >::operator[](), sc_core::sc_in< sc_dt::sc_uint< W > >::operator[](), sc_dt::sc_unsigned::operator[](), sc_core::sc_in< sc_dt::sc_biguint< W > >::operator[](), sc_core::sc_in< sc_dt::sc_bigint< W > >::operator[](), sc_dt::sc_fxnum_fast::operator[](), sc_dt::sc_signed::operator[](), sc_core::sc_inout< sc_dt::sc_int< W > >::operator[](), sc_core::sc_inout< sc_dt::sc_uint< W > >::operator[](), sc_core::sc_inout< sc_dt::sc_biguint< W > >::operator[](), sc_core::sc_inout< sc_dt::sc_bigint< W > >::operator[](), sc_dt::sc_proxy< sc_bv_base >::operator^=(), NetDest::OR(), sc_dt::sc_unsigned_subref_r::or_reduce(), sc_dt::sc_signed_subref_r::or_reduce(), WriteMask::orMask(), sc_gem5::VcdTraceValFinite< T >::output(), sc_gem5::VcdTraceValFxnum< T >::output(), sc_gem5::VcdTraceValTime::output(), sc_gem5::VcdTraceValInt< T >::output(), OutputUnit::OutputUnit(), QARMA::PACInvSub(), QARMA::PACMult(), QARMA::PACSub(), AtagCore::pagesize(), Net::EthAddr::parse(), MathExpr::parse(), TrafficGen::parseConfig(), PciDevice::PciDevice(), WriteMask::performAtomic(), PersistentTable::persistentRequestLock(), SMMUTLB::pickEntryIdxToReplace(), ARMArchTLB::pickEntryIdxToReplace(), IPACache::pickEntryIdxToReplace(), ConfigCache::pickEntryIdxToReplace(), WalkCache::pickEntryIdxToReplace(), tlm::circular_buffer< RSP >::poke_data(), MaltaCChip::postIntr(), DRAMInterface::prechargeBank(), Stats::DataWrapVec< VectorStandardDeviation, VectorDistInfoProxy >::prepare(), Stats::Vector2dBase< Vector2d, StatStor >::prepare(), Stats::DistStor::prepare(), Stats::HistStor::prepare(), Stats::VectorDistBase< VectorAverageDeviation, AvgSampleStor >::prepare(), preUnflattenMiscReg(), DataBlock::print(), NetDest::print(), RubyPrefetcher::print(), CacheMemory::print(), SparcISA::TlbMap::print(), WriteMask::print(), sc_dt::print_dec(), Packet::PrintReqState::printLabels(), MsrBase::printMsrBase(), printSorted(), System::printSystems(), IniFile::printUnreferenced(), Histogram::printWithMultiplier(), PowerISA::TLB::probeEntry(), Trace::TarmacParserRecord::TarmacParserRecordEvent::process(), QoS::MemSinkCtrl::processNextReqEvent(), HSAPacketProcessor::processPkt(), TLBCoalescer::processProbeTLBEvent(), NVMInterface::processReadReadyEvent(), sc_dt::scfx_rep::q_incr(), Queue< WriteQueueEntry >::Queue(), QTIsaac< ALPHA >::randinit(), MinorCPU::randomPriority(), sc_dt::sc_fxnum::range(), sc_dt::sc_unsigned::range(), sc_dt::sc_fxnum_fast::range(), sc_dt::sc_signed::range(), SimpleDisk::read(), tlm::circular_buffer< RSP >::read(), CowDiskImage::read(), Gcn3ISA::VecOperand< DataType, Const, NumDwords >::read(), Gicv3Redistributor::read(), Gicv3Distributor::read(), Gcn3ISA::ScalarOperand< DataType, Const, sizeof(DataType)/sizeof(VecElemU32) >::read(), VirtQueue::VirtRing< struct vring_used_elem >::read(), TraceCPU::ElasticDataGen::InputStream::read(), VGic::readCtrl(), X86ISA::readPackedMemAtomic(), GPUDynInst::readsExecMask(), GPUDynInst::readsFlatScratch(), VGic::readVCpu(), readvFunc(), PixelConverter::readWord(), FALRU::CacheTracking::recordAccess(), CacheMemory::recordCacheContents(), RubyPort::PioResponsePort::recvAtomic(), SerialLink::SerialLinkResponsePort::recvFunctional(), DRAMSim2::recvFunctional(), Bridge::BridgeResponsePort::recvFunctional(), DRAMsim3::recvFunctional(), recvmsgFunc(), ComputeUnit::DataPort::recvReqRetry(), ComputeUnit::SQCPort::recvReqRetry(), ComputeUnit::DTLBPort::recvReqRetry(), ComputeUnit::ITLBPort::recvReqRetry(), RubyPort::PioResponsePort::recvTimingReq(), TLBCoalescer::CpuSidePort::recvTimingReq(), SimpleMemory::recvTimingReq(), sc_gem5::Port::regPort(), BaseMemProbe::regProbeListeners(), SimpleNetwork::regStats(), Profiler::regStats(), Compressor::BaseDictionaryCompressor::DictionaryStats::regStats(), ExecStage::regStats(), SectorTags::SectorTagsStats::regStats(), Sequencer::regStats(), Compressor::Base::BaseStats::regStats(), GarnetNetwork::regStats(), BaseTags::BaseTagStats::regStats(), QoS::MemCtrl::MemCtrlStats::regStats(), InstructionQueue< Impl >::regStats(), BaseSimpleCPU::regStats(), PowerState::PowerStateStats::regStats(), CacheMemory::regStats(), AbstractMemory::MemStats::regStats(), SMMUv3::regStats(), GPUCoalescer::regStats(), BaseCPU::regStats(), FALRU::CacheTracking::regStats(), BaseXBar::regStats(), MemCtrl::CtrlStats::regStats(), ComputeUnit::regStats(), BaseCache::CacheStats::regStats(), BaseCache::CacheCmdStats::regStatsFromParent(), ComputeUnit::releaseWFsFromBarrier(), SparcISA::ISA::reloadRegMap(), RangeAddrMapper::remapAddr(), PollQueue::remove(), PCEventQueue::remove(), PacketFifo::remove(), OutputDirectory::remove(), sc_core::sc_in< sc_dt::sc_int< W > >::remove_traces(), sc_core::sc_in< sc_dt::sc_uint< W > >::remove_traces(), sc_core::sc_in< sc_dt::sc_biguint< W > >::remove_traces(), sc_core::sc_in< sc_dt::sc_bigint< W > >::remove_traces(), sc_core::sc_inout< sc_dt::sc_int< W > >::remove_traces(), sc_core::sc_inout< sc_dt::sc_uint< W > >::remove_traces(), sc_core::sc_inout< sc_dt::sc_biguint< W > >::remove_traces(), sc_core::sc_inout< sc_dt::sc_bigint< W > >::remove_traces(), BaseRemoteGDB::removeHardBreak(), AddrRange::removeIntlvBits(), NetDest::removeNetDest(), CxxConfigManager::rename(), Minor::ForwardInstData::reportData(), BaseGlobalEvent::reschedule(), ReturnAddrStack::reset(), ArmISA::HTMCheckpoint::reset(), DefaultBTB::reset(), DependencyGraph< DynInstPtr >::reset(), ActivityRecorder::reset(), Sinic::Device::reset(), Stats::DataWrapVec< VectorStandardDeviation, VectorDistInfoProxy >::reset(), MemChecker::reset(), VirtIODeviceBase::reset(), Stats::Vector2dBase< Vector2d, StatStor >::reset(), Stats::DistStor::reset(), Stats::HistStor::reset(), InstructionQueue< Impl >::resetState(), NetworkLink::resetStats(), Sequencer::resetStats(), AbstractController::resetStats(), GarnetNetwork::resetStats(), Router::resetStats(), GPUCoalescer::resetStats(), NetDest::resize(), tlm_utils::instance_specific_extension_container::resize(), sc_dt::scfx_rep::resize_to(), Stats::VectorBase< Vector, StatStor >::result(), Stats::VectorProxy< Stat >::result(), Stats::UnaryNode< Op >::result(), Stats::BinaryNode< Op >::result(), Stats::SumNode< Op >::result(), AtagRev::rev(), AtagCore::rootdev(), MinorCPU::roundRobinPriority(), Gicv3Distributor::route(), RubyPort::RubyPort(), RubyPrefetcher::RubyPrefetcher(), StatTest::run(), Sinic::Device::rxKick(), StackDistCalc::sanityCheckTree(), AQLRingBuffer::saveHostDispAddr(), Prefetcher::SBOOE::SBOOE(), sc_dt::sc_lv_base::sc_lv_base(), SC_MODULE(), sc_core::sc_trace(), sc_core::sc_trace< bool >(), sc_core::sc_trace< sc_dt::sc_logic >(), sc_dt::scfx_mant::scfx_mant(), sc_dt::scfx_rep::scfx_rep(), BaseGlobalEvent::schedule(), BaseGlobalEvent::scheduled(), NetworkInterface::scheduleOutputPort(), VectorRegisterFile::scheduleWriteOperands(), ScalarRegisterFile::scheduleWriteOperands(), VectorRegisterFile::scheduleWriteOperandsFromLoad(), ScalarRegisterFile::scheduleWriteOperandsFromLoad(), FastModel::ScxEvsCortexA76< Types >::ScxEvsCortexA76(), QoS::TurnaroundPolicyIdeal::selectBusState(), selectFunc(), Minor::SelfStallingPipeline< ElemType, ReportTraits, BubbleTraits >::SelfStallingPipeline(), LSQ< Impl >::LSQRequest::sendFragmentToTranslation(), PS2TouchKit::sendTouchKit(), Iris::ISA::serialize(), Iris::Interrupts::serialize(), NoMaliGpu::serialize(), ArmISA::PMU::serialize(), PowerISA::TLB::serialize(), EtherSwitch::Interface::PortFifo::serialize(), Loader::SymbolTable::serialize(), CpuLocalTimer::serialize(), PacketFifo::serialize(), PciDevice::serialize(), ArmSemihosting::serialize(), GenericTimer::serialize(), Sinic::Device::serialize(), CxxConfigManager::serialize(), serialize(), BaseCPU::serialize(), DistIface::RecvScheduler::serialize(), GicV2::serialize(), VirtIODeviceBase::serialize(), PollQueue::service(), BloomFilter::MultiBitSel::set(), WaitClass::set(), sc_dt::scfx_rep::set(), sc_dt::sc_uint_base::set(), sc_dt::sc_int_base::set(), sc_dt::sc_unsigned::set(), sc_dt::sc_signed::set(), sc_dt::scfx_rep::set_bin(), sc_dt::sc_fxnum::set_bit(), VecPredRegContainer< TheISA::VecPredRegSizeBits, TheISA::VecPredRegHasPackedRepr >::set_bits(), sc_dt::sc_subref_r< X >::set_cword(), sc_dt::sc_concref_r< X, Y >::set_cword(), sc_dt::scfx_rep::set_hex(), sc_dt::scfx_rep::set_oct(), sc_core::sc_spawn_options::set_sensitivity(), sc_dt::scfx_rep::set_slice(), sc_dt::sc_fxnum::set_slice(), sc_gem5::TraceFile::set_time_unit(), sc_dt::sc_bv_base::set_word(), sc_dt::sc_subref_r< X >::set_word(), sc_dt::sc_concref_r< X, Y >::set_word(), OutputDirectory::setDirectory(), DistEtherLink::Link::setLocalInt(), WriteMask::setMask(), RegisterManager::setParent(), X86ISA::Interrupts::setReg(), PowerISA::RemoteGDB::PowerGdbRegCache::setRegs(), SparcISA::RemoteGDB::SPARCGdbRegCache::setRegs(), SparcISA::RemoteGDB::SPARC64GdbRegCache::setRegs(), ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), EtherLink::Link::setRxInt(), setThreadArea32Func(), EtherLink::Link::setTxInt(), ArmISA::Crypto::sha256Op(), sc_dt::scfx_rep::shift_left(), sc_dt::scfx_rep::shift_right(), Topology::shortest_path_to_node(), X86ISA::I82094AA::signalInterrupt(), simd_modified_imm(), SimpleCache::SimpleCache(), SimpleIndirectPredictor::SimpleIndirectPredictor(), SimpleNetwork::SimpleNetwork(), simulate(), SkewedAssociative::skew(), NetDest::smallestElement(), Set::smallestElement(), AtagSerial::sn(), GicV2::softInt(), LinearSystem::solve(), DefaultDecode< Impl >::sortInsts(), DefaultRename< Impl >::sortInsts(), DefaultIEW< Impl >::sortInsts(), sc_gem5::spawnWork(), DefaultRename< Impl >::squash(), DefaultDecode< Impl >::squash(), TAGEBase::squash(), QTIsaac< ALPHA >::srand(), StaticInst::srcRegIdx(), BaseDynInst< Impl >::srcRegIdx(), MemChecker::startRead(), MemTraceProbe::startup(), ThermalModel::startup(), System::startup(), MemChecker::startWrite(), Minor::LSQ::StoreBuffer::step(), GuestABI::enable_if< std::is_integral< Integer >::value &&(sizeof(Integer)< sizeof(uint32_t)) >::type >::store(), GuestABI::Result< Aapcs32, Integer, typename std::enable_if< std::is_integral< Integer >::value &&(sizeof(Integer)==sizeof(uint32_t)) >::type >::store(), GuestABI::Result< Aapcs32, Integer, typename std::enable_if< std::is_integral< Integer >::value &&(sizeof(Integer)==sizeof(uint64_t)) >::type >::store(), GuestABI::Result< Aapcs32, Float, typename std::enable_if< std::is_floating_point< Float >::value >::type >::store(), GuestABI::enable_if< std::is_integral< Integer >::value &&(sizeof(Integer)<=8) >::type >::store(), GuestABI::Result< ABI, Ret, Enabled >::type >< Integer >::store(), GuestABI::Result< Aapcs64, HA, typename std::enable_if< IsAapcs64Hxa< HA >::value >::type >::store(), GuestABI::Result< Aapcs64, Composite, typename std::enable_if< IsAapcs64Composite< Composite >::value &&!IsAapcs64Hxa< Composite >::value >::type >::store(), GuestABI::Result< Aapcs32Vfp, HA, typename std::enable_if< IsAapcs32HomogeneousAggregate< HA >::value >::type >::store(), ArmISA::Crypto::store1Reg(), StoreSet::StoreSet(), Stats::ConstVectorNode< T >::str(), SubBlock::SubBlock(), ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemSV(), ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemVI(), ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSI(), ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSS(), ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSI(), ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSS(), UnifiedRenameMap::switchMode(), TAGEBase::tagePredict(), FALRU::tagsInit(), DefaultIEW< Impl >::takeOverFrom(), BaseCPU::takeOverFrom(), TCPIface::TCPIface(), VirtIO9PDiod::terminateDiod(), FastModel::SCGIC::Terminator::Terminator(), TEST(), sc_dt::sc_uint_base::test(), sc_dt::sc_int_base::test(), testAndRead(), testAndReadMask(), testAndWrite(), MultiperspectivePerceptron::ThreadData::ThreadData(), Trace::ArmNativeTrace::ThreadState::ThreadState(), AtomicSimpleCPU::tick(), DefaultFetch< Impl >::tick(), TimeBuffer< DecodeStruct >::TimeBuffer(), GenericTimerMem::timerCtrlRead(), GenericTimerMem::timerCtrlWrite(), to_number(), AddrRange::to_string(), Compressor::Base::toChunks(), Compressor::DictionaryCompressor< uint64_t >::toDictionaryEntry(), Topology::Topology(), LinearEquation::toStr(), Stats::VectorBase< Vector, StatStor >::total(), Stats::VectorProxy< Stat >::total(), Stats::Vector2dBase< Vector2d, StatStor >::total(), Stats::ConstVectorNode< T >::total(), Stats::UnaryNode< Op >::total(), Stats::BinaryNode< Op >::total(), Stats::SumNode< Op >::total(), MinorCPU::totalInsts(), FullO3CPU< O3CPUImpl >::totalInsts(), MinorCPU::totalOps(), FullO3CPU< O3CPUImpl >::totalOps(), TournamentBP::TournamentBP(), Trace::ExeTracerRecord::traceInst(), AbstractMemory::trackLoadLocked(), MultiperspectivePerceptron::train(), PacketQueue::trySatisfyFunctional(), SerialLink::SerialLinkRequestPort::trySatisfyFunctional(), Bridge::BridgeRequestPort::trySatisfyFunctional(), Packet::trySatisfyFunctional(), RubyPort::trySendRetries(), EtherBus::txDone(), PersistentTable::typeOfSmallest(), MultiperspectivePerceptron::uncondBranch(), CxxConfigManager::unRename(), NoMaliGpu::unserialize(), ArmISA::PMU::unserialize(), X86ISA::I82094AA::unserialize(), PowerISA::TLB::unserialize(), EmulationPageTable::unserialize(), EtherSwitch::Interface::PortFifo::unserialize(), DVFSHandler::unserialize(), Loader::SymbolTable::unserialize(), CpuLocalTimer::unserialize(), MemState::unserialize(), PacketFifo::unserialize(), PciDevice::unserialize(), ArmSemihosting::unserialize(), PhysicalMemory::unserialize(), GenericTimer::unserialize(), Sinic::Device::unserialize(), unserialize(), BaseCPU::unserialize(), DistIface::RecvScheduler::unserialize(), GicV2::unserialize(), VirtIODeviceBase::unserialize(), Serializable::unserializeGlobals(), Trace::X86NativeTrace::ThreadState::update(), Trace::ArmNativeTrace::ThreadState::update(), sc_core::sc_signal_rv< W >::update(), Gicv3Distributor::update(), MultiperspectivePerceptron::update(), tlm::tlm_generic_payload::update_extensions_from(), tlm::tlm_generic_payload::update_original_from(), MultiperspectivePerceptron::ThreadData::updateAcyclic(), ArmISA::PMU::updateAllCounters(), TAGEBase::updateGHist(), MultiperspectivePerceptronTAGE::updateHistories(), TAGEBase::updateHistories(), VGic::updateIntState(), ArmV8KvmCPU::updateKvmState(), updateKvmStateFPUCommon(), BaseO3DynInst< Impl >::updateMiscRegs(), TimerTable::updateNext(), MultiperspectivePerceptronTAGE::updatePartial(), MPP_TAGE::updatePathAndGlobalHistory(), TAGE_SC_L_TAGE::updatePathAndGlobalHistory(), TLBCoalescer::updatePhysAddresses(), Trace::TarmacTracerRecordV8::TraceRegEntryV8::updatePred(), GicV2::updateRunPri(), ArmV8KvmCPU::updateThreadContext(), updateThreadContextFPUCommon(), X86KvmCPU::updateThreadContextMSRs(), StackDistCalc::updateTree(), Trace::TarmacTracerRecordV8::TraceRegEntryV8::updateVec(), utimesFunc(), ActivityRecorder::validate(), Checker< O3CPUImpl >::validateExecution(), DefaultRename< Impl >::validInsts(), DefaultIEW< Impl >::validInstsFromRename(), Stats::VectorBase< Vector, StatStor >::value(), sc_core::sc_port_b< tlm_nonblocking_put_if< T > >::vbind(), sc_gem5::VcdTraceFile::VcdTraceFile(), sc_dt::vec_add_small(), sc_dt::vec_complement(), sc_dt::vec_copy(), sc_dt::vec_sub_small(), sc_dt::vec_to_char(), VirtQueue::VirtQueue(), Gicv3CPUInterface::virtualDropPriority(), Gicv3CPUInterface::virtualHighestActivePriority(), Stats::Text::visit(), ArmISA::VldMultOp::VldMultOp(), ArmISA::VldMultOp64::VldMultOp64(), ArmISA::VldSingleOp::VldSingleOp(), ArmISA::VldSingleOp64::VldSingleOp64(), ArmISA::VstMultOp::VstMultOp(), ArmISA::VstMultOp64::VstMultOp64(), ArmISA::VstSingleOp::VstSingleOp(), ArmISA::VstSingleOp64::VstSingleOp64(), sc_core::sc_prim_channel::wait(), sc_core::sc_module::wait(), MemDepUnit< MemDepPred, Impl >::wakeDependents(), WalkCache::WalkCache(), VectorRegisterFile::waveExecuteInst(), ScalarRegisterFile::waveExecuteInst(), Wavefront::Wavefront(), tlm::circular_buffer< RSP >::write(), CowDiskImage::write(), Gicv3Redistributor::write(), Gicv3Distributor::write(), Gcn3ISA::ScalarOperand< DataType, Const, sizeof(DataType)/sizeof(VecElemU32) >::write(), VirtQueue::VirtRing< struct vring_used_elem >::write(), CowDiskImage::writeback(), DefaultIEW< Impl >::writebackInsts(), Packet::writeData(), TraceCPU::ElasticDataGen::GraphNode::writeElementAsTrace(), X86ISA::IntelMP::FloatingPointer::writeOut(), X86ISA::IntelMP::ConfigTable::writeOut(), X86ISA::SMBios::SMBiosTable::writeOut(), writeOutString(), X86ISA::writePackedMem(), GPUDynInst::writesExecMask(), GPUDynInst::writesFlatScratch(), X86ISA::E820Table::writeTo(), VGic::writeVCpu(), writevFunc(), PixelConverter::writeWord(), X86ISA::X86MicroopBase::X86MicroopBase(), X86ISA::Cmos::X86RTC::X86RTC(), sc_dt::sc_unsigned_subref_r::xor_reduce(), sc_dt::sc_signed_subref_r::xor_reduce(), sc_dt::sc_unsigned::xor_reduce(), sc_dt::sc_signed::xor_reduce(), Stats::DataWrapVec2d< Derived, Vector2dInfoProxy >::ysubname(), Stats::DataWrapVec2d< Derived, Vector2dInfoProxy >::ysubnames(), Stats::VectorBase< Vector, StatStor >::zero(), Stats::VectorDistBase< VectorAverageDeviation, AvgSampleStor >::zero(), Stats::Formula::zero(), ArmISA::ISA::zeroSveVecRegUpperPart(), BaseGlobalEvent::~BaseGlobalEvent(), CacheMemory::~CacheMemory(), CheckTable::~CheckTable(), ComputeUnit::~ComputeUnit(), CowDiskImage::~CowDiskImage(), DirectoryMemory::~DirectoryMemory(), Minor::Execute::~Execute(), FUPool::~FUPool(), IniFile::~IniFile(), tlm_utils::instance_specific_extension_container::~instance_specific_extension_container(), MemDepUnit< MemDepPred, Impl >::MemDepEntry::~MemDepEntry(), PollQueue::~PollQueue(), RubyDirectedTester::~RubyDirectedTester(), RubyTester::~RubyTester(), Minor::LSQ::SplitDataRequest::~SplitDataRequest(), TimeBuffer< DecodeStruct >::~TimeBuffer(), Stats::Vector2dBase< Vector2d, StatStor >::~Vector2dBase(), Stats::VectorBase< Vector, StatStor >::~VectorBase(), and Stats::VectorDistBase< VectorAverageDeviation, AvgSampleStor >::~VectorDistBase().

◆ iCacheLineSize

ArmISA::iCacheLineSize

Definition at line 633 of file miscregs_types.hh.

◆ id

Bitfield<33> ArmISA::id

Definition at line 247 of file miscregs_types.hh.

Referenced by ArmISA::PMU::addEventProbe(), QoS::MemCtrl::addRequestor(), ArmISA::PMU::addSoftwareIncrementEvent(), ArmV8KvmCPU::dump(), ArmKvmCPU::dumpKvmStateMisc(), QoS::MemCtrl::escalateQueues(), flit::flit(), GuestABI::Argument< Aapcs32Vfp, Float, typename std::enable_if< std::is_floating_point< Float >::value >::type >::get(), GuestABI::Argument< Aapcs32Vfp, HA, typename std::enable_if< IsAapcs32HomogeneousAggregate< HA >::value >::type >::get(), ArmISA::PMU::getCounter(), BaseKvmCPU::getOneReg(), IDToInt(), LSQUnit< Impl >::init(), ArmProcess32::initState(), ArmProcess64::initState(), System::Threads::insert(), Iris::ThreadContext::installBp(), Iris::ThreadContext::instanceRegistryChanged(), intToID(), sc_dt::sc_fxval_fast::is_inf(), sc_dt::sc_fxval_fast::is_nan(), sc_dt::sc_fxval_fast::is_neg(), sc_dt::sc_fxnum_fast::is_neg(), sc_dt::sc_fxval_fast::is_normal(), sc_dt::sc_fxnum_fast::is_normal(), sc_dt::sc_fxval_fast::is_zero(), sc_dt::sc_fxnum_fast::is_zero(), QoS::MemCtrl::logRequest(), QoS::MemCtrl::logResponse(), System::lookupRequestorId(), OutVcState::OutVcState(), TrafficGen::parseConfig(), sc_dt::sc_fxval_fast::print(), sc_dt::sc_fxnum_fast::print(), sc_core::sc_report::register_id(), tlm_utils::passthrough_target_socket_tagged_b< MODULE, 32, tlm::tlm_base_protocol_types, sc_core::SC_ZERO_OR_MORE_BOUND >::register_transport_dbg(), ArmISA::PMU::registerEvent(), RubySystem::registerRequestorIDs(), System::registerThreadContext(), sc_core::sc_report_handler::report(), Minor::Fetch1::FetchRequest::reportData(), ThreadState::setContextId(), Iris::ThreadContext::setContextId(), BaseKvmCPU::setOneReg(), ThreadState::setThreadId(), Iris::ThreadContext::setThreadId(), Request::setVirt(), GuestABI::Result< Aapcs32Vfp, Float, typename std::enable_if< std::is_floating_point< Float >::value >::type >::store(), GuestABI::Result< Aapcs32Vfp, HA, typename std::enable_if< IsAapcs32HomogeneousAggregate< HA >::value >::type >::store(), BaseCPU::taskId(), Request::taskId(), System::Threads::thread(), and sc_dt::scfx_rep::to_double().

◆ idc

Bitfield<7> ArmISA::idc

Definition at line 432 of file miscregs_types.hh.

◆ ide

Bitfield<15> ArmISA::ide

Definition at line 438 of file miscregs_types.hh.

Referenced by IGbE::TxDescCache::pktComplete().

◆ ids

Bitfield<39, 36> ArmISA::ids

Definition at line 150 of file miscregs_types.hh.

Referenced by Iris::ThreadContext::extractResourceMap().

◆ iesb

Bitfield<15, 12> ArmISA::iesb

Definition at line 156 of file miscregs_types.hh.

◆ il

Bitfield< 25 > ArmISA::il

Definition at line 57 of file miscregs_types.hh.

◆ illegalExecution

Bitfield<61> ArmISA::illegalExecution

Definition at line 71 of file types.hh.

◆ imm

Bitfield<7, 0> ArmISA::imm

◆ imm16

Bitfield<15, 0> ArmISA::imm16

Definition at line 665 of file miscregs_types.hh.

◆ immed11_0

Bitfield<11, 0> ArmISA::immed11_0

Definition at line 145 of file types.hh.

◆ immed23_0

Bitfield<23, 0> ArmISA::immed23_0

Definition at line 155 of file types.hh.

◆ immed7_0

Bitfield<7, 0> ArmISA::immed7_0

Definition at line 146 of file types.hh.

◆ immedHi11_8

Bitfield<11, 8> ArmISA::immedHi11_8

Definition at line 148 of file types.hh.

◆ immedLo3_0

Bitfield<3, 0> ArmISA::immedLo3_0

Definition at line 149 of file types.hh.

◆ imo

Bitfield<4> ArmISA::imo

◆ instBits

uint32_t ArmISA::instBits

Definition at line 96 of file types.hh.

◆ intdis

Bitfield<23, 22> ArmISA::intdis

Definition at line 731 of file miscregs_types.hh.

◆ interptCtrlPresent

Bitfield<23> ArmISA::interptCtrlPresent

Definition at line 626 of file miscregs_types.hh.

◆ IntReg64Map

const IntRegMap ArmISA::IntReg64Map

◆ IntRegAbtMap

const IntRegMap ArmISA::IntRegAbtMap

◆ IntRegFiqMap

const IntRegMap ArmISA::IntRegFiqMap

◆ IntRegHypMap

const IntRegMap ArmISA::IntRegHypMap

◆ IntRegIrqMap

const IntRegMap ArmISA::IntRegIrqMap

◆ IntRegMonMap

const IntRegMap ArmISA::IntRegMonMap

◆ intRegsPerMode

const unsigned ArmISA::intRegsPerMode = NUM_INTREGS
static

Definition at line 459 of file intregs.hh.

Referenced by flattenIntRegModeIndex(), and intRegInMode().

◆ IntRegSvcMap

const IntRegMap ArmISA::IntRegSvcMap

◆ IntRegUndMap

const IntRegMap ArmISA::IntRegUndMap

◆ IntRegUsrMap

const IntRegMap ArmISA::IntRegUsrMap

◆ INTRLVREG0

const int ArmISA::INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs

◆ INTRLVREG1

const int ArmISA::INTRLVREG1 = INTRLVREG0 + 1

Definition at line 123 of file registers.hh.

◆ INTRLVREG2

const int ArmISA::INTRLVREG2 = INTRLVREG0 + 2

Definition at line 124 of file registers.hh.

◆ INTRLVREG3

const int ArmISA::INTRLVREG3 = INTRLVREG0 + 3

Definition at line 125 of file registers.hh.

◆ ioe

Bitfield<8> ArmISA::ioe

Definition at line 433 of file miscregs_types.hh.

◆ ips

Bitfield< 34, 32 > ArmISA::ips

Definition at line 501 of file miscregs_types.hh.

◆ ir0

ArmISA::ir0

Definition at line 592 of file miscregs_types.hh.

◆ ir1

Bitfield<3,2> ArmISA::ir1

Definition at line 593 of file miscregs_types.hh.

◆ ir2

Bitfield<5,4> ArmISA::ir2

Definition at line 594 of file miscregs_types.hh.

◆ ir3

Bitfield<7,6> ArmISA::ir3

Definition at line 595 of file miscregs_types.hh.

◆ ir4

Bitfield<9,8> ArmISA::ir4

Definition at line 596 of file miscregs_types.hh.

◆ ir5

Bitfield<11,10> ArmISA::ir5

Definition at line 597 of file miscregs_types.hh.

◆ ir6

Bitfield<13,12> ArmISA::ir6

Definition at line 598 of file miscregs_types.hh.

◆ ir7

Bitfield<15,14> ArmISA::ir7

Definition at line 599 of file miscregs_types.hh.

◆ irgn0

Bitfield< 9, 8 > ArmISA::irgn0

Definition at line 490 of file miscregs_types.hh.

◆ irgn1

Bitfield< 25, 24 > ArmISA::irgn1

Definition at line 497 of file miscregs_types.hh.

◆ irq

Bitfield<1> ArmISA::irq

Definition at line 327 of file miscregs_types.hh.

Referenced by KvmKernelGicV2::setIntState(), and KvmVM::setIRQLine().

◆ isMisc

Bitfield<32> ArmISA::isMisc

Definition at line 94 of file types.hh.

◆ it1

Bitfield<26, 25> ArmISA::it1

Definition at line 53 of file miscregs_types.hh.

Referenced by FutexMap::requeue().

◆ it2

Bitfield<15, 10> ArmISA::it2

Definition at line 59 of file miscregs_types.hh.

Referenced by FutexMap::requeue().

◆ itd

Bitfield<7> ArmISA::itd

Definition at line 377 of file miscregs_types.hh.

Referenced by getRestoredITBits().

◆ itstate

Bitfield<55, 48> ArmISA::itstate

Definition at line 79 of file types.hh.

◆ itstateCond

Bitfield<55, 52> ArmISA::itstateCond

Definition at line 80 of file types.hh.

◆ itstateMask

Bitfield<51, 48> ArmISA::itstateMask

Definition at line 81 of file types.hh.

◆ ixc

Bitfield<4> ArmISA::ixc

Definition at line 431 of file miscregs_types.hh.

◆ ixe

Bitfield<12> ArmISA::ixe

Definition at line 437 of file miscregs_types.hh.

◆ j

Bitfield<24> ArmISA::j

Definition at line 54 of file miscregs_types.hh.

Referenced by DRAMInterface::activateBank(), Histogram::add(), ArmISA::Crypto::aesInvMixColumns(), ArmISA::Crypto::aesMixColumns(), Aapcs32Vfp::State::allocate(), Set::broadcast(), FALRU::CacheTracking::check(), SwitchAllocator::check_for_wakeup(), ScheduleStage::checkRfOperandReadComplete(), MipsISA::ISA::clear(), SwitchAllocator::clear_request_vector(), CacheMemory::clearLockedAll(), Profiler::collateStats(), GarnetNetwork::collateStats(), Router::collateStats(), ArmISA::WatchPoint::compareAddress(), MemChecker::completeRead(), MultiperspectivePerceptron::computeOutput(), BaseTags::computeStats(), LdsState::countBankConflicts(), crc32(), Topology::createLinks(), Compressor::DictionaryCompressor< uint64_t >::decompress(), ComputeUnit::dispWorkgroup(), DRAMInterface::doBurstAccess(), ObjectMatch::domatch(), Trace::Logger::dump(), dumpFpuCommon(), SimpleLTInitiator2_dmi::end_of_simulation(), SimpleLTInitiator1_dmi::end_of_simulation(), SimpleLTInitiator_ext::end_of_simulation(), FetchUnit::exec(), FetchStage::exec(), ScheduleStage::exec(), Topology::extend_shortest_path(), FetchStage::FetchStage(), ScheduleStage::fillDispatchList(), Minor::FUPipeline::FUPipeline(), FUPool::FUPool(), sc_dt::scfx_rep::get_slice(), sc_dt::sc_fxnum::get_slice(), NetDest::getAllDest(), MultiperspectivePerceptron::PATH::getHash(), MultiperspectivePerceptron::GHISTPATH::getHash(), MultiperspectivePerceptron::SGHISTPATH::getHash(), RubyPrefetcher::getPrefetchEntry(), ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), TAGE_SC_L_TAGE_8KB::handleAllocAndUReset(), TAGE_SC_L_TAGE_64KB::handleAllocAndUReset(), MPP_TAGE::handleUReset(), TAGE_SC_L_TAGE::handleUReset(), TAGEBase::handleUReset(), ComputeUnit::hasDispResources(), GPUDynInst::hasSgprRawDependence(), GPUDynInst::hasVgprRawDependence(), CacheMemory::htmAbortTransaction(), CacheMemory::htmCommitTransaction(), SwitchAllocator::init(), FetchStage::init(), ScheduleStage::init(), CacheMemory::init(), FALRU::CacheTracking::init(), MPP_StatisticalCorrector::initBias(), StatisticalCorrector::initBias(), StatisticalCorrector::initGEHLTable(), MultiperspectivePerceptron::insertModhistSpec(), MultiperspectivePerceptron::insertModpathSpec(), MultiperspectivePerceptron::ThreadData::insertRecency(), SimpleLTInitiator2_dmi::invalidate_direct_mem_ptr(), SimpleLTInitiator1_dmi::invalidate_direct_mem_ptr(), SimpleLTInitiator_ext::invalidate_direct_mem_ptr(), VIPERCoalescer::issueRequest(), QoS::MemCtrl::logRequest(), QoS::MemCtrl::logResponse(), ArmISA::MacroVFPMemOp::MacroVFPMemOp(), DRAMInterface::minBankPrep(), VectorRegisterFile::operandsReady(), ScalarRegisterFile::operandsReady(), sc_dt::sc_fxnum::operator()(), sc_dt::sc_unsigned::operator()(), sc_dt::sc_fxnum_fast::operator()(), sc_dt::sc_signed::operator()(), TrafficGen::parseConfig(), NetDest::print(), CacheMemory::print(), printSorted(), sc_dt::sc_fxnum::range(), sc_dt::sc_unsigned::range(), sc_dt::sc_fxnum_fast::range(), sc_dt::sc_signed::range(), SimpleDisk::read(), TraceCPU::ElasticDataGen::InputStream::read(), CacheMemory::recordCacheContents(), Profiler::regStats(), Sequencer::regStats(), QoS::MemCtrl::MemCtrlStats::regStats(), GPUCoalescer::regStats(), BaseXBar::regStats(), System::regStats(), ComputeUnit::releaseWFsFromBarrier(), ScheduleStage::reserveResources(), Sequencer::resetStats(), InputUnit::resetStats(), GPUCoalescer::resetStats(), sc_dt::scfx_rep::resize(), ScheduleStage::scheduleRfDestOperands(), ScheduleStage::ScheduleStage(), VectorRegisterFile::scheduleWriteOperands(), ScalarRegisterFile::scheduleWriteOperands(), VectorRegisterFile::scheduleWriteOperandsFromLoad(), ScalarRegisterFile::scheduleWriteOperandsFromLoad(), sc_dt::scfx_rep::set_slice(), sc_dt::sc_fxnum::set_slice(), MultiperspectivePerceptron::ACYCLIC::setBitRequirements(), MultiperspectivePerceptron::BLURRYPATH::setBitRequirements(), ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), NetDest::smallestElement(), MultiperspectivePerceptron::ThreadData::ThreadData(), MultiperspectivePerceptron::train(), MultiperspectivePerceptron::update(), MultiperspectivePerceptronTAGE::updateHistories(), ArmV8KvmCPU::updateKvmState(), ArmV8KvmCPU::updateThreadContext(), sc_dt::vec_from_char(), Stats::Text::visit(), VectorRegisterFile::waveExecuteInst(), ScalarRegisterFile::waveExecuteInst(), CacheMemory::~CacheMemory(), ComputeUnit::~ComputeUnit(), Shader::~Shader(), and System::~System().

◆ jscvt

Bitfield<15, 12> ArmISA::jscvt

Definition at line 111 of file miscregs_types.hh.

◆ l1IndexPolicy

Bitfield<15,14> ArmISA::l1IndexPolicy

Definition at line 635 of file miscregs_types.hh.

◆ l2rstDISABLE_monitor

Bitfield<31> ArmISA::l2rstDISABLE_monitor

Definition at line 629 of file miscregs_types.hh.

◆ lbn

Bitfield< 19, 16 > ArmISA::lbn

Definition at line 699 of file miscregs_types.hh.

◆ len

ArmISA::len

Definition at line 439 of file miscregs_types.hh.

Referenced by X86ISA::RemoteGDB::acc(), ArmISA::RemoteGDB::acc(), Loader::DtbFile::addBootCmdLine(), CircularQueue< Prefetcher::STeMS::RegionMissOrderBufferEntry >::advance_tail(), sc_dt::assign_v_(), sc_dt::sc_proxy< sc_bv_base >::check_bounds(), RiscvISA::RemoteGDB::checkBpLen(), X86ISA::RemoteGDB::checkBpLen(), BaseRemoteGDB::checkBpLen(), VncServer::checkProtocolVersion(), BaseRemoteGDB::cmd_clr_hw_bkpt(), BaseRemoteGDB::cmd_mem_r(), BaseRemoteGDB::cmd_mem_w(), BaseRemoteGDB::cmd_set_hw_bkpt(), AtagCmdline::cmdline(), GPUCoalescer::completeIssue(), MultiperspectivePerceptron::computeBits(), sc_dt::concat(), sc_dt::sc_int_subref_r::concat_get_uint64(), PacketFifo::copyout(), DataBlock::copyPartial(), Terminal::data(), DMASequencer::dataCallback(), Trace::Logger::dump(), cp::Print::end_args(), ArmISA::ArmStaticInst::extendReg64(), Net::Ip6Hdr::extensionLength(), fallocateFunc(), Loader::DtbFile::findReleaseAddr(), ArmSemihosting::File::flen(), DmaReadFifo::get(), ArmISA::ISA::getCurSveVecLenInBits(), DataBlock::getData(), WriteMask::getMask(), getsocknameFunc(), getsockoptFunc(), PseudoInst::initParam(), BaseRemoteGDB::insertHardBreak(), BaseRemoteGDB::insertSoftBreak(), sc_dt::sc_proxy< sc_bv_base >::lrotate(), DMASequencer::makeRequest(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::nb_transport_fw(), sc_dt::operator!=(), sc_dt::sc_uint_base::operator=(), sc_dt::sc_int_base::operator=(), sc_dt::sc_unsigned::operator=(), sc_dt::sc_signed::operator=(), Net::IpHdr::options(), Net::TcpHdr::options(), CircleBuf< char >::peek(), Fifo< uint8_t >::peek(), sc_dt::print_dec(), Linux::printk(), cp::Print::process(), VirtQueue::produceDescriptor(), CircleBuf< char >::read(), Terminal::read(), Fifo< uint8_t >::read(), VncServer::read(), VirtIO9PDiod::read(), VirtIO9PSocket::read(), ArmSemihosting::FileFeatures::read(), VncServer::read1(), VirtIO9PProxy::readAll(), PseudoInst::readfile(), ArmSemihosting::readString(), EtherTapStub::recvReal(), ComputeUnit::DataPort::recvReqRetry(), ComputeUnit::SQCPort::recvReqRetry(), ComputeUnit::DTLBPort::recvReqRetry(), ComputeUnit::ITLBPort::recvReqRetry(), PS2TouchKit::recvTouchKit(), BaseRemoteGDB::removeHardBreak(), BaseRemoteGDB::removeSoftBreak(), PacketFifo::reserve(), VncServer::sendError(), EtherTapStub::sendReal(), EtherTapBase::sendSimulated(), DataBlock::setData(), WriteMask::setMask(), setsockoptFunc(), ArmISA::Decoder::setSveLen(), KvmVM::setUserMemoryRegion(), to_lower(), sc_dt::sc_uint_base::to_string(), sc_dt::sc_int_base::to_string(), sc_dt::sc_unsigned::to_string(), sc_dt::sc_signed::to_string(), DmaReadFifo::tryGet(), VirtIOConsole::TermRecvQueue::trySend(), CircleBuf< char >::write(), Terminal::write(), Fifo< uint8_t >::write(), VncServer::write(), VirtIO9PDiod::write(), VirtIO9PSocket::write(), VirtIO9PProxy::writeAll(), PseudoInst::writefile(), and sc_dt::sc_proxy< sc_bv_base >::xor_reduce().

◆ lo

Bitfield<19, 16> ArmISA::lo

Definition at line 137 of file miscregs_types.hh.

Referenced by Trace::TarmacParserRecord::advanceTrace().

◆ loadOp

Bitfield<20> ArmISA::loadOp

Definition at line 136 of file types.hh.

◆ lpae

Bitfield< 11 > ArmISA::lpae

Definition at line 419 of file miscregs_types.hh.

Referenced by ArmISA::TlbEntry::setAttributes().

◆ lrcpc

Bitfield<23, 20> ArmISA::lrcpc

Definition at line 109 of file miscregs_types.hh.

◆ lsm

Bitfield<11, 8> ArmISA::lsm

Definition at line 157 of file miscregs_types.hh.

◆ lsv

Bitfield<4, 3> ArmISA::lsv

Definition at line 718 of file miscregs_types.hh.

◆ ltcoproc

Bitfield<11, 8> ArmISA::ltcoproc

Definition at line 211 of file types.hh.

◆ ltopcode11_8

Bitfield<11, 8> ArmISA::ltopcode11_8

Definition at line 205 of file types.hh.

◆ ltopcode15

Bitfield<15> ArmISA::ltopcode15

Definition at line 204 of file types.hh.

◆ ltopcode4

Bitfield<4> ArmISA::ltopcode4

Definition at line 208 of file types.hh.

◆ ltopcode7_4

Bitfield<7, 4> ArmISA::ltopcode7_4

Definition at line 207 of file types.hh.

◆ ltopcode7_6

Bitfield<7, 6> ArmISA::ltopcode7_6

Definition at line 206 of file types.hh.

◆ ltrd

Bitfield<11, 8> ArmISA::ltrd

Definition at line 210 of file types.hh.

◆ m

Bitfield<0> ArmISA::m

Definition at line 389 of file miscregs_types.hh.

Referenced by PhysicalMemory::access(), SrcClockDomain::clockPeriod(), RealViewOsc::clockPeriod(), PhysicalMemory::createBackingStore(), MessageBuffer::delayHead(), MessageBuffer::enqueueDeferredMessages(), LocalMemPipeline::exec(), GlobalMemPipeline::exec(), ScalarMemPipeline::exec(), NetworkInterface::flitisizeMessage(), PhysicalMemory::functionalAccess(), sc_gem5::Kernel::init(), EmbeddedPyBind::init(), init_drain(), init_loader(), init_net(), init_range(), init_serialize(), QTIsaac< ALPHA >::isaac(), DistEtherLink::LocalIface::LocalIface(), Loader::MemoryImage::mask(), Loader::SymbolTable::mask(), sc_core::operator<<(), sc_gem5::pushParentModule(), pybind_init_event(), pybind_init_stats(), pybind_init_tracers(), Stats::pythonDump(), Stats::pythonReset(), QTIsaac< ALPHA >::randinit(), MessageBuffer::reanalyzeList(), sc_gem5::Kernel::regStats(), sc_gem5::reportIdToMsgMap(), sc_gem5::reportMsgInfoMap(), PybindSimObjectResolver::resolveSimObject(), QTIsaac< ALPHA >::rngstep(), sc_core::sc_export_base::sc_export_base(), sc_core::sc_port_base::sc_port_base(), PhysicalMemory::serialize(), DistEtherLink::TxLink::setDistInt(), DistEtherLink::RxLink::setDistInt(), ArmISA::TLB::setMMU(), ArmISA::TableWalker::setMMU(), KvmVM::setUserMemoryRegion(), Topology::shortest_path_to_node(), sc_gem5::Kernel::startup(), RealViewOsc::startup(), stattest_init_pybind(), sc_gem5::Kernel::stopWork(), PhysicalMemory::unserialize(), DerivedClockDomain::updateClockPeriod(), NetDest::vecIndex(), and Gicv2m::write().

◆ m5Func

Bitfield<15, 8> ArmISA::m5Func

Definition at line 165 of file types.hh.

◆ mask

Bitfield< 3, 0 > ArmISA::mask

Definition at line 711 of file miscregs_types.hh.

Referenced by FALRU::accessBlock(), addPAC(), ArmISA::VectorCatch::addressMatching(), ArmISA::ISA::addressTranslation(), ArmISA::ISA::addressTranslation64(), AddrRange::AddrRange(), ArmProcess::argsInit(), DataBlock::atomicPartial(), auth(), BiModeBP::BiModeBP(), SparcISA::buildPstateMask(), ArmSemihosting::call64(), CopyEngine::CopyEngineChannel::channelWrite(), ArmISA::TLB::checkPermissions(), ArmISA::TLB::checkPermissions64(), ArmISA::WatchPoint::compareAddress(), sc_dt::sc_uint_subref_r::concat_get_ctrl(), sc_dt::sc_int_subref_r::concat_get_ctrl(), sc_dt::sc_uint_base::concat_get_ctrl(), sc_dt::sc_int_base::concat_get_ctrl(), sc_dt::sc_unsigned::concat_get_ctrl(), sc_dt::sc_signed::concat_get_ctrl(), sc_dt::sc_uint_subref_r::concat_get_data(), sc_dt::sc_int_subref_r::concat_get_data(), sc_dt::sc_uint_base::concat_get_data(), sc_dt::sc_int_base::concat_get_data(), sc_dt::sc_unsigned::concat_get_data(), sc_dt::sc_signed::concat_get_data(), sc_dt::sc_signed::concat_get_uint64(), DataBlock::copyPartial(), ArmISA::ArmStaticInst::cpsrWriteByInstr(), GenericPciHost::decodeAddress(), Compressor::DictionaryCompressor< T >::MaskedPattern< mask >::decompress(), GPUDynInst::doApertureCheck(), SparcISA::doNormalFault(), SMMUTranslationProcess::doReadPTE(), SparcISA::doREDFault(), ArmISA::ArmStaticInst::encoding(), ArmISA::VectorCatch::exceptionTrapping(), Gcn3ISA::Inst_SOPK__S_SETREG_B32::execute(), ArmISA::ArmStaticInst::extendReg64(), findParity(), findZero(), finishVfp(), VecPredRegT< VecElem, NumElems, Packed, Const >::firstActive(), fixFpDFpSDest(), fixFpSFpDDest(), GuestABI::Argument< ABI, Arg, Enabled >::type >< Integer >::get(), Prefetcher::DeltaCorrelatingPredictionTables::DCPTEntry::getCandidates(), SparcISA::getHyperVector(), SparcISA::getPrivVector(), AddrRange::granularity(), DMASequencer::init(), PowerISA::PowerStaticInst::insertCRField(), HDLcd::intMask(), PowerISA::IntRotateOp::IntRotateOp(), ArmISA::SelfDebug::isDebugEnabledForEL32(), ArmISA::SelfDebug::isDebugEnabledForEL64(), Compressor::DictionaryCompressor< T >::MaskedPattern< mask >::isPattern(), Compressor::DictionaryCompressor< T >::MaskedValuePattern< 0, 0xFFFFFFFFFFFFFFFF >::isPattern(), Compressor::DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits >::isValidDelta(), KernelWorkload::KernelWorkload(), VecPredRegT< VecElem, NumElems, Packed, Const >::lastActive(), SMMUCommandExecProcess::main(), SparcISA::TLB::MakeTsbPtr(), ArmISA::Stage2LookUp::mergeTe(), mul62x62(), MultiSocketSimpleSwitchAT::MultiSocketSimpleSwitchAT(), BaseCPU::mwait(), BaseCPU::mwaitAtomic(), VecPredRegT< VecElem, NumElems, Packed, Const >::noneActive(), sc_dt::sc_uint_subref::operator=(), sc_dt::sc_int_subref::operator=(), sc_gem5::VcdTraceValInt< T >::output(), V7LPageTableOps::pageMask(), V8PageTableOps4k::pageMask(), V8PageTableOps16k::pageMask(), V8PageTableOps64k::pageMask(), ArmSystem::physAddrMask(), Linux::printk(), SparcISA::ISA::processHSTickCompare(), SparcISA::ISA::processSTickCompare(), ArmISA::TableWalker::processWalkAArch64(), purifyTaggedAddr(), Gcn3ISA::quadMask(), ArmISA::ISA::MiscRegLUTEntryInitializer::rao(), ArmISA::ISA::MiscRegLUTEntryInitializer::raz(), IGbE::read(), ArmISA::ISA::readMiscReg(), ArmISA::ISA::readMiscRegNoEffect(), Iob::receiveDeviceInterrupt(), UFSHostDevice::requestHandler(), ArmISA::ISA::MiscRegLUTEntryInitializer::res0(), ArmISA::ISA::MiscRegLUTEntryInitializer::res1(), GPUDynInst::resolveFlatSegment(), roundDown(), roundUp(), VectorRegisterFile::scheduleWriteOperandsFromLoad(), SMMUTranslationProcess::sendEvent(), Iob::serialize(), ArmISA::SelfDebug::setDebugMask(), SparcISA::ISA::setFSReg(), Pl011::setInterruptMask(), Pl011::setInterrupts(), HDLcd::setInterrupts(), ArmISA::ISA::setMiscReg(), BaseKvmCPU::setSignalMask(), ArmISA::ArmStaticInst::shiftReg64(), ArmISA::ArmStaticInst::spsrWriteByInstr(), stripPAC(), ArmISA::Interrupts::takeInt(), TEST(), testAndReadMask(), AddrRange::to_string(), sc_dt::sc_concatref::to_uint64(), TournamentBP::TournamentBP(), SparcISA::PageTableEntry::translate(), ArmISA::TLB::translateFs(), ArmISA::TLB::translateMmuOn(), ArmISA::TLB::translateSe(), Iob::unserialize(), Flags< FlagsType >< FlagsType >::update(), ArmISA::TlbEntry::updateAttributes(), Prefetcher::SignaturePath::updateSignature(), vcvtFpFpH(), vcvtFpHFp(), sc_dt::vec_to_char(), vfpFpToFixed(), vfpSFixedToFpD(), vfpSFixedToFpS(), V7LPageTableOps::walkMask(), V8PageTableOps4k::walkMask(), V8PageTableOps16k::walkMask(), V8PageTableOps64k::walkMask(), VectorRegisterFile::waveExecuteInst(), Gcn3ISA::wholeQuadMode(), IGbE::write(), GicV2::writeDistributor(), sc_dt::sc_uint_base::xor_reduce(), and sc_dt::sc_int_base::xor_reduce().

◆ MaxInstSrcRegs

const int ArmISA::MaxInstSrcRegs
Initial value:
= ArmISAInst::MaxInstDestRegs +

Definition at line 57 of file registers.hh.

Referenced by TraceCPU::ElasticDataGen::InputStream::read(), and BaseDynInst< Impl >::renamedSrcRegIdx().

◆ MaxPhysAddrRange

const unsigned ArmISA::MaxPhysAddrRange = 48

◆ MaxSveVecLenInBits

constexpr unsigned ArmISA::MaxSveVecLenInBits = 2048
constexpr

Definition at line 809 of file types.hh.

◆ MaxSveVecLenInBytes

constexpr unsigned ArmISA::MaxSveVecLenInBytes = MaxSveVecLenInBits >> 3
constexpr

Definition at line 814 of file types.hh.

◆ MaxSveVecLenInDWords

constexpr unsigned ArmISA::MaxSveVecLenInDWords = MaxSveVecLenInBits >> 6
constexpr

Definition at line 816 of file types.hh.

◆ MaxSveVecLenInWords

constexpr unsigned ArmISA::MaxSveVecLenInWords = MaxSveVecLenInBits >> 5
constexpr

Definition at line 815 of file types.hh.

◆ md

Bitfield<12> ArmISA::md

Definition at line 761 of file miscregs_types.hh.

Referenced by ArmISA::SelfDebug::testDebug().

◆ mdbgen

Bitfield<15> ArmISA::mdbgen

Definition at line 738 of file miscregs_types.hh.

◆ mediaOpcode

Bitfield<24, 20> ArmISA::mediaOpcode

Definition at line 102 of file types.hh.

◆ mf

Bitfield<15> ArmISA::mf

Definition at line 758 of file miscregs_types.hh.

◆ mi

Bitfield<14> ArmISA::mi

Definition at line 759 of file miscregs_types.hh.

Referenced by Trace::InstPBTrace::getInstRecord().

◆ miocnce

Bitfield<38> ArmISA::miocnce

Definition at line 242 of file miscregs_types.hh.

◆ miscOpcode

Bitfield<7, 4> ArmISA::miscOpcode

Definition at line 114 of file types.hh.

◆ miscRegInfo

std::bitset< NUM_MISCREG_INFOS > ArmISA::miscRegInfo

◆ miscRegName

const char* const ArmISA::miscRegName[]

◆ mode

Bitfield<4, 0> ArmISA::mode

Definition at line 70 of file miscregs_types.hh.

Referenced by accessFunc(), ArmISA::ISA::addressTranslation(), ArmISA::ISA::addressTranslation64(), badMode(), badMode32(), ArmSemihosting::callOpen(), ArmISA::TLB::checkPAN(), ArmISA::TLB::checkPermissions(), ArmISA::TLB::checkPermissions64(), chmodFunc(), OutputDirectory::create(), ArmSemihosting::FileBase::create(), decodeMrsMsrBankedReg(), X86ISA::EndBitUnion(), EndBitUnion(), faccessatFunc(), fallocateFunc(), fchmodFunc(), X86ISA::TLB::finalizePhysical(), ArmISA::TLB::finalizePhysical(), DefaultFetch< Impl >::FetchTranslation::finish(), DataTranslation< ExecContextPtr >::finish(), SETranslatingPortProxy::fixupAddr(), flattenIntRegModeIndex(), fp16_add(), fp16_compare_eq(), fp16_compare_ge(), fp16_compare_gt(), fp16_compare_un(), fp16_cvtf(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_process_NaN(), fp16_process_NaNs(), fp16_process_NaNs3(), fp16_round(), fp16_round_(), fp16_scale(), fp16_sqrt(), fp16_unpack(), fp32_add(), fp32_compare_eq(), fp32_compare_ge(), fp32_compare_gt(), fp32_compare_un(), fp32_cvtf(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_process_NaN(), fp32_process_NaNs(), fp32_process_NaNs3(), fp32_round(), fp32_round_(), fp32_scale(), fp32_sqrt(), fp32_unpack(), fp64_add(), fp64_compare_eq(), fp64_compare_ge(), fp64_compare_gt(), fp64_compare_un(), fp64_cvtf(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_process_NaN(), fp64_process_NaNs(), fp64_process_NaNs3(), fp64_round(), fp64_round_(), fp64_scale(), fp64_sqrt(), fp64_unpack(), fplibCompare(), fplibConvert(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), fplibRSqrtStepFused(), fplibTrigSMul(), ArmISA::FpRegImmOp::FpRegImmOp(), ArmISA::FpRegRegImmOp::FpRegRegImmOp(), ArmISA::FpRegRegOp::FpRegRegOp(), ArmISA::FpRegRegRegCondOp::FpRegRegRegCondOp(), ArmISA::FpRegRegRegImmOp::FpRegRegRegImmOp(), ArmISA::FpRegRegRegOp::FpRegRegRegOp(), ArmISA::FpRegRegRegRegOp::FpRegRegRegRegOp(), Shader::functionalTLBAccess(), ArmISA::RfeOp::generateDisassembly(), ArmISA::SrsOp::generateDisassembly(), ArmISA::TLB::getResultTe(), ArmSemihosting::getSTDIO(), ArmISA::TLB::getTE(), X86ISA::GpuTLB::handleFuncTranslationReturn(), X86ISA::GpuTLB::handleTranslationReturn(), HTMSequencer::htmCallback(), illegalExceptionReturn(), TimingSimpleCPU::initiateMemAMO(), TimingSimpleCPU::initiateMemRead(), X86ISA::Walker::WalkerState::initState(), intRegInMode(), ArmISA::ArmFault::invoke64(), mkdirFunc(), mknodFunc(), RawDiskImage::open(), OutputDirectory::open(), openatFunc(), FDArray::openFile(), openFunc(), ArmSemihosting::File::openImpl(), opModeIsH(), opModeIsT(), opModeToEL(), X86ISA::Walker::WalkerState::pageFault(), X86ISA::PageFault::PageFault(), X86ISA::GpuTLB::pagingProtectionChecks(), ArmISA::PairMemOp::PairMemOp(), TrafficGen::parseConfig(), Trace::TarmacTracerRecordV8::TraceInstEntryV8::print(), Trace::TarmacTracerRecord::TraceInstEntry::print(), X86ISA::Walker::WalkerState::recvPacket(), SC_MODULE(), sc_core::sc_set_stop_mode(), X86ISA::I8259::serialize(), ArmSemihosting::FileBase::serialize(), System::setMemoryMode(), setVfpMicroFlags(), X86ISA::Walker::WalkerState::stepWalk(), ArmISA::SelfDebug::testDebug(), ArmISA::TLB::testTranslation(), ArmISA::TLB::testWalk(), X86ISA::TLB::translate(), X86ISA::GpuTLB::translate(), Iris::TLB::translateAtomic(), X86ISA::TLB::translateAtomic(), PowerISA::TLB::translateAtomic(), SparcISA::TLB::translateAtomic(), X86ISA::GpuTLB::translateAtomic(), ArmISA::TLB::translateAtomic(), ArmISA::TLB::translateComplete(), ArmISA::TLB::translateFs(), X86ISA::TLB::translateFunctional(), SparcISA::TLB::translateFunctional(), ArmISA::TLB::translateFunctional(), ArmISA::TLB::translateMmuOff(), ArmISA::TLB::translateMmuOn(), ArmISA::TLB::translateSe(), Iris::TLB::translateTiming(), X86ISA::TLB::translateTiming(), PowerISA::TLB::translateTiming(), SparcISA::TLB::translateTiming(), X86ISA::GpuTLB::translateTiming(), ArmISA::TLB::translateTiming(), TranslatingPortProxy::tryTLBs(), TranslatingPortProxy::tryTLBsOnce(), unknownMode(), unknownMode32(), X86ISA::I8259::unserialize(), Trace::TarmacTracerRecord::TraceRegEntry::updateInt(), WriteAllocator::updateMode(), vcvtFpFpH(), X86ISA::I8259::write(), and TimingSimpleCPU::writeMem().

◆ moe

Bitfield<5, 2> ArmISA::moe

Definition at line 745 of file miscregs_types.hh.

◆ mp

Bitfield<11> ArmISA::mp

◆ mpam

Bitfield<43, 40> ArmISA::mpam

Definition at line 167 of file miscregs_types.hh.

◆ ms

Bitfield<10> ArmISA::ms

Definition at line 763 of file miscregs_types.hh.

◆ n

ArmISA::n

Definition at line 450 of file miscregs_types.hh.

Referenced by sc_core::sc_port_b< tlm_nonblocking_put_if< T > >::_gem5Interface(), ThermalModel::addNode(), DRAMInterface::addRankToRankDelay(), NVMInterface::addRankToRankDelay(), TBETable< ENTRY >::areNSlotsAvailable(), MessageBuffer::areNSlotsAvailable(), atomic_read(), atomic_write(), sc_dt::b_or_assign_(), tlm::circular_buffer< RSP >::buf_free(), tlm::circular_buffer< RSP >::buf_write(), ceilLog2(), DVFSHandler::clkPeriodAtPerfLevel(), sc_dt::convert_to_bin(), NVMInterface::doBurstAccess(), ThermalModel::doStep(), SimpleLTInitiator2_dmi::end_of_simulation(), SimpleLTInitiator1_dmi::end_of_simulation(), SimpleLTInitiator_ext::end_of_simulation(), MathExpr::eval(), Wavefront::exec(), CxxConfigManager::findObject(), sc_dt::sc_bitref_r< T >::get_bit(), sc_dt::sc_subref_r< X >::get_bit(), sc_dt::sc_subref_r< X >::get_cword(), sc_dt::sc_subref_r< X >::get_word(), ThermalResistor::getEquation(), ThermalDomain::getEquation(), ThermalCapacitor::getEquation(), ThermalModel::getTemp(), MathExpr::getVariables(), V7LPageTableOps::index(), SimpleLTInitiator2_dmi::invalidate_direct_mem_ptr(), SimpleLTInitiator1_dmi::invalidate_direct_mem_ptr(), SimpleLTInitiator_ext::invalidate_direct_mem_ptr(), NetDest::isEqual(), isPowerOf2(), sc_gem5::listContains(), sc_dt::sc_proxy< sc_bv_base >::lrotate(), sc_dt::lrotate(), sc_dt::scfx_rep::lshift(), SwitchingFiber::main(), tlm::tlm_fifo< RSP >::nb_peek(), sc_gem5::Object::Object(), sc_core::sc_vector_iter< Element, AccessPolicy >::operator+(), sc_core::sc_vector_iter< Element, AccessPolicy >::operator+=(), sc_core::sc_vector_iter< Element, AccessPolicy >::operator-(), sc_core::sc_vector_iter< Element, AccessPolicy >::operator-=(), sc_dt::operator==(), sc_dt::sc_proxy< sc_bv_base >::operator>>(), sc_core::sc_port_b< tlm_nonblocking_put_if< T > >::operator[](), sc_core::sc_vector_iter< Element, AccessPolicy >::operator[](), sc_dt::operator^(), ArmISA::TableWalker::LongDescriptor::paddr(), MathExpr::parse(), ArmISA::TableWalker::pendingChange(), power(), Linux::printk(), StackDistCalc::printStack(), prlimitFunc(), ArmISA::TableWalker::processWalkLPAE(), sc_dt::quantization_scfx_rep(), X86ISA::SMBios::SMBiosStructure::readString(), ArmISA::HTMCheckpoint::restore(), PowerISA::IntRotateOp::rotateValue(), Stats::DistBase< Distribution, DistStor >::sample(), Stats::DistProxy< Stat >::sample(), Stats::SparseHistBase< SparseHistogram, SparseHistStor >::sample(), ArmISA::HTMCheckpoint::save(), sc_dt::scfx_string::scfx_string(), sc_dt::sc_bitref< X >::set_bit(), FastModel::CortexA76::set_evs_param(), FastModel::CortexA76Cluster::set_evs_param(), sc_dt::scfx_rep::set_hex(), sc_dt::scfx_rep::set_oct(), sc_dt::sc_subref_r< X >::set_word(), ThermalDomain::setNode(), ThermalReference::setNode(), X86ISA::SMBios::SMBiosStructure::setString(), sc_dt::scfx_rep::shift_left(), sc_dt::scfx_rep::shift_right(), ThermalModel::startup(), testPredicate(), sc_dt::sc_proxy< sc_bv_base >::to_string(), MathExpr::toStr(), DVFSHandler::voltageAtPerfLevel(), sc_core::wait(), X86ISA::Cmos::X86RTC::X86RTC(), sc_dt::sc_uint_base::xor_reduce(), and sc_dt::sc_int_base::xor_reduce().

◆ nEt

Bitfield<6> ArmISA::nEt

Definition at line 322 of file miscregs_types.hh.

◆ nmea

Bitfield<20> ArmISA::nmea

Definition at line 307 of file miscregs_types.hh.

◆ nmfi

Bitfield<27> ArmISA::nmfi

Definition at line 337 of file miscregs_types.hh.

Referenced by ArmISA::ArmStaticInst::cpsrWriteByInstr().

◆ nos0

Bitfield<24> ArmISA::nos0

Definition at line 581 of file miscregs_types.hh.

◆ nos1

Bitfield<25> ArmISA::nos1

Definition at line 582 of file miscregs_types.hh.

◆ nos2

Bitfield<26> ArmISA::nos2

Definition at line 583 of file miscregs_types.hh.

◆ nos3

Bitfield<27> ArmISA::nos3

Definition at line 584 of file miscregs_types.hh.

◆ nos4

Bitfield<28> ArmISA::nos4

Definition at line 585 of file miscregs_types.hh.

◆ nos5

Bitfield<29> ArmISA::nos5

Definition at line 586 of file miscregs_types.hh.

◆ nos6

Bitfield<30> ArmISA::nos6

Definition at line 587 of file miscregs_types.hh.

◆ nos7

Bitfield<31> ArmISA::nos7

Definition at line 588 of file miscregs_types.hh.

◆ ns

Bitfield< 18 > ArmISA::ns

◆ ns0

Bitfield<18> ArmISA::ns0

Definition at line 579 of file miscregs_types.hh.

◆ ns1

Bitfield<19> ArmISA::ns1

Definition at line 580 of file miscregs_types.hh.

◆ nsasedis

Bitfield<15> ArmISA::nsasedis

Definition at line 287 of file miscregs_types.hh.

◆ nsd

Bitfield<28> ArmISA::nsd

Definition at line 753 of file miscregs_types.hh.

◆ nsd32dis

Bitfield<14> ArmISA::nsd32dis

Definition at line 288 of file miscregs_types.hh.

◆ nsi

Bitfield<30> ArmISA::nsi

Definition at line 751 of file miscregs_types.hh.

◆ nsp

Bitfield<27> ArmISA::nsp

Definition at line 754 of file miscregs_types.hh.

◆ nss

Bitfield<26> ArmISA::nss

Definition at line 755 of file miscregs_types.hh.

◆ nsu

Bitfield<25> ArmISA::nsu

Definition at line 756 of file miscregs_types.hh.

◆ nTT

Bitfield<2> ArmISA::nTT

Definition at line 691 of file miscregs_types.hh.

◆ ntwe

Bitfield<18> ArmISA::ntwe

Definition at line 356 of file miscregs_types.hh.

◆ ntwi

Bitfield<16> ArmISA::ntwi

Definition at line 359 of file miscregs_types.hh.

◆ NumArgumentRegs

const int ArmISA::NumArgumentRegs = 4

Definition at line 107 of file registers.hh.

Referenced by SparcISA::getArgument(), and getArgument().

◆ NumArgumentRegs64

const int ArmISA::NumArgumentRegs64 = 8

Definition at line 108 of file registers.hh.

◆ NumCCRegs

const int ArmISA::NumCCRegs = NUM_CCREGS

◆ numCPUs

Bitfield<25,24> ArmISA::numCPUs

Definition at line 627 of file miscregs_types.hh.

◆ NumFloatRegs

const int ArmISA::NumFloatRegs = 0

◆ NumFloatV7ArchRegs

const int ArmISA::NumFloatV7ArchRegs = 64

Definition at line 92 of file registers.hh.

◆ NumIntArchRegs

const int ArmISA::NumIntArchRegs = NUM_ARCH_INTREGS

Definition at line 81 of file registers.hh.

Referenced by ArmISA::HTMCheckpoint::restore(), and ArmISA::HTMCheckpoint::save().

◆ NumIntRegs

const int ArmISA::NumIntRegs = NUM_INTREGS

◆ NumMiscRegs

const int ArmISA::NumMiscRegs = NUM_MISCREGS

◆ NumVecElemPerNeonVecReg

constexpr unsigned ArmISA::NumVecElemPerNeonVecReg = 4
constexpr

◆ NumVecElemPerVecReg

constexpr unsigned ArmISA::NumVecElemPerVecReg = MaxSveVecLenInWords
constexpr

◆ NumVecIntrlvRegs

const int ArmISA::NumVecIntrlvRegs = 4

Definition at line 96 of file registers.hh.

◆ NumVecPredRegs

const int ArmISA::NumVecPredRegs = 18

◆ NumVecRegs

const int ArmISA::NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs

◆ NumVecSpecialRegs

const int ArmISA::NumVecSpecialRegs = 8

Definition at line 95 of file registers.hh.

◆ NumVecV7ArchRegs

const int ArmISA::NumVecV7ArchRegs = 16

Definition at line 93 of file registers.hh.

Referenced by Trace::ArmNativeTrace::ThreadState::update().

◆ NumVecV8ArchRegs

const int ArmISA::NumVecV8ArchRegs = 32

◆ nv

Bitfield< 42 > ArmISA::nv

Definition at line 153 of file miscregs_types.hh.

◆ nv1

Bitfield<43> ArmISA::nv1

Definition at line 238 of file miscregs_types.hh.

◆ nv2

Bitfield<45> ArmISA::nv2

Definition at line 236 of file miscregs_types.hh.

◆ nz

ArmISA::nz

Definition at line 49 of file miscregs_types.hh.

Referenced by fplibFPToFixedJS(), and testPredicate().

◆ ofc

Bitfield<2> ArmISA::ofc

Definition at line 429 of file miscregs_types.hh.

◆ ofe

Bitfield<10> ArmISA::ofe

Definition at line 435 of file miscregs_types.hh.

◆ offset

Bitfield<23, 0> ArmISA::offset

Definition at line 153 of file types.hh.

Referenced by _llseekFunc(), IniFile::Section::add(), IniFile::add(), Loader::DtbFile::addBootCmdLine(), Prefetcher::STeMS::ActiveGenerationTableEntry::addOffset(), ArmISA::VfpMacroOp::addStride(), TraceCPU::ElasticDataGen::adjustInitTraceOffset(), ArmISA::BigFpMemRegOp::BigFpMemRegOp(), LSQ< Impl >::SplitDataRequest::buildPackets(), Gcn3ISA::Inst_SMEM::calcAddr(), BaseXBar::calcPacketTiming(), VirtDescriptor::chainRead(), VirtDescriptor::chainWrite(), BaseRemoteGDB::cmd_query_var(), BaseCache::cmpAndSwap(), PacketFifo::copyout(), DataBlock::copyPartial(), GenericTimerMem::counterCtrlRead(), GenericTimerMem::counterCtrlWrite(), Linux::ThreadInfo::curTaskInfo(), Linux::ThreadInfo::curTaskMmFromTaskStruct(), Linux::ThreadInfo::curTaskNameFromTaskStruct(), Linux::ThreadInfo::curTaskPIDFromTaskStruct(), Linux::ThreadInfo::curTaskStartFromTaskStruct(), Linux::ThreadInfo::curTaskTGIDFromTaskStruct(), DMASequencer::dataCallback(), GenericPciHost::decodeAddress(), PseudoInst::decodeAddrOffset(), BaseRemoteGDB::encodeXferResponse(), IdeController::EndBitUnion(), Gcn3ISA::Inst_SOPK__S_SETREG_B32::execute(), Gcn3ISA::Inst_SMEM__S_LOAD_DWORD::execute(), Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX2::execute(), Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX4::execute(), Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX8::execute(), Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX16::execute(), Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORD::execute(), Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX2::execute(), Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX4::execute(), Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX8::execute(), Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX16::execute(), Gcn3ISA::Inst_SMEM__S_STORE_DWORD::execute(), Gcn3ISA::Inst_SMEM__S_STORE_DWORDX2::execute(), Gcn3ISA::Inst_SMEM__S_STORE_DWORDX4::execute(), Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_UBYTE::execute(), Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_USHORT::execute(), Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORD::execute(), Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX2::execute(), Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX3::execute(), Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX4::execute(), Gcn3ISA::Inst_MUBUF__BUFFER_STORE_BYTE::execute(), Gcn3ISA::Inst_MUBUF__BUFFER_STORE_SHORT::execute(), Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORD::execute(), Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX2::execute(), Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX3::execute(), Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX4::execute(), fallocateFunc(), VMA::fillMemPages(), SectorTags::findBlock(), Loader::DtbFile::findReleaseAddr(), CompressedTags::findVictim(), RiscvISA::Load::generateDisassembly(), RiscvISA::Store::generateDisassembly(), ArmISA::MemoryReg64::generateDisassembly(), Gcn3ISA::Inst_DS::generateDisassembly(), GuestABI::Argument< Aapcs32, Composite, typename std::enable_if< IsAapcs32Composite< Composite >::value >::type >::get(), SubBlock::getByte(), DataBlock::getData(), DataBlock::getDataMod(), KvmKernelGicV2::getGicReg(), BaseKvmCPU::getGuestData(), UncoalescedTable::getInstPackets(), WriteMask::getMask(), LSQ< Impl >::SplitDataRequest::handleLocalAccess(), Gcn3ISA::Inst_DS__DS_WRITE_B32::initiateAcc(), Gcn3ISA::Inst_DS__DS_WRITE_B8::initiateAcc(), Gcn3ISA::Inst_DS__DS_WRITE_B16::initiateAcc(), Gcn3ISA::Inst_DS__DS_READ_B32::initiateAcc(), Gcn3ISA::Inst_DS__DS_READ_U8::initiateAcc(), Gcn3ISA::Inst_DS__DS_READ_U16::initiateAcc(), Gcn3ISA::Inst_DS__DS_WRITE_B64::initiateAcc(), Gcn3ISA::Inst_DS__DS_READ_B64::initiateAcc(), Gcn3ISA::Inst_DS::initMemRead(), Gcn3ISA::Inst_DS::initMemWrite(), Shader::initShHiddenPrivateBase(), ArmISA::FsFreebsd::initState(), ArmISA::FsLinux::initState(), SparcISA::ISA::installGlobals(), SparcISA::ISA::installWindow(), SubBlock::internalMergeFrom(), SubBlock::internalMergeTo(), EmulationPageTable::isUnmapped(), ArmISA::MacroVFPMemOp::MacroVFPMemOp(), DMASequencer::makeRequest(), UFSHostDevice::manageReadTransfer(), UFSHostDevice::manageWriteTransfer(), MultiLevelPageTable< EntryTypes >::map(), VMA::MappedFileBuffer::MappedFileBuffer(), MemState::mapRegion(), HSADriver::mmap(), mmap2Func(), mmapFunc(), CowDiskImage::open(), TimeBuffer< T >::wire::operator+=(), TimeBuffer< T >::wire::operator-=(), Stats::Vector2dBase< Vector2d, StatStor >::operator[](), CircleBuf< char >::peek(), WriteMask::performAtomic(), WalkCache::pickSetIdx(), pread64Func(), Prefetcher::Base::PrefetchInfo::PrefetchInfo(), pwrite64Func(), PciVirtIO::read(), MmioVirtIO::read(), RawDiskImage::read(), Gicv2m::read(), CowDiskImage::read(), VirtIOBlock::read(), VirtDescriptor::read(), GenericTimerFrame::read(), IdeDisk::readCommand(), IdeController::readConfig(), PciDevice::readConfig(), SMMUv3::readControl(), IdeDisk::readControl(), PseudoInst::readfile(), UFSHostDevice::UFSSCSIDevice::readFlash(), Iris::ThreadContext::readVecPredReg(), MemCtrl::recvTimingReq(), MultiLevelPageTable< EntryTypes >::remap(), RangeAddrMapper::remapAddr(), GPUDynInst::resolveFlatSegment(), BaseCache::satisfyRequest(), Net::TcpPtr::set(), Net::UdpPtr::set(), SubBlock::setByte(), DataBlock::setData(), KvmKernelGicV2::setGicReg(), WriteMask::setMask(), split_first(), split_last(), Intel8254Timer::Counter::startup(), WriteMask::test(), MemTest::tick(), MultiLevelPageTable< EntryTypes >::unmap(), Intel8254Timer::Counter::unserialize(), MSHR::TargetList::updateWriteFlags(), ArmISA::VldSingleOp::VldSingleOp(), ArmISA::VstSingleOp::VstSingleOp(), MmioVirtIO::write(), PciVirtIO::write(), RawDiskImage::write(), Gicv2m::write(), CowDiskImage::write(), VirtIOBlock::write(), Intel8254Timer::Counter::write(), VirtDescriptor::write(), GenericTimerFrame::write(), IdeDisk::writeCommand(), IdeController::writeConfig(), PciDevice::writeConfig(), NSGigE::writeConfig(), IGbE::writeConfig(), SMMUv3::writeControl(), IdeDisk::writeControl(), GicV2::writeDistributor(), PseudoInst::writefile(), and UFSHostDevice::UFSSCSIDevice::writeFlash().

◆ opc2

Bitfield<7,5> ArmISA::opc2

◆ opcode

Bitfield<24, 21> ArmISA::opcode

◆ opcode15

Bitfield<15> ArmISA::opcode15

Definition at line 113 of file types.hh.

◆ opcode15_12

Bitfield<15, 12> ArmISA::opcode15_12

Definition at line 112 of file types.hh.

◆ opcode18

Bitfield<18> ArmISA::opcode18

Definition at line 111 of file types.hh.

◆ opcode19

Bitfield<19> ArmISA::opcode19

Definition at line 110 of file types.hh.

◆ opcode19_16

Bitfield<19, 16> ArmISA::opcode19_16

Definition at line 109 of file types.hh.

◆ opcode20

Bitfield<20> ArmISA::opcode20

Definition at line 107 of file types.hh.

◆ opcode22

Bitfield<22> ArmISA::opcode22

Definition at line 108 of file types.hh.

◆ opcode23_20

Bitfield<23, 20> ArmISA::opcode23_20

Definition at line 105 of file types.hh.

◆ opcode23_21

Bitfield<23, 21> ArmISA::opcode23_21

Definition at line 106 of file types.hh.

◆ opcode24

Bitfield<24> ArmISA::opcode24

Definition at line 103 of file types.hh.

◆ opcode24_23

Bitfield<24, 23> ArmISA::opcode24_23

Definition at line 104 of file types.hh.

◆ opcode4

Bitfield<4> ArmISA::opcode4

Definition at line 118 of file types.hh.

◆ opcode6

Bitfield<6> ArmISA::opcode6

Definition at line 117 of file types.hh.

◆ opcode7

Bitfield<7> ArmISA::opcode7

Definition at line 116 of file types.hh.

◆ or0

Bitfield<17,16> ArmISA::or0

Definition at line 600 of file miscregs_types.hh.

◆ or1

Bitfield<19,18> ArmISA::or1

Definition at line 601 of file miscregs_types.hh.

◆ or2

Bitfield<21,20> ArmISA::or2

Definition at line 602 of file miscregs_types.hh.

◆ or3

Bitfield<23,22> ArmISA::or3

Definition at line 603 of file miscregs_types.hh.

◆ or4

Bitfield<25,24> ArmISA::or4

Definition at line 604 of file miscregs_types.hh.

◆ or5

Bitfield<27,26> ArmISA::or5

Definition at line 605 of file miscregs_types.hh.

◆ or6

Bitfield<29,28> ArmISA::or6

Definition at line 606 of file miscregs_types.hh.

◆ or7

Bitfield<31,30> ArmISA::or7

Definition at line 607 of file miscregs_types.hh.

◆ orgn0

Bitfield< 11, 10 > ArmISA::orgn0

Definition at line 491 of file miscregs_types.hh.

◆ orgn1

Bitfield< 27, 26 > ArmISA::orgn1

Definition at line 498 of file miscregs_types.hh.

◆ oslk

Bitfield<1> ArmISA::oslk

◆ oslm_0

Bitfield<0> ArmISA::oslm_0

Definition at line 693 of file miscregs_types.hh.

◆ oslm_3

Bitfield<3> ArmISA::oslm_3

Definition at line 690 of file miscregs_types.hh.

◆ pa

Bitfield<39, 12> ArmISA::pa

◆ pac

Bitfield<2, 1> ArmISA::pac

Definition at line 719 of file miscregs_types.hh.

Referenced by ArmISA::WatchPoint::isEnabled().

◆ PageBytes

const Addr ArmISA::PageBytes = ULL(1) << PageShift

◆ PageShift

const Addr ArmISA::PageShift = 12

◆ pan

Bitfield< 23, 20 > ArmISA::pan

Definition at line 55 of file miscregs_types.hh.

Referenced by ArmISA::ISA::setMiscReg().

◆ parange

Bitfield<3, 0> ArmISA::parange

Definition at line 130 of file miscregs_types.hh.

◆ PCReg

const int ArmISA::PCReg = INTREG_PC

◆ pcsample

Bitfield<3,0> ArmISA::pcsample

Definition at line 783 of file miscregs_types.hh.

◆ pd0

Bitfield<4> ArmISA::pd0

Definition at line 484 of file miscregs_types.hh.

◆ pd1

Bitfield<5> ArmISA::pd1

Definition at line 485 of file miscregs_types.hh.

◆ pmc

Bitfield<2, 1> ArmISA::pmc

Definition at line 705 of file miscregs_types.hh.

Referenced by ArmISA::BrkPoint::isEnabled().

◆ pmsver

Bitfield<35, 32> ArmISA::pmsver

Definition at line 77 of file miscregs_types.hh.

◆ pmuver

Bitfield<11, 8> ArmISA::pmuver

Definition at line 81 of file miscregs_types.hh.

◆ PREDREG_FFR

const int ArmISA::PREDREG_FFR = 16

Definition at line 127 of file registers.hh.

◆ PREDREG_UREG0

const int ArmISA::PREDREG_UREG0 = 17

Definition at line 128 of file registers.hh.

◆ procid

Bitfield<31,8> ArmISA::procid

Definition at line 612 of file miscregs_types.hh.

◆ ps

Bitfield< 18, 16 > ArmISA::ps

◆ psruser

Bitfield<22> ArmISA::psruser

Definition at line 134 of file types.hh.

◆ ptw

Bitfield< 8 > ArmISA::ptw

Definition at line 279 of file miscregs_types.hh.

◆ pubwl

ArmISA::pubwl

Definition at line 139 of file types.hh.

◆ punwl

Bitfield<24, 20> ArmISA::punwl

Definition at line 163 of file types.hh.

◆ q

Bitfield<27> ArmISA::q

◆ qc

Bitfield<27> ArmISA::qc

Definition at line 446 of file miscregs_types.hh.

◆ rao2

Bitfield<18> ArmISA::rao2

Definition at line 358 of file miscregs_types.hh.

◆ rao3

Bitfield<16> ArmISA::rao3

Definition at line 361 of file miscregs_types.hh.

◆ rao4

Bitfield<6, 3> ArmISA::rao4

Definition at line 379 of file miscregs_types.hh.

◆ ras

Bitfield<31, 28> ArmISA::ras

Definition at line 170 of file miscregs_types.hh.

◆ raz

Bitfield<31, 28> ArmISA::raz

Definition at line 478 of file miscregs_types.hh.

◆ raz_13_4

Bitfield<13,4> ArmISA::raz_13_4

Definition at line 634 of file miscregs_types.hh.

◆ raz_28

Bitfield<28> ArmISA::raz_28

Definition at line 639 of file miscregs_types.hh.

◆ rd

Bitfield<15, 12> ArmISA::rd

Definition at line 123 of file types.hh.

Referenced by ArmISA::ArmStaticInst::printDataInst().

◆ rdm

Bitfield<31, 28> ArmISA::rdm

Definition at line 95 of file miscregs_types.hh.

◆ recip_sqrt_estimate

const uint8_t ArmISA::recip_sqrt_estimate[256]
static
Initial value:
= {
255, 253, 251, 249, 247, 245, 243, 242, 240, 238, 236, 234, 233, 231, 229, 228,
226, 224, 223, 221, 219, 218, 216, 215, 213, 212, 210, 209, 207, 206, 204, 203,
201, 200, 198, 197, 196, 194, 193, 192, 190, 189, 188, 186, 185, 184, 183, 181,
180, 179, 178, 176, 175, 174, 173, 172, 170, 169, 168, 167, 166, 165, 164, 163,
162, 160, 159, 158, 157, 156, 155, 154, 153, 152, 151, 150, 149, 148, 147, 146,
145, 144, 143, 142, 141, 140, 140, 139, 138, 137, 136, 135, 134, 133, 132, 131,
131, 130, 129, 128, 127, 126, 126, 125, 124, 123, 122, 121, 121, 120, 119, 118,
118, 117, 116, 115, 114, 114, 113, 112, 111, 111, 110, 109, 109, 108, 107, 106,
105, 104, 103, 101, 100, 99, 97, 96, 95, 93, 92, 91, 90, 88, 87, 86,
85, 84, 82, 81, 80, 79, 78, 77, 76, 75, 74, 72, 71, 70, 69, 68,
67, 66, 65, 64, 63, 62, 61, 60, 60, 59, 58, 57, 56, 55, 54, 53,
52, 51, 51, 50, 49, 48, 47, 46, 46, 45, 44, 43, 42, 42, 41, 40,
39, 38, 38, 37, 36, 35, 35, 34, 33, 33, 32, 31, 30, 30, 29, 28,
28, 27, 26, 26, 25, 24, 24, 23, 22, 22, 21, 20, 20, 19, 19, 18,
17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 11, 11, 10, 10, 9, 9,
8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1, 1, 0
}

Definition at line 3507 of file fplib.cc.

Referenced by fplibRSqrtEstimate().

◆ regList

Bitfield<15, 0> ArmISA::regList

Definition at line 151 of file types.hh.

◆ res0

ArmISA::res0

Definition at line 689 of file miscregs_types.hh.

◆ res0_

Bitfield<13> ArmISA::res0_

Definition at line 740 of file miscregs_types.hh.

◆ res0_0

Bitfield< 0 > ArmISA::res0_0

Definition at line 704 of file miscregs_types.hh.

◆ res0_1

Bitfield< 5 > ArmISA::res0_1

Definition at line 702 of file miscregs_types.hh.

◆ res0_2

Bitfield< 9, 8 > ArmISA::res0_2

Definition at line 697 of file miscregs_types.hh.

◆ res0_3

Bitfield< 13 > ArmISA::res0_3

Definition at line 733 of file miscregs_types.hh.

◆ res0_4

Bitfield< 24, 16 > ArmISA::res0_4

Definition at line 730 of file miscregs_types.hh.

◆ res0_5

Bitfield< 29 > ArmISA::res0_5

Definition at line 727 of file miscregs_types.hh.

◆ res1_13_12_el2

Bitfield<13, 12> ArmISA::res1_13_12_el2

Definition at line 675 of file miscregs_types.hh.

◆ res1_7_0_el2

Bitfield<7, 0> ArmISA::res1_7_0_el2

Definition at line 681 of file miscregs_types.hh.

◆ res1_8_el2

Bitfield<8> ArmISA::res1_8_el2

Definition at line 678 of file miscregs_types.hh.

◆ res1_9_el2

Bitfield<9> ArmISA::res1_9_el2

Definition at line 677 of file miscregs_types.hh.

◆ reserved_20_13

Bitfield<20,13> ArmISA::reserved_20_13

Definition at line 623 of file miscregs_types.hh.

◆ reserved_22

Bitfield<22> ArmISA::reserved_22

Definition at line 625 of file miscregs_types.hh.

◆ reserved_30_26

Bitfield<30,26> ArmISA::reserved_30_26

Definition at line 628 of file miscregs_types.hh.

◆ reserved_4_3

Bitfield<4,3> ArmISA::reserved_4_3

Definition at line 617 of file miscregs_types.hh.

◆ ReturnAddressReg

const int ArmISA::ReturnAddressReg = INTREG_LR

◆ ReturnValueReg

const int ArmISA::ReturnValueReg = 0

◆ ReturnValueReg1

const int ArmISA::ReturnValueReg1 = 1

Definition at line 105 of file registers.hh.

◆ ReturnValueReg2

const int ArmISA::ReturnValueReg2 = 2

Definition at line 106 of file registers.hh.

◆ rfr

Bitfield<19> ArmISA::rfr

Definition at line 286 of file miscregs_types.hh.

◆ rm

Bitfield<3, 0> ArmISA::rm

◆ rMode

Bitfield<23, 22> ArmISA::rMode

◆ rn

Bitfield<19, 16> ArmISA::rn

◆ rndr

ArmISA::rndr

Definition at line 87 of file miscregs_types.hh.

◆ rotate

Bitfield<11, 8> ArmISA::rotate

Definition at line 143 of file types.hh.

Referenced by ArmISA::PredIntOp::generateDisassembly().

◆ roundingModes

Bitfield<31, 28> ArmISA::roundingModes

Definition at line 467 of file miscregs_types.hh.

◆ rr

Bitfield<14> ArmISA::rr

Definition at line 364 of file miscregs_types.hh.

◆ rs

Bitfield< 11, 8 > ArmISA::rs

◆ rsvd

Bitfield<29, 28> ArmISA::rsvd

Definition at line 409 of file miscregs_types.hh.

◆ rt

Bitfield<15, 12> ArmISA::rt

◆ rw

Bitfield< 10 > ArmISA::rw

Definition at line 249 of file miscregs_types.hh.

Referenced by Pl111::pixelConverter().

◆ rxfull

Bitfield<30> ArmISA::rxfull

Definition at line 725 of file miscregs_types.hh.

◆ rxo

Bitfield<27> ArmISA::rxo

Definition at line 728 of file miscregs_types.hh.

◆ s

Bitfield< 9 > ArmISA::s

Definition at line 556 of file miscregs_types.hh.

Referenced by IniFile::add(), sc_gem5::Event::addSensitivity(), sc_gem5::Process::addStatic(), sc_dt::scfx_string::append(), sc_core::sc_module::at_negedge(), sc_core::at_negedge(), sc_core::sc_module::at_posedge(), sc_core::at_posedge(), atomic_read(), atomic_write(), tlm_utils::multi_passthrough_initiator_socket< MultiSocketSimpleSwitchAT >::before_end_of_elaboration(), tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::bw_process::bw_process(), Debug::changeFlag(), Prefetcher::AccessMapPatternMatching::checkCandidate(), BaseRemoteGDB::cmd_query_var(), AtagCmdline::cmdline(), sc_dt::concat(), sc_dt::convert_signed_2C_to_SM(), sc_dt::convert_signed_SM_to_2C(), sc_dt::convert_SM_to_2C(), sc_dt::convert_to_bin(), sc_gem5::Event::delSensitivity(), tlm_utils::convenience_socket_cb_holder::display_warning(), ExecStage::dispStatusToStr(), ScheduleStage::doDispatchListTransition(), Stats::VectorBase< Vector, StatStor >::doInit(), Stats::VectorDistBase< VectorAverageDeviation, AvgSampleStor >::doInit(), BaseDynInst< Impl >::dump(), ExecStage::dumpDispList(), eat_end_white(), eat_lead_white(), eat_white(), emptyStrings(), Stats::VectorInfo::enable(), Stats::VectorDistInfo::enable(), ExecStage::exec(), sc_gem5::Port::finalize(), FUPool::FUPool(), GPUDynInst::hasSgprRawDependence(), GPUDynInst::hasVgprRawDependence(), Random::init(), sc_dt::sc_lv_base::init(), sc_gem5::Reset::install(), SMMUTLB::invalidateAll(), ARMArchTLB::invalidateAll(), IPACache::invalidateAll(), ConfigCache::invalidateAll(), WalkCache::invalidateAll(), SMMUTLB::invalidateASID(), ARMArchTLB::invalidateASID(), WalkCache::invalidateASID(), IPACache::invalidateIPAA(), SMMUTLB::invalidateSID(), ConfigCache::invalidateSID(), WalkCache::invalidateVA(), ARMArchTLB::invalidateVAA(), WalkCache::invalidateVAA(), SMMUTLB::invalidateVMID(), ARMArchTLB::invalidateVMID(), IPACache::invalidateVMID(), WalkCache::invalidateVMID(), tlm::tlm_base_target_socket< 64, SignalInterruptFwIf, SignalInterruptBwIf >::kind(), tlm::tlm_base_initiator_socket< 64, SignalInterruptFwIf, SignalInterruptBwIf >::kind(), SMMUTLB::lookupAnyVA(), EmulatedDriver::match(), ArmISA::TableWalker::memAttrs(), sc_dt::mul_signs(), sc_gem5::newDynamicSensitivityEvent(), sc_gem5::newDynamicSensitivityEventAndList(), sc_gem5::newDynamicSensitivityEventOrList(), sc_gem5::newReset(), sc_gem5::newStaticSensitivityEvent(), sc_gem5::newStaticSensitivityExport(), sc_gem5::newStaticSensitivityFinder(), sc_gem5::newStaticSensitivityInterface(), sc_gem5::newStaticSensitivityPort(), sc_gem5::Event::notify(), sc_dt::scfx_rep::operator new(), sc_dt::operator!=(), tlm::tlm_base_target_socket< 64, SignalInterruptFwIf, SignalInterruptBwIf >::operator()(), sc_dt::operator*(), sc_dt::operator/(), tlm::operator<<(), sc_core::operator<<(), parseParam(), MSHR::TargetList::print(), CacheBlk::print(), sc_dt::print_dec(), sc_dt::print_other(), ArmISA::ArmStaticInst::printDataInst(), Linux::printk(), quote(), Random::Random(), recipEstimate(), recipSqrtEstimate(), AbstractController::recvTimingResp(), tlm_utils::simple_target_socket_b< SimpleLTTarget_ext, BUSWIDTH, my_extended_payload_types >::register_transport_dbg(), ExecStage::regStats(), WalkCache::regStats(), EventQueue::replaceHead(), ScheduleStage::reserveResources(), Stats::Group::resetStats(), SyscallReturn::retry(), sc_gem5::Process::satisfySensitivity(), sc_dt::sc_bv_base::sc_bv_base(), SC_MODULE(), sc_dt::sc_concatref::scan(), sc_dt::sc_uint_subref::scan(), sc_dt::sc_int_subref::scan(), sc_dt::sc_uint_base::scan(), sc_dt::sc_int_base::scan(), sc_dt::scfx_parse_base(), sc_dt::scfx_parse_sign(), TCPIface::sendCmd(), PhysicalMemory::serialize(), AbstractController::serviceMemoryQueue(), sc_gem5::Process::setDynamic(), Trace::InstRecord::setMem(), TaggedEntry::setSecure(), KvmVM::setSystem(), SimpleNetwork::SimpleNetwork(), split_first(), split_last(), QTIsaac< ALPHA >::srand(), tlm_utils::simple_target_socket_tagged_b< SimpleBusLT, 32, tlm::tlm_base_protocol_types >::start_of_simulation(), startswith(), sc_gem5::Kernel::status(), sc_gem5::Scheduler::status(), sc_gem5::Process::terminate(), TEST(), to_bool(), sc_dt::sc_fxval_fast::to_dec(), sc_dt::sc_fxnum::to_dec(), sc_dt::sc_fxnum_fast::to_dec(), to_lower(), sc_dt::to_string(), sc_dt::scfx_rep::to_uint64(), tokenize(), Trace::InstPBTrace::traceMem(), sc_dt::trim_unsigned(), PhysicalMemory::~PhysicalMemory(), and sc_gem5::Process::~Process().

◆ sa

Bitfield<3> ArmISA::sa

◆ sa0

Bitfield<4> ArmISA::sa0

Definition at line 384 of file miscregs_types.hh.

◆ sataRAMLatency

ArmISA::sataRAMLatency

Definition at line 616 of file miscregs_types.hh.

◆ sb

Bitfield<39, 36> ArmISA::sb

Definition at line 105 of file miscregs_types.hh.

Referenced by Prefetcher::SBOOE::access().

◆ sc2

Bitfield<19> ArmISA::sc2

Definition at line 734 of file miscregs_types.hh.

Referenced by addPACDA(), addPACDB(), addPACIA(), addPACIB(), authDA(), authDB(), authIA(), and authIB().

◆ scd

Bitfield<7> ArmISA::scd

Definition at line 320 of file miscregs_types.hh.

◆ sd

Bitfield<4> ArmISA::sd

◆ sed

Bitfield<8> ArmISA::sed

Definition at line 374 of file miscregs_types.hh.

Referenced by ArmISA::ArmStaticInst::checkSETENDEnabled().

◆ sel

ArmISA::sel

◆ sel2

Bitfield<39, 36> ArmISA::sel2

Definition at line 168 of file miscregs_types.hh.

◆ sevenAndFour

Bitfield<33> ArmISA::sevenAndFour

Definition at line 93 of file types.hh.

◆ sf

Bitfield<7> ArmISA::sf

Definition at line 765 of file miscregs_types.hh.

◆ sField

Bitfield<20> ArmISA::sField

Definition at line 121 of file types.hh.

◆ sh

Bitfield<8, 7> ArmISA::sh

◆ sh0

Bitfield< 13, 12 > ArmISA::sh0

Definition at line 492 of file miscregs_types.hh.

◆ sh1

Bitfield< 29, 28 > ArmISA::sh1

Definition at line 499 of file miscregs_types.hh.

Referenced by StatTest::init(), and StatTest::run().

◆ sha1

Bitfield<11, 8> ArmISA::sha1

Definition at line 99 of file miscregs_types.hh.

◆ sha2

Bitfield<15, 12> ArmISA::sha2

Definition at line 98 of file miscregs_types.hh.

◆ sha3

Bitfield<35, 32> ArmISA::sha3

Definition at line 94 of file miscregs_types.hh.

◆ shift

Bitfield<6, 5> ArmISA::shift

◆ shiftSize

Bitfield<11, 7> ArmISA::shiftSize

Definition at line 125 of file types.hh.

◆ shortVectors

Bitfield<27, 24> ArmISA::shortVectors

Definition at line 466 of file miscregs_types.hh.

◆ si

Bitfield<6> ArmISA::si

Definition at line 766 of file miscregs_types.hh.

Referenced by GenericISA::BasicDecodeCache::decode(), RiscvISA::Decoder::decode(), Trace::InstPBTrace::getInstRecord(), MathExprPowerModel::getStatValue(), Minor::ExecContext::getWritableVecPredRegOperand(), CheckerCPU::getWritableVecPredRegOperand(), SimpleExecContext::getWritableVecPredRegOperand(), Minor::ExecContext::getWritableVecRegOperand(), CheckerCPU::getWritableVecRegOperand(), SimpleExecContext::getWritableVecRegOperand(), CheckerCPU::readCCRegOperand(), SimpleExecContext::readCCRegOperand(), Minor::ExecContext::readCCRegOperand(), Minor::ExecContext::readFloatRegOperandBits(), SimpleExecContext::readFloatRegOperandBits(), CheckerCPU::readFloatRegOperandBits(), Minor::ExecContext::readIntRegOperand(), SimpleExecContext::readIntRegOperand(), CheckerCPU::readIntRegOperand(), BaseO3DynInst< Impl >::readMiscRegOperand(), SimpleExecContext::readMiscRegOperand(), Minor::ExecContext::readMiscRegOperand(), CheckerCPU::readMiscRegOperand(), CheckerCPU::readVec16BitLaneOperand(), Minor::ExecContext::readVec16BitLaneOperand(), SimpleExecContext::readVec16BitLaneOperand(), CheckerCPU::readVec32BitLaneOperand(), Minor::ExecContext::readVec32BitLaneOperand(), SimpleExecContext::readVec32BitLaneOperand(), CheckerCPU::readVec64BitLaneOperand(), Minor::ExecContext::readVec64BitLaneOperand(), SimpleExecContext::readVec64BitLaneOperand(), CheckerCPU::readVec8BitLaneOperand(), Minor::ExecContext::readVec8BitLaneOperand(), SimpleExecContext::readVec8BitLaneOperand(), Minor::ExecContext::readVecElemOperand(), CheckerCPU::readVecElemOperand(), SimpleExecContext::readVecElemOperand(), SimpleExecContext::readVecLaneOperand(), Minor::ExecContext::readVecPredRegOperand(), CheckerCPU::readVecPredRegOperand(), SimpleExecContext::readVecPredRegOperand(), Minor::ExecContext::readVecRegOperand(), CheckerCPU::readVecRegOperand(), SimpleExecContext::readVecRegOperand(), SimpleExecContext::setCCRegOperand(), CheckerCPU::setCCRegOperand(), BaseO3DynInst< Impl >::setCCRegOperand(), Minor::ExecContext::setCCRegOperand(), SimpleExecContext::setFloatRegOperandBits(), Minor::ExecContext::setFloatRegOperandBits(), CheckerCPU::setFloatRegOperandBits(), BaseO3DynInst< Impl >::setFloatRegOperandBits(), SimpleExecContext::setIntRegOperand(), Minor::ExecContext::setIntRegOperand(), CheckerCPU::setIntRegOperand(), BaseO3DynInst< Impl >::setIntRegOperand(), BaseO3DynInst< Impl >::setMiscRegOperand(), SimpleExecContext::setMiscRegOperand(), Minor::ExecContext::setMiscRegOperand(), CheckerCPU::setMiscRegOperand(), Minor::ExecContext::setVecElemOperand(), SimpleExecContext::setVecElemOperand(), CheckerCPU::setVecElemOperand(), BaseO3DynInst< Impl >::setVecElemOperand(), CheckerCPU::setVecLaneOperand(), Minor::ExecContext::setVecLaneOperand(), SimpleExecContext::setVecLaneOperand(), BaseO3DynInst< Impl >::setVecLaneOperand(), CheckerCPU::setVecLaneOperandT(), Minor::ExecContext::setVecLaneOperandT(), SimpleExecContext::setVecLaneOperandT(), Minor::ExecContext::setVecPredRegOperand(), SimpleExecContext::setVecPredRegOperand(), CheckerCPU::setVecPredRegOperand(), BaseO3DynInst< Impl >::setVecPredRegOperand(), Minor::ExecContext::setVecRegOperand(), SimpleExecContext::setVecRegOperand(), CheckerCPU::setVecRegOperand(), BaseO3DynInst< Impl >::setVecRegOperand(), Trace::InstPBTrace::traceInst(), and Trace::InstPBTrace::traceMem().

◆ sif

Bitfield<9> ArmISA::sif

Definition at line 318 of file miscregs_types.hh.

◆ singlePrecision

Bitfield<7, 4> ArmISA::singlePrecision

Definition at line 461 of file miscregs_types.hh.

◆ sl0

Bitfield<7, 6> ArmISA::sl0

Definition at line 558 of file miscregs_types.hh.

◆ sm3

Bitfield<39, 36> ArmISA::sm3

Definition at line 93 of file miscregs_types.hh.

◆ sm4

Bitfield<43, 40> ArmISA::sm4

Definition at line 92 of file miscregs_types.hh.

◆ smd

Bitfield<7> ArmISA::smd

Definition at line 321 of file miscregs_types.hh.

◆ snsmem

Bitfield<15, 12> ArmISA::snsmem

Definition at line 127 of file miscregs_types.hh.

◆ sp

Bitfield< 3 > ArmISA::sp

◆ span

Bitfield<23> ArmISA::span

Definition at line 345 of file miscregs_types.hh.

Referenced by SMMUTranslationProcess::doReadSTE().

◆ specres

ArmISA::specres

Definition at line 104 of file miscregs_types.hh.

◆ specsei

Bitfield<27, 24> ArmISA::specsei

Definition at line 135 of file miscregs_types.hh.

◆ spiddis

Bitfield<16> ArmISA::spiddis

Definition at line 737 of file miscregs_types.hh.

◆ spniddis

Bitfield<17> ArmISA::spniddis

Definition at line 736 of file miscregs_types.hh.

◆ squareRoot

Bitfield<23, 20> ArmISA::squareRoot

Definition at line 465 of file miscregs_types.hh.

◆ ss

Bitfield< 2 > ArmISA::ss

Definition at line 56 of file miscregs_types.hh.

Referenced by PendingWriteInst::ackWriteCompletion(), UncoalescedTable::checkDeadlock(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::checkTransaction(), GPUCoalescer::coalescePacket(), LSQUnit< Impl >::completeDataAccess(), GPUCoalescer::completeHitCallback(), X86ISA::X86FaultBase::describe(), X86ISA::PageFault::describe(), RegisterFile::dump(), ExecStage::dumpDispList(), dumpSimcall(), TrieTestData::dumpTrie(), sc_core::sc_in_rv< W >::end_of_elaboration(), sc_core::sc_inout_rv< W >::end_of_elaboration(), sc_gem5::Port::finalize(), sc_core::sc_event_finder_t< sc_core::sc_signal_inout_if< bool > >::find_event(), PowerISA::MiscOp::generateDisassembly(), RiscvISA::RegOp::generateDisassembly(), ImmOp64::generateDisassembly(), RiscvISA::MemFenceMicro::generateDisassembly(), MrsOp::generateDisassembly(), RiscvISA::Load::generateDisassembly(), PowerISA::CondLogicOp::generateDisassembly(), ArmISA::DataXImmOp::generateDisassembly(), ArmISA::BranchImm::generateDisassembly(), PowerISA::PowerStaticInst::generateDisassembly(), RiscvISA::LoadReserved::generateDisassembly(), ArmISA::SysDC64::generateDisassembly(), ArmISA::BranchImm64::generateDisassembly(), ArmISAInst::MicroTmeBasic64::generateDisassembly(), RiscvISA::Store::generateDisassembly(), ArmISA::SveIndexIIOp::generateDisassembly(), ArmISA::SveMemVecFillSpill::generateDisassembly(), RegRegImmImmOp64::generateDisassembly(), RiscvISA::LoadReservedMicro::generateDisassembly(), PowerISA::MemDispOp::generateDisassembly(), ArmISA::DataXImmOnlyOp::generateDisassembly(), RiscvISA::SystemOp::generateDisassembly(), ArmISAInst::TmeImmOp64::generateDisassembly(), ArmISA::BranchImmCond64::generateDisassembly(), PowerISA::CondMoveOp::generateDisassembly(), MsrImmOp::generateDisassembly(), RiscvISA::StoreCond::generateDisassembly(), ArmISA::SveIndexIROp::generateDisassembly(), X86ISA::X86StaticInst::generateDisassembly(), ArmISA::BranchReg::generateDisassembly(), PowerISA::IntOp::generateDisassembly(), SparcISA::SparcStaticInst::generateDisassembly(), PowerISA::BranchPCRel::generateDisassembly(), RegRegRegImmOp64::generateDisassembly(), RiscvISA::StoreCondMicro::generateDisassembly(), ArmISAInst::TmeRegNone64::generateDisassembly(), ArmISA::DataXSRegOp::generateDisassembly(), MsrRegOp::generateDisassembly(), ArmISA::SveMemPredFillSpill::generateDisassembly(), ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), ArmISA::BranchRegReg64::generateDisassembly(), RiscvISA::CSROp::generateDisassembly(), ArmISA::SveIndexRIOp::generateDisassembly(), RiscvISA::AtomicMemOp::generateDisassembly(), ArmISA::RfeOp::generateDisassembly(), ArmISA::BranchReg64::generateDisassembly(), RiscvISA::AtomicMemOpMicro::generateDisassembly(), X86ISA::X86MicroopBase::generateDisassembly(), ArmISA::DataXERegOp::generateDisassembly(), MrrcOp::generateDisassembly(), PowerISA::IntImmOp::generateDisassembly(), ArmISA::SveIndexRROp::generateDisassembly(), ArmISA::BranchRegReg::generateDisassembly(), ArmISA::SveContigMemSS::generateDisassembly(), PowerISA::BranchNonPCRel::generateDisassembly(), ArmISA::BranchRet64::generateDisassembly(), ArmISA::DataX1RegOp::generateDisassembly(), McrrOp::generateDisassembly(), ArmISA::SvePredCountOp::generateDisassembly(), PowerISA::IntShiftOp::generateDisassembly(), ArmISA::BranchRetA64::generateDisassembly(), ArmISA::DataX1RegImmOp::generateDisassembly(), ArmISA::MemoryImm64::generateDisassembly(), PowerISA::FloatOp::generateDisassembly(), ImmOp::generateDisassembly(), ArmISA::SveContigMemSI::generateDisassembly(), ArmISA::BranchEret64::generateDisassembly(), ArmISA::SrsOp::generateDisassembly(), ArmISA::SvePredCountPredOp::generateDisassembly(), ArmISA::DataX1Reg2ImmOp::generateDisassembly(), ArmISA::MemoryDImm64::generateDisassembly(), RegImmOp::generateDisassembly(), ArmISA::BranchEretA64::generateDisassembly(), ArmISA::SveWhileOp::generateDisassembly(), ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), MiscRegImmOp64::generateDisassembly(), PowerISA::IntRotateOp::generateDisassembly(), ArmISA::DataX2RegOp::generateDisassembly(), ArmISA::MemoryDImmEx64::generateDisassembly(), RegRegOp::generateDisassembly(), ArmISA::SveCompTermOp::generateDisassembly(), ArmISA::BranchImmReg64::generateDisassembly(), MiscRegRegImmOp64::generateDisassembly(), ArmISA::MemoryPreIndex64::generateDisassembly(), RegOp::generateDisassembly(), ArmISA::DataX2RegImmOp::generateDisassembly(), ArmISA::SveUnaryPredOp::generateDisassembly(), ArmISA::ArmStaticInst::generateDisassembly(), PowerISA::BranchPCRelCond::generateDisassembly(), ArmISA::MemoryPostIndex64::generateDisassembly(), RegMiscRegImmOp64::generateDisassembly(), ArmISA::DataX3RegOp::generateDisassembly(), RegImmRegOp::generateDisassembly(), ArmISA::SveUnaryUnpredOp::generateDisassembly(), ArmISA::BranchImmImmReg64::generateDisassembly(), ArmISA::MemoryReg64::generateDisassembly(), ArmISA::DataXCondCompImmOp::generateDisassembly(), RegRegRegImmOp::generateDisassembly(), ArmISA::SveUnaryWideImmUnpredOp::generateDisassembly(), PowerISA::BranchNonPCRelCond::generateDisassembly(), ArmISA::MemoryRaw64::generateDisassembly(), ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), ArmISA::DataXCondCompRegOp::generateDisassembly(), RegNone::generateDisassembly(), ArmISA::MemoryEx64::generateDisassembly(), RegRegRegRegOp::generateDisassembly(), ArmISA::SveUnaryWideImmPredOp::generateDisassembly(), ArmISA::PredImmOp::generateDisassembly(), PowerISA::BranchRegCond::generateDisassembly(), ArmISA::DataXCondSelOp::generateDisassembly(), ArmISA::MemoryLiteral64::generateDisassembly(), ArmISA::MicroSetPCCPSR::generateDisassembly(), ArmISA::SveBinImmUnpredConstrOp::generateDisassembly(), RegRegRegOp::generateDisassembly(), ArmISA::PredIntOp::generateDisassembly(), ArmISA::SveBinImmPredOp::generateDisassembly(), ArmISA::MicroIntMov::generateDisassembly(), RegRegImmOp::generateDisassembly(), ArmISA::DataImmOp::generateDisassembly(), ArmISA::SveBinWideImmUnpredOp::generateDisassembly(), ArmISA::MicroIntImmOp::generateDisassembly(), MiscRegRegImmOp::generateDisassembly(), ArmISA::DataRegOp::generateDisassembly(), ArmISA::SveBinDestrPredOp::generateDisassembly(), ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), ArmISA::MicroIntImmXOp::generateDisassembly(), RegMiscRegImmOp::generateDisassembly(), ArmISA::DataRegRegOp::generateDisassembly(), ArmISA::SveBinConstrPredOp::generateDisassembly(), ArmISA::MicroIntOp::generateDisassembly(), RegImmImmOp::generateDisassembly(), ArmISA::SveBinUnpredOp::generateDisassembly(), RegRegImmImmOp::generateDisassembly(), ArmISA::MicroIntRegXOp::generateDisassembly(), ArmISA::SveBinIdxUnpredOp::generateDisassembly(), ArmISA::PredMacroOp::generateDisassembly(), ArmISA::MemoryOffset< Base >::generateDisassembly(), RegImmRegShiftOp::generateDisassembly(), ArmISA::SvePredLogicalOp::generateDisassembly(), ArmISA::SvePredBinPermOp::generateDisassembly(), ArmISA::MicroMemOp::generateDisassembly(), ArmISA::SveCmpOp::generateDisassembly(), ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), ArmISA::MicroMemPairOp::generateDisassembly(), ArmISA::MemoryPreIndex< Base >::generateDisassembly(), ArmISA::SveCmpImmOp::generateDisassembly(), ArmISA::SveTerPredOp::generateDisassembly(), ArmISA::SveTerImmUnpredOp::generateDisassembly(), ArmISA::MemoryPostIndex< Base >::generateDisassembly(), ArmISA::SveReducOp::generateDisassembly(), ArmISA::SveOrdReducOp::generateDisassembly(), ArmISA::SvePtrueOp::generateDisassembly(), ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), ArmISA::SveIntCmpOp::generateDisassembly(), ArmISA::SveIntCmpImmOp::generateDisassembly(), ArmISA::SveAdrOp::generateDisassembly(), ArmISA::SveElemCountOp::generateDisassembly(), ArmISA::SvePartBrkOp::generateDisassembly(), ArmISA::SvePartBrkPropOp::generateDisassembly(), ArmISA::SveSelectOp::generateDisassembly(), ArmISA::SveUnaryPredPredOp::generateDisassembly(), ArmISA::SveTblOp::generateDisassembly(), ArmISA::SveUnpackOp::generateDisassembly(), ArmISA::SvePredTestOp::generateDisassembly(), ArmISA::SvePredUnaryWImplicitSrcOp::generateDisassembly(), ArmISA::SvePredUnaryWImplicitSrcPredOp::generateDisassembly(), ArmISA::SvePredUnaryWImplicitDstOp::generateDisassembly(), ArmISA::SveWImplicitSrcDstOp::generateDisassembly(), ArmISA::SveBinImmUnpredDestrOp::generateDisassembly(), ArmISA::SveBinImmIdxUnpredOp::generateDisassembly(), ArmISA::SveUnarySca2VecUnpredOp::generateDisassembly(), ArmISA::SveDotProdIdxOp::generateDisassembly(), ArmISA::SveDotProdOp::generateDisassembly(), ArmISA::SveComplexOp::generateDisassembly(), ArmISA::FpCondCompRegOp::generateDisassembly(), ArmISA::SveComplexIdxOp::generateDisassembly(), ArmISA::FpCondSelOp::generateDisassembly(), ArmISA::FpRegRegOp::generateDisassembly(), ArmISA::FpRegImmOp::generateDisassembly(), ArmISA::FpRegRegImmOp::generateDisassembly(), ArmISA::FpRegRegRegOp::generateDisassembly(), ArmISA::FpRegRegRegCondOp::generateDisassembly(), ArmISA::FpRegRegRegRegOp::generateDisassembly(), ArmISA::FpRegRegRegImmOp::generateDisassembly(), BaseKvmCPU::getAndFormatOneReg(), LdsState::getDynInstr(), ArmISA::ArmStaticInst::getPSTATEFromPSR(), Logger::print(), UncoalescedTable::printRequestTable(), GPUCoalescer::printRequestTable(), NetworkInterface::OutputPort::printVnets(), NetworkInterface::InputPort::printVnets(), LdsState::process(), RubyPort::MemResponsePort::recvTimingReq(), sc_core::sc_port_base::report_error(), ScheduleStage::reserveResources(), sc_core::sc_spawn_options::set_stack_size(), sc_gem5::TraceFile::set_time_unit(), ThermalDomain::setSubSystem(), sc_core::sc_vector_base::size(), TEST(), TEST_F(), sc_core::sc_time::to_string(), sc_core::sc_time_tuple::to_string(), GPUCoalescer::wakeup(), and VIPERCoalescer::writeCompleteCallback().

◆ ssc

Bitfield< 15, 14 > ArmISA::ssc

◆ st

Bitfield< 11 > ArmISA::st

◆ StackPointerReg

const int ArmISA::StackPointerReg = INTREG_SP

◆ status

Bitfield<5, 0> ArmISA::status

Definition at line 417 of file miscregs_types.hh.

Referenced by FullO3CPU< O3CPUImpl >::addThreadToExitingList(), MipsISA::MipsFaultBase::base(), FastModel::ScxEvsCortexA76< Types >::before_end_of_elaboration(), bindFunc(), ArmSemihosting::callIsError(), MipsISA::Interrupts::checkInterrupts(), RiscvISA::TLB::checkPermissions(), FDArray::closeFDEntry(), MipsISA::ISA::configCP(), connectFunc(), RiscvISA::TLB::doTranslate(), FullO3CPU< O3CPUImpl >::drainResume(), IdeController::EndBitUnion(), exitFunc(), exitGroupFunc(), exitImpl(), MipsISA::forkThread(), MipsISA::Interrupts::getInterrupt(), RiscvISA::TLB::getMemPriv(), getsocknameFunc(), getsockoptFunc(), RiscvISA::Interrupts::globalMask(), RiscvISA::Walker::WalkerState::initState(), BaseDynInst< Impl >::initVars(), RiscvISA::RiscvFault::invoke(), RiscvISA::Reset::invoke(), MipsISA::ResetFault::invoke(), ioctlFunc(), listenFunc(), Sequencer::makeRequest(), System::Threads::numRunning(), MipsISA::TlbRefillFault::offset(), VirtIOBlock::RequestQueue::onNotifyDescriptor(), IGbE::RxDescCache::pktComplete(), pollFunc(), Uart8250::processIntrEvent(), Pl050::read(), PS2Mouse::recv(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvTimingReq(), Sinic::Device::rxKick(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::sendBeginResp(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::sendEndReq(), PS2Mouse::serialize(), Pl050::serialize(), VirtIODeviceBase::setDeviceStatus(), MipsISA::MipsFaultBase::setExceptionState(), setsockoptFunc(), BaseDynInst< Impl >::setSquashed(), socketpairFunc(), UFSHostDevice::UFSSCSIDevice::statusCheck(), RiscvISA::Walker::WalkerState::stepWalk(), DrainManager::tryDrain(), PS2Mouse::unserialize(), Pl050::unserialize(), MipsISA::updateStatusView(), MipsISA::updateTCStatusView(), MinorCPU::wakeup(), FullO3CPU< O3CPUImpl >::wakeup(), and PciVirtIO::write().

◆ stride

Bitfield<21, 20> ArmISA::stride

◆ su

Bitfield<1> ArmISA::su

Definition at line 771 of file miscregs_types.hh.

◆ subArchDefined

Bitfield<29, 0> ArmISA::subArchDefined

Definition at line 456 of file miscregs_types.hh.

◆ sve

Bitfield<35, 32> ArmISA::sve

Definition at line 169 of file miscregs_types.hh.

◆ sveLen

Bitfield<59, 56> ArmISA::sveLen

Definition at line 76 of file types.hh.

◆ sw

Bitfield<10> ArmISA::sw

Definition at line 371 of file miscregs_types.hh.

Referenced by sc_dt::operator<<().

◆ swio

Bitfield<1> ArmISA::swio

Definition at line 280 of file miscregs_types.hh.

◆ SyscallNumReg

const int ArmISA::SyscallNumReg = ReturnValueReg

Definition at line 130 of file registers.hh.

Referenced by RiscvLinuxProcess64::syscall(), and RiscvLinuxProcess32::syscall().

◆ SyscallPseudoReturnReg

const int ArmISA::SyscallPseudoReturnReg = ReturnValueReg

◆ SyscallSuccessReg

const int ArmISA::SyscallSuccessReg = ReturnValueReg

Definition at line 132 of file registers.hh.

◆ t

Bitfield<5> ArmISA::t

Definition at line 67 of file miscregs_types.hh.

Referenced by adapt_ext2gp< BUSWIDTH >::adapt_ext2gp(), addPAC(), Prefetcher::Base::addTLB(), ArmSemihosting::ArmSemihosting(), tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::b2nb_thread(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::b_transport(), adapt_gp2ext< BUSWIDTH >::backward_nb_transport(), SimpleATTarget2::beginResponse(), SimpleATTarget1::beginResponse(), BitfieldBackend::bitfieldBackendPrinter(), tlm_utils::simple_target_socket_tagged_b< SimpleBusLT, 32, tlm::tlm_base_protocol_types >::bw_invalidate_direct_mem_ptr(), TAGE_SC_L_TAGE::calculateIndicesAndTags(), IGbE::chkInterrupt(), SparcISA::TLB::clearUsedBits(), sc_dt::concat(), Prefetcher::Queued::DeferredPacket::createPkt(), SimpleBusLT< NR_OF_INITIATORS, NR_OF_TARGETS >::decode(), sc_gem5::Event::delSensitivity(), FullO3CPU< O3CPUImpl >::drain(), HDLcd::PixelPump::dumpSettings(), Packet::findNextSenderState(), adapt_gp2ext< BUSWIDTH >::forward_nb_transport(), MultiSocketSimpleSwitchAT::free(), sc_core::sc_time::from_seconds(), sc_core::sc_time::from_value(), MultiSocketSimpleSwitchAT::fwPEQcb(), Sequencer::getFirstResponseToCompletionDelayHist(), GPUCoalescer::getFirstResponseToCompletionDelayHist(), Sequencer::getForwardRequestToFirstResponseHist(), GPUCoalescer::getForwardRequestToFirstResponseHist(), MultiperspectivePerceptron::RECENCYPOS::getHash(), Sequencer::getHitMachLatencyHist(), Sequencer::getHitTypeLatencyHist(), Sequencer::getHitTypeMachLatencyHist(), Sequencer::getIncompleteTimes(), Sequencer::getInitialToForwardDelayHist(), GPUCoalescer::getInitialToForwardDelayHist(), Sequencer::getIssueToInitialDelayHist(), GPUCoalescer::getIssueToInitialDelayHist(), Sequencer::getMissMachLatencyHist(), GPUCoalescer::getMissMachLatencyHist(), Sequencer::getMissTypeLatencyHist(), GPUCoalescer::getMissTypeLatencyHist(), Sequencer::getMissTypeMachLatencyHist(), GPUCoalescer::getMissTypeMachLatencyHist(), Sequencer::getTypeLatencyHist(), GPUCoalescer::getTypeLatencyHist(), MultiperspectivePerceptron::RECENCYPOS::hash(), sc_core::sc_inout< sc_dt::sc_lv< W > >::initialize(), System::Threads::insert(), TimingSimpleCPU::IprEvent::IprEvent(), SimpleLTInitiator2::logEndTransaction(), SimpleLTInitiator3::logEndTransaction(), SimpleLTInitiator_ext::logEndTransaction(), SimpleLTInitiator1_dmi::logEndTransaction(), SimpleATInitiator2::logEndTransaction(), SimpleATInitiator1::logEndTransaction(), SparcISA::TLB::lookup(), sc_dt::multiply(), SimpleLTTarget_ext::myNBTransport(), tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::nb2b_thread(), tlm::tlm_put_get_imp< RSP, REQ >::nb_can_get(), tlm::tlm_put_get_imp< RSP, REQ >::nb_can_peek(), tlm::tlm_put_get_imp< RSP, REQ >::nb_can_put(), tlm::tlm_put_get_imp< RSP, REQ >::nb_get(), tlm::tlm_put_get_imp< RSP, REQ >::nb_peek(), tlm::tlm_put_get_imp< RSP, REQ >::nb_put(), sc_core::sc_fifo_in< T >::nb_read(), sc_core::sc_fifo< T >::nb_read(), tlm_utils::callback_binder_fw< tlm::tlm_base_protocol_types >::nb_transport_fw(), sc_core::sc_fifo_out< T >::nb_write(), sc_core::sc_fifo< T >::nb_write(), sc_core::sc_prim_channel::next_trigger(), sc_core::sc_module::next_trigger(), sc_core::next_trigger(), sc_core::sc_event_queue::notify(), sc_gem5::Event::notify(), sc_core::sc_event::notify(), sc_core::sc_event::notify_delayed(), sc_gem5::Event::notifyDelayed(), tlm::tlm_put_get_imp< RSP, REQ >::ok_to_get(), tlm::tlm_put_get_imp< RSP, REQ >::ok_to_peek(), tlm::tlm_put_get_imp< RSP, REQ >::ok_to_put(), sc_core::sc_time::operator!=(), sc_core::operator*(), CircularQueue< T >::iterator::operator+(), CircularQueue< T >::iterator::operator++(), sc_core::sc_time::operator+=(), CircularQueue< T >::iterator::operator+=(), CircularQueue< T >::iterator::operator-(), CircularQueue< T >::iterator::operator--(), sc_core::sc_time::operator-=(), CircularQueue< T >::iterator::operator-=(), sc_core::operator/(), sc_core::sc_time::operator<(), sc_core::operator<<(), sc_core::sc_time::operator<=(), sc_core::sc_out< bool >::operator=(), sc_core::sc_time::operator=(), sc_core::sc_inout< sc_dt::sc_lv< W > >::operator=(), sc_core::sc_fifo< T >::operator=(), Net::TcpPtr::operator=(), Net::UdpPtr::operator=(), sc_core::sc_time::operator==(), sc_core::sc_time::operator>(), sc_core::sc_time::operator>=(), TrafficGen::parseConfig(), tlm_utils::peq_with_cb_and_phase< MultiSocketSimpleSwitchAT >::peq_with_cb_and_phase(), BaseDynInst< Impl >::popResult(), SparcISA::PageTableEntry::populate(), MSHR::TargetList::populateFlags(), IGbE::postInterrupt(), WriteQueueEntry::TargetList::print(), MSHR::TargetList::print(), MSHR::promoteDeferredTargets(), MSHR::promoteReadable(), MSHR::promoteWritable(), sc_gem5::NodeList< Process >::pushFirst(), sc_gem5::NodeList< Process >::pushLast(), tlm::tlm_put_get_imp< RSP, REQ >::put(), pybind_init_core(), pybind_init_event(), System::Threads::quiesce(), System::Threads::quiesceTick(), sc_core::sc_fifo_in< T >::read(), sc_core::sc_fifo< T >::read(), RealViewTemperatureSensor::read(), SerialLink::SerialLinkResponsePort::recvTimingReq(), SerialLink::SerialLinkRequestPort::recvTimingResp(), tlm_utils::simple_target_socket_b< SimpleLTTarget_ext, BUSWIDTH, my_extended_payload_types >::register_b_transport(), tlm_utils::simple_target_socket_tagged_b< SimpleBusLT, 32, tlm::tlm_base_protocol_types >::register_get_direct_mem_ptr(), System::Threads::replace(), EventQueue::replaceHead(), MSHR::TargetList::replaceUpgrades(), SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >::RequestThread(), SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >::ResponseThread(), SC_MODULE(), sc_core::sc_start(), sc_core::sc_time::sc_time(), sc_core::sc_time_tuple::sc_time_tuple(), TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(), Consumer::scheduleEventAbsolute(), System::serialize(), Serializable::serializeAll(), CheckerCPU::setScalarResult(), BaseDynInst< Impl >::setScalarResult(), TaggedEntry::setTag(), sc_gem5::Process::setTimeout(), CheckerCPU::setVecElemResult(), BaseDynInst< Impl >::setVecElemResult(), CheckerCPU::setVecPredResult(), BaseDynInst< Impl >::setVecPredResult(), CheckerCPU::setVecResult(), BaseDynInst< Impl >::setVecResult(), StaticInst::simpleAsBytes(), SimpleLTTarget1::SimpleLTTarget1(), LinearSystem::solve(), tlm_utils::simple_target_socket_b< SimpleLTTarget_ext, BUSWIDTH, my_extended_payload_types >::start_of_simulation(), BaseCPU::suspendContext(), Clocked::ticksToCycles(), timeFunc(), tlm::tlm_transport_if< REQ, RSP >::transport(), WriteQueueEntry::TargetList::trySatisfyFunctional(), MSHR::TargetList::trySatisfyFunctional(), SerialLink::SerialLinkResponsePort::trySendTiming(), SerialLink::SerialLinkRequestPort::trySendTiming(), QARMA::tweakCellInvRot(), QARMA::tweakCellRot(), BaseRemoteGDB::TrapEvent::type(), Globals::unserialize(), System::unserialize(), MPP_TAGE::updatePathAndGlobalHistory(), TAGE_SC_L_TAGE::updatePathAndGlobalHistory(), sc_core::sc_prim_channel::wait(), sc_core::sc_module::wait(), sc_core::wait(), sc_core::sc_buffer< T, WRITER_POLICY >::write(), sc_core::sc_fifo_out< T >::write(), sc_core::sc_fifo< T >::write(), sc_core::sc_inout< sc_dt::sc_lv< W > >::write(), sc_gem5::ScSignalBaseT< sc_dt::sc_logic, WRITER_POLICY >::write(), tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::process_handle_list::~process_handle_list(), and tlm_utils::tlm_quantumkeeper::~tlm_quantumkeeper().

◆ t0

Bitfield<0> ArmISA::t0

Definition at line 230 of file miscregs_types.hh.

Referenced by fp16_sqrt(), fp32_sqrt(), fp64_muladd(), mul64x32(), and QARMA::PACMult().

◆ t0sz

ArmISA::t0sz

Definition at line 487 of file miscregs_types.hh.

◆ t0sz64

Bitfield<5, 0> ArmISA::t0sz64

Definition at line 557 of file miscregs_types.hh.

◆ t1

Bitfield<1> ArmISA::t1

◆ t10

Bitfield<10> ArmISA::t10

Definition at line 220 of file miscregs_types.hh.

◆ t11

Bitfield<11> ArmISA::t11

Definition at line 219 of file miscregs_types.hh.

◆ t12

Bitfield<12> ArmISA::t12

Definition at line 218 of file miscregs_types.hh.

◆ t13

Bitfield<13> ArmISA::t13

Definition at line 217 of file miscregs_types.hh.

◆ t15

Bitfield<15> ArmISA::t15

Definition at line 216 of file miscregs_types.hh.

◆ t1sz

Bitfield< 21, 16 > ArmISA::t1sz

Definition at line 494 of file miscregs_types.hh.

◆ t2

Bitfield<2> ArmISA::t2

◆ t2e

Bitfield<6> ArmISA::t2e

Definition at line 488 of file miscregs_types.hh.

◆ t3

Bitfield<3> ArmISA::t3

Definition at line 227 of file miscregs_types.hh.

Referenced by QARMA::PACMult(), and Shader::sampleInstRoundTrip().

◆ t4

Bitfield<4> ArmISA::t4

Definition at line 226 of file miscregs_types.hh.

Referenced by Shader::sampleInstRoundTrip().

◆ t5

Bitfield<5> ArmISA::t5

Definition at line 225 of file miscregs_types.hh.

Referenced by Shader::sampleInstRoundTrip().

◆ t6

Bitfield<6> ArmISA::t6

Definition at line 224 of file miscregs_types.hh.

◆ t7

Bitfield<7> ArmISA::t7

Definition at line 223 of file miscregs_types.hh.

◆ t8

Bitfield<8> ArmISA::t8

Definition at line 222 of file miscregs_types.hh.

◆ t9

Bitfield<9> ArmISA::t9

Definition at line 221 of file miscregs_types.hh.

◆ tac

Bitfield<21> ArmISA::tac

Definition at line 259 of file miscregs_types.hh.

◆ tacr

Bitfield<21> ArmISA::tacr

Definition at line 260 of file miscregs_types.hh.

◆ tagRAMLatency

Bitfield<8,6> ArmISA::tagRAMLatency

Definition at line 619 of file miscregs_types.hh.

◆ tagRAMSetup

Bitfield<9> ArmISA::tagRAMSetup

Definition at line 620 of file miscregs_types.hh.

◆ tagRAMSlice

Bitfield<12> ArmISA::tagRAMSlice

Definition at line 622 of file miscregs_types.hh.

◆ tam

Bitfield<30> ArmISA::tam

Definition at line 670 of file miscregs_types.hh.

◆ tase

Bitfield<15> ArmISA::tase

Definition at line 194 of file miscregs_types.hh.

◆ tbi

Bitfield< 20 > ArmISA::tbi

◆ tbi0

Bitfield< 37 > ArmISA::tbi0

Definition at line 503 of file miscregs_types.hh.

◆ tbi1

Bitfield< 38 > ArmISA::tbi1

Definition at line 504 of file miscregs_types.hh.

◆ tbid

Bitfield<29> ArmISA::tbid

Definition at line 532 of file miscregs_types.hh.

Referenced by computeAddrTop().

◆ tbid0

Bitfield<51> ArmISA::tbid0

Definition at line 542 of file miscregs_types.hh.

◆ tbid1

Bitfield<52> ArmISA::tbid1

Definition at line 543 of file miscregs_types.hh.

◆ tcp0

Bitfield<0> ArmISA::tcp0

Definition at line 210 of file miscregs_types.hh.

◆ tcp1

Bitfield<1> ArmISA::tcp1

Definition at line 209 of file miscregs_types.hh.

◆ tcp10

Bitfield<10> ArmISA::tcp10

Definition at line 198 of file miscregs_types.hh.

◆ tcp11

Bitfield<11> ArmISA::tcp11

Definition at line 197 of file miscregs_types.hh.

◆ tcp12

Bitfield<12> ArmISA::tcp12

Definition at line 196 of file miscregs_types.hh.

◆ tcp13

Bitfield<13> ArmISA::tcp13

Definition at line 195 of file miscregs_types.hh.

◆ tcp2

Bitfield<2> ArmISA::tcp2

Definition at line 208 of file miscregs_types.hh.

◆ tcp3

Bitfield<3> ArmISA::tcp3

Definition at line 207 of file miscregs_types.hh.

◆ tcp4

Bitfield<4> ArmISA::tcp4

Definition at line 206 of file miscregs_types.hh.

◆ tcp5

Bitfield<5> ArmISA::tcp5

Definition at line 205 of file miscregs_types.hh.

◆ tcp6

Bitfield<6> ArmISA::tcp6

Definition at line 204 of file miscregs_types.hh.

◆ tcp7

Bitfield<7> ArmISA::tcp7

Definition at line 203 of file miscregs_types.hh.

◆ tcp8

Bitfield<8> ArmISA::tcp8

Definition at line 201 of file miscregs_types.hh.

◆ tcp9

Bitfield<9> ArmISA::tcp9

Definition at line 200 of file miscregs_types.hh.

◆ tda

Bitfield< 21 > ArmISA::tda

Definition at line 183 of file miscregs_types.hh.

◆ tdcc

Bitfield<12> ArmISA::tdcc

Definition at line 742 of file miscregs_types.hh.

◆ tde

Bitfield<8> ArmISA::tde

Definition at line 184 of file miscregs_types.hh.

◆ tdosa

Bitfield<10> ArmISA::tdosa

Definition at line 182 of file miscregs_types.hh.

◆ tdz

Bitfield<28> ArmISA::tdz

Definition at line 252 of file miscregs_types.hh.

◆ te

Bitfield<30> ArmISA::te

◆ tea

Bitfield<37> ArmISA::tea

Definition at line 243 of file miscregs_types.hh.

◆ teer

Bitfield<15> ArmISA::teer

Definition at line 312 of file miscregs_types.hh.

◆ terr

Bitfield<36> ArmISA::terr

Definition at line 244 of file miscregs_types.hh.

◆ tfp

Bitfield< 10 > ArmISA::tfp

Definition at line 199 of file miscregs_types.hh.

◆ tg0

Bitfield< 15, 14 > ArmISA::tg0

Definition at line 493 of file miscregs_types.hh.

◆ tg1

Bitfield< 31, 30 > ArmISA::tg1

Definition at line 500 of file miscregs_types.hh.

◆ tge

Bitfield<27> ArmISA::tge

Definition at line 253 of file miscregs_types.hh.

◆ tgran16

Bitfield<23, 20> ArmISA::tgran16

Definition at line 125 of file miscregs_types.hh.

◆ tgran16_2

Bitfield<35, 32> ArmISA::tgran16_2

Definition at line 122 of file miscregs_types.hh.

◆ tgran4

Bitfield<31, 28> ArmISA::tgran4

Definition at line 123 of file miscregs_types.hh.

◆ tgran4_2

Bitfield<43, 40> ArmISA::tgran4_2

Definition at line 120 of file miscregs_types.hh.

◆ tgran64

Bitfield<27, 24> ArmISA::tgran64

Definition at line 124 of file miscregs_types.hh.

◆ tgran64_2

Bitfield<39, 36> ArmISA::tgran64_2

Definition at line 121 of file miscregs_types.hh.

◆ thee

Bitfield<6> ArmISA::thee

Definition at line 380 of file miscregs_types.hh.

◆ thumb

Bitfield<36> ArmISA::thumb

◆ tid0

Bitfield<15> ArmISA::tid0

Definition at line 266 of file miscregs_types.hh.

◆ tid1

Bitfield<16> ArmISA::tid1

Definition at line 265 of file miscregs_types.hh.

◆ tid2

Bitfield<17> ArmISA::tid2

Definition at line 264 of file miscregs_types.hh.

◆ tid3

Bitfield<18> ArmISA::tid3

Definition at line 263 of file miscregs_types.hh.

◆ tidcp

Bitfield<20> ArmISA::tidcp

Definition at line 261 of file miscregs_types.hh.

◆ tlb

Bitfield<59, 56> ArmISA::tlb

Definition at line 88 of file miscregs_types.hh.

Referenced by RiscvISA::RemoteGDB::acc(), getDTBPtr(), and getITBPtr().

◆ tlor

Bitfield< 14 > ArmISA::tlor

Definition at line 245 of file miscregs_types.hh.

◆ top6

Bitfield<7, 2> ArmISA::top6

Definition at line 64 of file types.hh.

◆ topcode10_8

Bitfield<10, 8> ArmISA::topcode10_8

Definition at line 175 of file types.hh.

◆ topcode10_9

Bitfield<10, 9> ArmISA::topcode10_9

Definition at line 174 of file types.hh.

◆ topcode11_8

Bitfield<11, 8> ArmISA::topcode11_8

Definition at line 173 of file types.hh.

◆ topcode11_9

Bitfield<11, 9> ArmISA::topcode11_9

Definition at line 172 of file types.hh.

◆ topcode12_10

Bitfield<12, 10> ArmISA::topcode12_10

Definition at line 171 of file types.hh.

◆ topcode12_11

Bitfield<12, 11> ArmISA::topcode12_11

Definition at line 170 of file types.hh.

◆ topcode13_11

Bitfield<13, 11> ArmISA::topcode13_11

Definition at line 169 of file types.hh.

◆ topcode15_13

Bitfield<15, 13> ArmISA::topcode15_13

Definition at line 168 of file types.hh.

◆ topcode3_0

Bitfield<3, 0> ArmISA::topcode3_0

Definition at line 181 of file types.hh.

◆ topcode7

Bitfield<7> ArmISA::topcode7

Definition at line 177 of file types.hh.

◆ topcode7_4

Bitfield<7, 4> ArmISA::topcode7_4

Definition at line 180 of file types.hh.

◆ topcode7_5

Bitfield<7, 5> ArmISA::topcode7_5

Definition at line 179 of file types.hh.

◆ topcode7_6

Bitfield<7, 6> ArmISA::topcode7_6

Definition at line 178 of file types.hh.

◆ topcode9_6

Bitfield<9, 6> ArmISA::topcode9_6

Definition at line 176 of file types.hh.

◆ TotalNumRegs

const int ArmISA::TotalNumRegs
Initial value:

Definition at line 100 of file registers.hh.

◆ tpc

Bitfield<23> ArmISA::tpc

Definition at line 257 of file miscregs_types.hh.

◆ tpm

Bitfield<6> ArmISA::tpm

Definition at line 186 of file miscregs_types.hh.

◆ tpmcr

Bitfield<5> ArmISA::tpmcr

Definition at line 187 of file miscregs_types.hh.

◆ tpu

Bitfield<24> ArmISA::tpu

Definition at line 256 of file miscregs_types.hh.

◆ tr0

ArmISA::tr0

Definition at line 569 of file miscregs_types.hh.

◆ tr1

Bitfield<3,2> ArmISA::tr1

Definition at line 570 of file miscregs_types.hh.

◆ tr2

Bitfield<5,4> ArmISA::tr2

Definition at line 571 of file miscregs_types.hh.

◆ tr3

Bitfield<7,6> ArmISA::tr3

Definition at line 572 of file miscregs_types.hh.

◆ tr4

Bitfield<9,8> ArmISA::tr4

Definition at line 573 of file miscregs_types.hh.

◆ tr5

Bitfield<11,10> ArmISA::tr5

Definition at line 574 of file miscregs_types.hh.

◆ tr6

Bitfield<13,12> ArmISA::tr6

Definition at line 575 of file miscregs_types.hh.

◆ tr7

Bitfield<15,14> ArmISA::tr7

Definition at line 576 of file miscregs_types.hh.

◆ tracefilt

ArmISA::tracefilt

Definition at line 75 of file miscregs_types.hh.

◆ tracever

Bitfield<7, 4> ArmISA::tracever

Definition at line 82 of file miscregs_types.hh.

◆ tre

Bitfield<28> ArmISA::tre

Definition at line 336 of file miscregs_types.hh.

◆ trvm

Bitfield<30> ArmISA::trvm

Definition at line 250 of file miscregs_types.hh.

◆ ts

Bitfield<55, 52> ArmISA::ts

◆ tsc

Bitfield<19> ArmISA::tsc

Definition at line 262 of file miscregs_types.hh.

◆ tsw

Bitfield<22> ArmISA::tsw

Definition at line 258 of file miscregs_types.hh.

◆ tta

Bitfield< 20 > ArmISA::tta

Definition at line 193 of file miscregs_types.hh.

◆ tta_e2h

Bitfield<28> ArmISA::tta_e2h

Definition at line 671 of file miscregs_types.hh.

◆ ttee

Bitfield<16> ArmISA::ttee

Definition at line 215 of file miscregs_types.hh.

◆ ttl

Bitfield<51, 48> ArmISA::ttl

Definition at line 148 of file miscregs_types.hh.

◆ ttlb

Bitfield<25> ArmISA::ttlb

Definition at line 255 of file miscregs_types.hh.

◆ tvm

Bitfield<26> ArmISA::tvm

Definition at line 254 of file miscregs_types.hh.

Referenced by MiscRegOp64::checkEL2Trap().

◆ twe

Bitfield< 13 > ArmISA::twe

Definition at line 267 of file miscregs_types.hh.

◆ twi

Bitfield< 12 > ArmISA::twi

Definition at line 268 of file miscregs_types.hh.

◆ txfull

Bitfield<29> ArmISA::txfull

Definition at line 726 of file miscregs_types.hh.

◆ txu

Bitfield<26> ArmISA::txu

Definition at line 729 of file miscregs_types.hh.

◆ tz

Bitfield< 8 > ArmISA::tz

Definition at line 202 of file miscregs_types.hh.

Referenced by mkutctime().

◆ u

Bitfield<22> ArmISA::u

Definition at line 348 of file miscregs_types.hh.

Referenced by bitsToFloat32(), bitsToFloat64(), sc_dt::div_by_zero(), floatToBits32(), floatToBits64(), fp16_cvtf(), fp32_cvtf(), fp64_cvtf(), fplibFixedToFP(), fplibFPToFixed(), FPToFixed_16(), FPToFixed_32(), FPToFixed_64(), sc_core::sc_time::from_value(), MPP_TAGE::handleUReset(), TAGE_SC_L_TAGE::handleUReset(), TAGEBase::handleUReset(), ArmISA::ISA::MiscRegLUTEntryInitializer::mapsTo(), tlm_utils::callback_binder_bw< tlm::tlm_base_protocol_types >::nb_transport_bw(), sc_core::sc_prim_channel::next_trigger(), sc_core::sc_module::next_trigger(), sc_core::next_trigger(), sc_gem5::Event::notify(), sc_core::sc_event::notify(), sc_dt::operator!=(), sc_dt::operator%(), sc_dt::operator&(), sc_dt::operator*(), sc_dt::operator+(), sc_dt::operator-(), sc_dt::operator/(), sc_dt::operator<(), sc_dt::operator<<(), sc_dt::operator<=(), sc_dt::operator==(), sc_dt::operator>(), sc_dt::operator>=(), sc_dt::operator>>(), sc_dt::operator^(), sc_dt::operator|(), SparcISA::SparcStaticInst::passesFpCondition(), TAGE_SC_L_TAGE_8KB::resetUctr(), MPP_TAGE::resetUctr(), TAGEBase::resetUctr(), BitUnionData::templatedFunction(), tlm::tlm_generic_payload::update_original_from(), sc_dt::vec_add_small(), sc_dt::vec_complement(), sc_dt::vec_copy(), sc_dt::vec_copy_and_zero(), sc_dt::vec_div_small(), sc_dt::vec_find_first_nonzero(), sc_dt::vec_from_char(), sc_dt::vec_mul_small_on(), sc_dt::vec_sub_on(), sc_dt::vec_sub_on2(), sc_dt::vec_sub_small(), sc_dt::vec_to_char(), sc_core::sc_prim_channel::wait(), sc_core::sc_module::wait(), and sc_core::wait().

◆ uao

Bitfield<7, 4> ArmISA::uao

Definition at line 158 of file miscregs_types.hh.

◆ uci

Bitfield<26> ArmISA::uci

Definition at line 339 of file miscregs_types.hh.

◆ uct

Bitfield<15> ArmISA::uct

Definition at line 362 of file miscregs_types.hh.

◆ udccdis

Bitfield<12> ArmISA::udccdis

Definition at line 741 of file miscregs_types.hh.

◆ ufc

Bitfield<3> ArmISA::ufc

Definition at line 430 of file miscregs_types.hh.

◆ ufe

Bitfield<11> ArmISA::ufe

Definition at line 436 of file miscregs_types.hh.

◆ uma

Bitfield<9> ArmISA::uma

Definition at line 373 of file miscregs_types.hh.

◆ unflattenResultMiscReg

int ArmISA::unflattenResultMiscReg[NUM_MISCREGS]

If the reg is a child reg of a banked set, then the parent is the last banked one in the list.

This is messy, and the wish is to eventually have the bitmap replaced with a better data structure. the preUnflatten function initializes a lookup table to speed up the search for these banked registers.

Definition at line 1344 of file miscregs.cc.

Referenced by preUnflattenMiscReg(), and unflattenMiscReg().

◆ up

Bitfield<23> ArmISA::up

◆ useImm

Bitfield<25> ArmISA::useImm

Definition at line 100 of file types.hh.

◆ uwxn

Bitfield<20> ArmISA::uwxn

Definition at line 351 of file miscregs_types.hh.

◆ v

Bitfield< 28 > ArmISA::v

Definition at line 51 of file miscregs_types.hh.

Referenced by sc_gem5::VcdTraceFile::addNewTraceVal(), RoutingUnit::addRoute(), sc_gem5::VcdTraceFile::addTraceVal(), Trace::TarmacParserRecord::advanceTrace(), sc_dt::sc_concat_bool::allocate(), ArmISA::ISA::MiscRegLUTEntryInitializer::allPrivileges(), IniFile::Entry::appendValue(), ArmISA::ISA::MiscRegLUTEntryInitializer::banked(), ArmISA::ISA::MiscRegLUTEntryInitializer::banked64(), ArmISA::ISA::MiscRegLUTEntryInitializer::bankedChild(), LSQ< Impl >::cacheBlocked(), ArmISA::WatchPoint::compareAddress(), sc_dt::copy_digits_signed(), Topology::createLinks(), CircularQueue< Prefetcher::STeMS::RegionMissOrderBufferEntry >::decrease(), Topology::extend_shortest_path(), VecPredRegContainer< TheISA::VecPredRegSizeBits, TheISA::VecPredRegHasPackedRepr >::get_bits(), htop9(), ArmISA::ISA::MiscRegLUTEntryInitializer::hyp(), ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2H(), ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HRead(), ArmISA::ISA::MiscRegLUTEntryInitializer::hypE2HWrite(), ArmISA::ISA::MiscRegLUTEntryInitializer::hypRead(), ArmISA::ISA::MiscRegLUTEntryInitializer::hypWrite(), ArmISA::ISA::MiscRegLUTEntryInitializer::implemented(), CircularQueue< Prefetcher::STeMS::RegionMissOrderBufferEntry >::increase(), MultiperspectivePerceptron::insert(), InstResult::InstResult(), ArmISA::BrkPoint::isEnabled(), ArmISA::WatchPoint::isEnabled(), isPow2(), sc_gem5::Process::isUnwinding(), Topology::makeLink(), ArmISA::TlbEntry::match(), PortProxy::memsetBlob(), PortProxy::memsetBlobPhys(), ArmISA::ISA::MiscRegLUTEntryInitializer::mon(), ArmISA::ISA::MiscRegLUTEntryInitializer::monE2H(), ArmISA::ISA::MiscRegLUTEntryInitializer::monE2HRead(), ArmISA::ISA::MiscRegLUTEntryInitializer::monE2HWrite(), ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecure(), ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecureRead(), ArmISA::ISA::MiscRegLUTEntryInitializer::monNonSecureWrite(), ArmISA::ISA::MiscRegLUTEntryInitializer::monSecure(), ArmISA::ISA::MiscRegLUTEntryInitializer::monSecureRead(), ArmISA::ISA::MiscRegLUTEntryInitializer::monSecureWrite(), ArmISA::ISA::MiscRegLUTEntryInitializer::mutex(), sc_gem5::newReset(), ArmISA::ISA::MiscRegLUTEntryInitializer::nonSecure(), PerfectSwitch::operateMessageBuffer(), sc_dt::operator!=(), sc_dt::operator%(), sc_dt::sc_uint_base::operator%=(), sc_dt::sc_int_base::operator%=(), sc_dt::sc_unsigned::operator%=(), sc_dt::sc_signed::operator%=(), sc_dt::operator&(), sc_dt::sc_bitref< X >::operator&=(), sc_dt::sc_uint_base::operator&=(), sc_dt::sc_int_base::operator&=(), sc_dt::sc_unsigned::operator&=(), sc_dt::sc_signed::operator&=(), sc_dt::operator*(), sc_dt::sc_int< W >::operator*=(), sc_dt::sc_uint_base::operator*=(), sc_dt::sc_int_base::operator*=(), sc_dt::sc_unsigned::operator*=(), sc_dt::sc_signed::operator*=(), sc_dt::operator+(), sc_dt::sc_int< W >::operator+=(), sc_dt::sc_uint< W >::operator+=(), sc_dt::sc_uint_base::operator+=(), sc_dt::sc_int_base::operator+=(), Stats::ScalarBase< Scalar, StatStor >::operator+=(), Stats::ScalarProxy< Stat >::operator+=(), sc_dt::sc_unsigned::operator+=(), sc_dt::sc_signed::operator+=(), sc_dt::operator-(), sc_dt::sc_int< W >::operator-=(), sc_dt::sc_uint< W >::operator-=(), sc_dt::sc_uint_base::operator-=(), sc_dt::sc_int_base::operator-=(), Stats::ScalarBase< Scalar, StatStor >::operator-=(), Stats::ScalarProxy< Stat >::operator-=(), sc_dt::sc_unsigned::operator-=(), sc_dt::sc_signed::operator-=(), sc_dt::operator/(), sc_dt::sc_uint_base::operator/=(), sc_dt::sc_int_base::operator/=(), sc_dt::sc_unsigned::operator/=(), sc_dt::sc_signed::operator/=(), sc_dt::operator<(), sc_dt::operator<<(), sc_dt::sc_uint_base::operator<<=(), sc_dt::sc_int_base::operator<<=(), sc_dt::sc_unsigned::operator<<=(), sc_dt::sc_signed::operator<<=(), sc_dt::operator<=(), sc_dt::sc_bigint< W >::operator=(), sc_dt::sc_biguint< W >::operator=(), sc_core::sc_int_sigref::operator=(), sc_core::sc_uint_sigref::operator=(), sc_core::sc_unsigned_sigref::operator=(), sc_dt::sc_int< W >::operator=(), sc_dt::sc_uint< W >::operator=(), sc_core::sc_signed_sigref::operator=(), sc_dt::sc_concatref::operator=(), sc_dt::sc_uint_subref::operator=(), sc_dt::sc_int_subref::operator=(), sc_dt::sc_bitref< X >::operator=(), sc_dt::sc_uint_base::operator=(), sc_dt::sc_int_base::operator=(), Stats::ScalarBase< Scalar, StatStor >::operator=(), sc_dt::sc_unsigned::operator=(), Stats::ScalarProxy< Stat >::operator=(), sc_dt::sc_signed::operator=(), Stats::Formula::operator=(), sc_dt::operator==(), sc_dt::operator>(), sc_dt::operator>=(), sc_dt::operator>>(), sc_dt::sc_uint_base::operator>>=(), sc_dt::sc_int_base::operator>>=(), sc_dt::sc_unsigned::operator>>=(), sc_dt::sc_signed::operator>>=(), sc_dt::operator^(), sc_dt::sc_uint_base::operator^=(), sc_dt::sc_int_base::operator^=(), sc_dt::sc_unsigned::operator^=(), sc_dt::sc_signed::operator^=(), sc_dt::operator|(), sc_dt::sc_bitref< X >::operator|=(), sc_dt::sc_uint_base::operator|=(), sc_dt::sc_int_base::operator|=(), sc_dt::sc_unsigned::operator|=(), sc_dt::sc_signed::operator|=(), p9toh(), MathExpr::parse(), ArmISA::ISA::MiscRegLUTEntryInitializer::priv(), ArmISA::ISA::MiscRegLUTEntryInitializer::privNonSecure(), ArmISA::ISA::MiscRegLUTEntryInitializer::privNonSecureRead(), ArmISA::ISA::MiscRegLUTEntryInitializer::privNonSecureWrite(), ArmISA::ISA::MiscRegLUTEntryInitializer::privRead(), ArmISA::ISA::MiscRegLUTEntryInitializer::privSecure(), ArmISA::ISA::MiscRegLUTEntryInitializer::privSecureRead(), ArmISA::ISA::MiscRegLUTEntryInitializer::privSecureWrite(), Trace::TarmacParserRecord::TarmacParserRecordEvent::process(), ArmISA::ISA::MiscRegLUTEntryInitializer::reads(), DistIface::RecvScheduler::resumeRecvTicks(), Stats::DistBase< Distribution, DistStor >::sample(), Stats::DistProxy< Stat >::sample(), Stats::SparseHistBase< SparseHistogram, SparseHistStor >::sample(), sc_core::sc_assemble_vector(), sc_dt::sc_bigint< W >::sc_bigint(), sc_dt::sc_biguint< W >::sc_biguint(), sc_core::sc_cref(), sc_dt::sc_int< W >::sc_int(), sc_dt::sc_int_base::sc_int_base(), sc_core::sc_ref(), sc_dt::sc_signed::sc_signed(), sc_core::sc_time::sc_time(), sc_core::sc_trace(), sc_dt::sc_uint< W >::sc_uint(), sc_dt::sc_uint_base::sc_uint_base(), sc_dt::sc_unsigned::sc_unsigned(), ArmISA::ISA::MiscRegLUTEntryInitializer::secure(), sc_dt::sc_uint_base::set(), sc_dt::sc_int_base::set(), sc_dt::sc_unsigned::set(), Packet::set(), sc_dt::sc_signed::set(), Packet::setBE(), Packet::setLE(), ArmISA::ISA::setMiscReg(), ArmISA::ISA::setMiscRegNoEffect(), Packet::setRaw(), ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), IniFile::Entry::setValue(), FullO3CPU< O3CPUImpl >::setVectorsAsReady(), swap_byte(), LSQ< Impl >::LSQRequest::taskId(), ArmISA::BrkPoint::test(), ArmISA::WatchPoint::test(), ArmISA::BrkPoint::testContextMatch(), testPredicate(), ArmISA::BrkPoint::testVMIDMatch(), to_number(), tokenize(), TranslatingPortProxy::tryMemsetBlob(), ArmISA::ISA::MiscRegLUTEntryInitializer::unverifiable(), ArmV8KvmCPU::updateKvmState(), ArmV8KvmCPU::updateThreadContext(), ArmISA::ISA::MiscRegLUTEntryInitializer::user(), ArmISA::ISA::MiscRegLUTEntryInitializer::userNonSecureRead(), ArmISA::ISA::MiscRegLUTEntryInitializer::userNonSecureWrite(), ArmISA::ISA::MiscRegLUTEntryInitializer::userSecureRead(), ArmISA::ISA::MiscRegLUTEntryInitializer::userSecureWrite(), sc_dt::vec_add_small(), sc_dt::vec_complement(), sc_dt::vec_copy_and_zero(), sc_dt::vec_div_small(), sc_dt::vec_find_first_nonzero(), sc_dt::vec_from_str(), sc_dt::vec_mul_small_on(), sc_dt::vec_sub_on(), sc_dt::vec_sub_on2(), sc_dt::vec_sub_small(), sc_dt::vec_to_char(), ArmISA::ISA::MiscRegLUTEntryInitializer::warnNotFail(), sc_core::sc_signal< sc_dt::sc_int< W > >::write_part(), sc_core::sc_signal< sc_dt::sc_uint< W > >::write_part(), sc_core::sc_signal< sc_dt::sc_biguint< W > >::write_part(), sc_core::sc_signal< sc_dt::sc_bigint< W > >::write_part(), ArmISA::ISA::MiscRegLUTEntryInitializer::writes(), and sc_dt::sc_bigint< W >::~sc_bigint().

◆ va

Bitfield<8> ArmISA::va

◆ varange

Bitfield<19, 16> ArmISA::varange

Definition at line 155 of file miscregs_types.hh.

◆ VecPredRegHasPackedRepr

constexpr unsigned ArmISA::VecPredRegHasPackedRepr = false
constexpr

Definition at line 820 of file types.hh.

Referenced by Trace::InstRecord::setData().

◆ VecPredRegSizeBits

constexpr unsigned ArmISA::VecPredRegSizeBits = MaxSveVecLenInBytes
constexpr

Definition at line 819 of file types.hh.

Referenced by Trace::InstRecord::setData(), and Trace::ExeTracerRecord::traceInst().

◆ VECREG_UREG0

const int ArmISA::VECREG_UREG0 = 32

◆ VecRegSizeBytes

constexpr unsigned ArmISA::VecRegSizeBytes = MaxSveVecLenInBytes
constexpr

Definition at line 818 of file types.hh.

Referenced by Trace::ExeTracerRecord::traceInst().

◆ VecSpecialElem

const int ArmISA::VecSpecialElem = NumVecV8ArchRegs * NumVecElemPerNeonVecReg

◆ vectorcatch

Bitfield<15,12> ArmISA::vectorcatch

Definition at line 780 of file miscregs_types.hh.

◆ vf

Bitfield<6> ArmISA::vf

Definition at line 275 of file miscregs_types.hh.

◆ vfpExceptionTrapping

Bitfield<15, 12> ArmISA::vfpExceptionTrapping

Definition at line 463 of file miscregs_types.hh.

◆ vfpHalfPrecision

Bitfield<27, 24> ArmISA::vfpHalfPrecision

Definition at line 477 of file miscregs_types.hh.

◆ vh

Bitfield<11, 8> ArmISA::vh

Definition at line 139 of file miscregs_types.hh.

◆ vi

Bitfield<7> ArmISA::vi

Definition at line 274 of file miscregs_types.hh.

◆ virtextns

Bitfield<19,16> ArmISA::virtextns

Definition at line 779 of file miscregs_types.hh.

◆ vm

Bitfield<0> ArmISA::vm

◆ vmidbits

Bitfield<7, 4> ArmISA::vmidbits

Definition at line 140 of file miscregs_types.hh.

◆ vse

Bitfield<8> ArmISA::vse

Definition at line 273 of file miscregs_types.hh.

◆ width

Bitfield< 4 > ArmISA::width

◆ wnr

Bitfield<11> ArmISA::wnr

Definition at line 421 of file miscregs_types.hh.

◆ wpaddrmask

Bitfield<7,4> ArmISA::wpaddrmask

Definition at line 782 of file miscregs_types.hh.

◆ writeback

Bitfield<21> ArmISA::writeback

◆ wrps

Bitfield<23, 20> ArmISA::wrps

Definition at line 79 of file miscregs_types.hh.

◆ wt

Bitfield<20> ArmISA::wt

Definition at line 713 of file miscregs_types.hh.

◆ wxn

Bitfield<19> ArmISA::wxn

Definition at line 355 of file miscregs_types.hh.

Referenced by ArmISA::TLB::checkPermissions64().

◆ xnx

ArmISA::xnx

Definition at line 134 of file miscregs_types.hh.

◆ xp

Bitfield<23> ArmISA::xp

Definition at line 347 of file miscregs_types.hh.

◆ z

Bitfield< 30 > ArmISA::z

◆ zen

Bitfield< 17, 16 > ArmISA::zen

Definition at line 402 of file miscregs_types.hh.

◆ ZeroReg

const int ArmISA::ZeroReg = INTREG_ZERO
ArmISA::INTREG_R0_ABT
@ INTREG_R0_ABT
Definition: intregs.hh:220
ArmISA::INTREG_R4
@ INTREG_R4
Definition: intregs.hh:58
ArmISA::INTREG_R14_UND
@ INTREG_R14_UND
Definition: intregs.hh:94
ArmISA::INTREG_R10_FIQ
@ INTREG_R10_FIQ
Definition: intregs.hh:104
ArmISA::INTREG_R4_ABT
@ INTREG_R4_ABT
Definition: intregs.hh:224
ArmISA::INTREG_R0_FIQ
@ INTREG_R0_FIQ
Definition: intregs.hh:290
ArmISA::INTREG_R7_UND
@ INTREG_R7_UND
Definition: intregs.hh:263
X86ISA::NumIntRegs
const int NumIntRegs
Definition: registers.hh:58
ArmISA::INTREG_R14_USR
@ INTREG_R14_USR
Definition: intregs.hh:180
ArmISA::INTREG_R2_USR
@ INTREG_R2_USR
Definition: intregs.hh:167
ArmISA::INTREG_R3_SVC
@ INTREG_R3_SVC
Definition: intregs.hh:189
ArmISA::INTREG_R2
@ INTREG_R2
Definition: intregs.hh:56
ArmISA::INTREG_R1_HYP
@ INTREG_R1_HYP
Definition: intregs.hh:238
ArmISA::INTREG_R13_HYP
@ INTREG_R13_HYP
Definition: intregs.hh:84
ArmISA::INTREG_R8_UND
@ INTREG_R8_UND
Definition: intregs.hh:264
ArmISA::INTREG_R8_IRQ
@ INTREG_R8_IRQ
Definition: intregs.hh:281
ArmISA::INTREG_R1_SVC
@ INTREG_R1_SVC
Definition: intregs.hh:187
X86ISA::NumVecPredRegs
const int NumVecPredRegs
Definition: registers.hh:79
ArmISA::INTREG_R7_HYP
@ INTREG_R7_HYP
Definition: intregs.hh:244
X86ISA::NumMiscRegs
const int NumMiscRegs
Definition: registers.hh:55
ArmISA::INTREG_R4_UND
@ INTREG_R4_UND
Definition: intregs.hh:260
ArmISA::INTREG_R15_SVC
@ INTREG_R15_SVC
Definition: intregs.hh:200
ArmISA::INTREG_R6_ABT
@ INTREG_R6_ABT
Definition: intregs.hh:226
ArmISA::INTREG_ZERO
@ INTREG_ZERO
Definition: intregs.hh:112
ArmISA::INTREG_R7_MON
@ INTREG_R7_MON
Definition: intregs.hh:210
ArmISA::INTREG_R5_FIQ
@ INTREG_R5_FIQ
Definition: intregs.hh:295
ArmISA::INTREG_R11_UND
@ INTREG_R11_UND
Definition: intregs.hh:267
ArmISA::INTREG_R6_UND
@ INTREG_R6_UND
Definition: intregs.hh:262
ArmISA::INTREG_R13_UND
@ INTREG_R13_UND
Definition: intregs.hh:92
ArmISA::INTREG_R13_MON
@ INTREG_R13_MON
Definition: intregs.hh:79
ArmISA::INTREG_R7_IRQ
@ INTREG_R7_IRQ
Definition: intregs.hh:280
ArmISA::INTREG_R5_UND
@ INTREG_R5_UND
Definition: intregs.hh:261
ArmISA::INTREG_R2_ABT
@ INTREG_R2_ABT
Definition: intregs.hh:222
ArmISA::INTREG_R1_IRQ
@ INTREG_R1_IRQ
Definition: intregs.hh:274
ArmISA::INTREG_R0_HYP
@ INTREG_R0_HYP
Definition: intregs.hh:237
ArmISA::INTREG_R6_IRQ
@ INTREG_R6_IRQ
Definition: intregs.hh:279
ArmISA::INTREG_R10_ABT
@ INTREG_R10_ABT
Definition: intregs.hh:230
ArmISA::INTREG_R7_USR
@ INTREG_R7_USR
Definition: intregs.hh:172
ArmISA::INTREG_R5_MON
@ INTREG_R5_MON
Definition: intregs.hh:208
ArmISA::INTREG_R3_ABT
@ INTREG_R3_ABT
Definition: intregs.hh:223
ArmISA::INTREG_R4_HYP
@ INTREG_R4_HYP
Definition: intregs.hh:241
ArmISA::INTREG_R9_UND
@ INTREG_R9_UND
Definition: intregs.hh:265
ArmISA::INTREG_R3_UND
@ INTREG_R3_UND
Definition: intregs.hh:259
ArmISA::INTREG_R9_SVC
@ INTREG_R9_SVC
Definition: intregs.hh:195
ArmISA::INTREG_R15_MON
@ INTREG_R15_MON
Definition: intregs.hh:217
ArmISA::MaxInstSrcRegs
const int MaxInstSrcRegs
Definition: registers.hh:57
ArmISA::INTREG_R13_IRQ
@ INTREG_R13_IRQ
Definition: intregs.hh:97
ArmISA::INTREG_R11_HYP
@ INTREG_R11_HYP
Definition: intregs.hh:248
ArmISA::INTREG_R5_IRQ
@ INTREG_R5_IRQ
Definition: intregs.hh:278
ArmISA::INTREG_R2_SVC
@ INTREG_R2_SVC
Definition: intregs.hh:188
ArmISA::INTREG_R8_HYP
@ INTREG_R8_HYP
Definition: intregs.hh:245
ArmISA::INTREG_R12_HYP
@ INTREG_R12_HYP
Definition: intregs.hh:249
ArmISA::INTREG_R11_ABT
@ INTREG_R11_ABT
Definition: intregs.hh:231
ArmISA::INTREG_R0
@ INTREG_R0
Definition: intregs.hh:54
ArmISA::INTREG_R6
@ INTREG_R6
Definition: intregs.hh:60
ArmISA::INTREG_R3_HYP
@ INTREG_R3_HYP
Definition: intregs.hh:240
ArmISA::INTREG_R0_SVC
@ INTREG_R0_SVC
Definition: intregs.hh:186
ArmISA::INTREG_R8_USR
@ INTREG_R8_USR
Definition: intregs.hh:173
ArmISA::INTREG_R15_FIQ
@ INTREG_R15_FIQ
Definition: intregs.hh:299
ArmISA::INTREG_R2_HYP
@ INTREG_R2_HYP
Definition: intregs.hh:239
ArmISA::INTREG_R12_SVC
@ INTREG_R12_SVC
Definition: intregs.hh:198
ArmISA::INTREG_R4_USR
@ INTREG_R4_USR
Definition: intregs.hh:169
ArmISA::INTREG_R10_IRQ
@ INTREG_R10_IRQ
Definition: intregs.hh:283
ArmISA::INTREG_R6_MON
@ INTREG_R6_MON
Definition: intregs.hh:209
ArmISA::INTREG_R1
@ INTREG_R1
Definition: intregs.hh:55
ArmISA::INTREG_R14_IRQ
@ INTREG_R14_IRQ
Definition: intregs.hh:99
ArmISA::INTREG_R15_HYP
@ INTREG_R15_HYP
Definition: intregs.hh:253
ArmISA::INTREG_R11_MON
@ INTREG_R11_MON
Definition: intregs.hh:214
ArmISA::INTREG_R3_FIQ
@ INTREG_R3_FIQ
Definition: intregs.hh:293
ArmISA::INTREG_R12_USR
@ INTREG_R12_USR
Definition: intregs.hh:177
ArmISA::INTREG_R9_IRQ
@ INTREG_R9_IRQ
Definition: intregs.hh:282
ArmISA::INTREG_R7
@ INTREG_R7
Definition: intregs.hh:61
X86ISA::NumFloatRegs
const int NumFloatRegs
Definition: registers.hh:63
ArmISA::INTREG_R0_USR
@ INTREG_R0_USR
Definition: intregs.hh:165
ArmISA::INTREG_R2_MON
@ INTREG_R2_MON
Definition: intregs.hh:205
ArmISA::INTREG_R12_MON
@ INTREG_R12_MON
Definition: intregs.hh:215
ArmISA::INTREG_R14_MON
@ INTREG_R14_MON
Definition: intregs.hh:81
ArmISA::INTREG_R13_ABT
@ INTREG_R13_ABT
Definition: intregs.hh:87
ArmISA::INTREG_R12_ABT
@ INTREG_R12_ABT
Definition: intregs.hh:232
ArmISA::INTREG_R12_UND
@ INTREG_R12_UND
Definition: intregs.hh:268
ArmISA::INTREG_R7_FIQ
@ INTREG_R7_FIQ
Definition: intregs.hh:297
ArmISA::INTREG_R5_HYP
@ INTREG_R5_HYP
Definition: intregs.hh:242
ArmISA::INTREG_R14_SVC
@ INTREG_R14_SVC
Definition: intregs.hh:76
ArmISA::INTREG_R1_FIQ
@ INTREG_R1_FIQ
Definition: intregs.hh:291
ArmISA::INTREG_R8_MON
@ INTREG_R8_MON
Definition: intregs.hh:211
ArmISA::INTREG_R1_UND
@ INTREG_R1_UND
Definition: intregs.hh:257
ArmISA::INTREG_R1_MON
@ INTREG_R1_MON
Definition: intregs.hh:204
ArmISA::INTREG_R10_USR
@ INTREG_R10_USR
Definition: intregs.hh:175
ArmISA::INTREG_R0_IRQ
@ INTREG_R0_IRQ
Definition: intregs.hh:273
ArmISA::INTREG_R4_FIQ
@ INTREG_R4_FIQ
Definition: intregs.hh:294
ArmISA::INTREG_R2_IRQ
@ INTREG_R2_IRQ
Definition: intregs.hh:275
ArmISA::INTREG_R8_FIQ
@ INTREG_R8_FIQ
Definition: intregs.hh:102
ArmISA::INTREG_R2_UND
@ INTREG_R2_UND
Definition: intregs.hh:258
ArmISA::INTREG_R15_IRQ
@ INTREG_R15_IRQ
Definition: intregs.hh:287
ArmISA::INTREG_R3_IRQ
@ INTREG_R3_IRQ
Definition: intregs.hh:276
ArmISA::INTREG_R6_USR
@ INTREG_R6_USR
Definition: intregs.hh:171
ArmISA::INTREG_R13_FIQ
@ INTREG_R13_FIQ
Definition: intregs.hh:107
ArmISA::INTREG_R5_USR
@ INTREG_R5_USR
Definition: intregs.hh:170
ArmISA::INTREG_R11_SVC
@ INTREG_R11_SVC
Definition: intregs.hh:197
ArmISA::INTREG_R3
@ INTREG_R3
Definition: intregs.hh:57
ArmISA::INTREG_R4_SVC
@ INTREG_R4_SVC
Definition: intregs.hh:190
ArmISA::INTREG_R14_HYP
@ INTREG_R14_HYP
Definition: intregs.hh:251
ArmISA::INTREG_R10_SVC
@ INTREG_R10_SVC
Definition: intregs.hh:196
ArmISA::INTREG_R6_FIQ
@ INTREG_R6_FIQ
Definition: intregs.hh:296
ArmISA::INTREG_R9_ABT
@ INTREG_R9_ABT
Definition: intregs.hh:229
ArmISA::INTREG_R1_USR
@ INTREG_R1_USR
Definition: intregs.hh:166
ArmISA::INTREG_R7_SVC
@ INTREG_R7_SVC
Definition: intregs.hh:193
ArmISA::INTREG_R6_SVC
@ INTREG_R6_SVC
Definition: intregs.hh:192
ArmISA::INTREG_R2_FIQ
@ INTREG_R2_FIQ
Definition: intregs.hh:292
ArmISA::INTREG_R4_IRQ
@ INTREG_R4_IRQ
Definition: intregs.hh:277
ArmISA::INTREG_R11_FIQ
@ INTREG_R11_FIQ
Definition: intregs.hh:105
ArmISA::INTREG_R6_HYP
@ INTREG_R6_HYP
Definition: intregs.hh:243
ArmISA::INTREG_R10_MON
@ INTREG_R10_MON
Definition: intregs.hh:213
ArmISA::INTREG_R15_ABT
@ INTREG_R15_ABT
Definition: intregs.hh:234
ArmISA::INTREG_R13_USR
@ INTREG_R13_USR
Definition: intregs.hh:178
ArmISA::INTREG_R10_HYP
@ INTREG_R10_HYP
Definition: intregs.hh:247
ArmISA::INTREG_R12_FIQ
@ INTREG_R12_FIQ
Definition: intregs.hh:106
ArmISA::INTREG_R12_IRQ
@ INTREG_R12_IRQ
Definition: intregs.hh:285
ArmISA::INTREG_R5_ABT
@ INTREG_R5_ABT
Definition: intregs.hh:225
ArmISA::INTREG_R9_MON
@ INTREG_R9_MON
Definition: intregs.hh:212
ArmISA::INTREG_R9_HYP
@ INTREG_R9_HYP
Definition: intregs.hh:246
ArmISA::INTREG_R8_SVC
@ INTREG_R8_SVC
Definition: intregs.hh:194
ArmISA::INTREG_R7_ABT
@ INTREG_R7_ABT
Definition: intregs.hh:227
ArmISA::INTREG_R8_ABT
@ INTREG_R8_ABT
Definition: intregs.hh:228
ArmISA::INTREG_R14_ABT
@ INTREG_R14_ABT
Definition: intregs.hh:89
ArmISA::INTREG_R3_USR
@ INTREG_R3_USR
Definition: intregs.hh:168
ArmISA::INTREG_R5_SVC
@ INTREG_R5_SVC
Definition: intregs.hh:191
ArmISA::INTREG_R0_MON
@ INTREG_R0_MON
Definition: intregs.hh:203
ArmISA::INTREG_R11_USR
@ INTREG_R11_USR
Definition: intregs.hh:176
ArmISA::INTREG_R15_USR
@ INTREG_R15_USR
Definition: intregs.hh:182
ArmISA::INTREG_R0_UND
@ INTREG_R0_UND
Definition: intregs.hh:256
ArmISA::INTREG_R9_USR
@ INTREG_R9_USR
Definition: intregs.hh:174
ArmISA::INTREG_R14_FIQ
@ INTREG_R14_FIQ
Definition: intregs.hh:109
ArmISA::INTREG_R13_SVC
@ INTREG_R13_SVC
Definition: intregs.hh:74
ArmISA::INTREG_R9_FIQ
@ INTREG_R9_FIQ
Definition: intregs.hh:103
ArmISA::INTREG_R10_UND
@ INTREG_R10_UND
Definition: intregs.hh:266
ArmISA::INTREG_R5
@ INTREG_R5
Definition: intregs.hh:59
ArmISA::INTREG_R1_ABT
@ INTREG_R1_ABT
Definition: intregs.hh:221
ArmISA::INTREG_R11_IRQ
@ INTREG_R11_IRQ
Definition: intregs.hh:284
ArmISA::INTREG_R15_UND
@ INTREG_R15_UND
Definition: intregs.hh:270
X86ISA::NumVecRegs
const int NumVecRegs
Definition: registers.hh:77
ArmISA::INTREG_R3_MON
@ INTREG_R3_MON
Definition: intregs.hh:206
ArmISA::INTREG_R4_MON
@ INTREG_R4_MON
Definition: intregs.hh:207

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