gem5  v20.1.0.0
modulo.h
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20 /*****************************************************************************
21 
22  modulo.h --
23 
24  Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 
39 #include "common.h"
40 
41 SC_MODULE( modulo )
42 {
43  SC_HAS_PROCESS( modulo );
44 
45  sc_in_clk clk;
46 
47  //====================================================================
48  // [C] Always Needed Member Function
49  // -- constructor
50  // -- entry
51  //====================================================================
52 
53  const sc_signal<bool>& reset ;
54  const sc_signal<int>& in_value1; // Input port
55  const sc_signal_bool_vector4& in_value2; // Input port
56  const sc_signal_bool_vector4& in_value3; // Input port
57  const sc_signal_bool_vector8& in_value4; // Input port
58  const sc_signal_bool_vector8& in_value5; // Input port
59  const sc_signal<bool>& in_valid; // Input port
60  sc_signal<int>& out_value1; // Output port
61  sc_signal_bool_vector4& out_value2; // Output port
62  sc_signal_bool_vector4& out_value3; // Output port
63  sc_signal_bool_vector8& out_value4; // Output port
64  sc_signal_bool_vector8& out_value5; // Output port
65  sc_signal<bool>& out_valid; // Output port
66 
67  //
68  // Constructor
69  //
70 
71  modulo(
72  sc_module_name NAME, // referense name
73  sc_clock& CLK, // clock
74  const sc_signal<bool>& RESET,
75  const sc_signal<int>& IN_VALUE1,
76  const sc_signal_bool_vector4& IN_VALUE2,
77  const sc_signal_bool_vector4& IN_VALUE3,
78  const sc_signal_bool_vector8& IN_VALUE4,
79  const sc_signal_bool_vector8& IN_VALUE5,
80  const sc_signal<bool>& IN_VALID, // Input port
81  sc_signal<int>& OUT_VALUE1,
82  sc_signal_bool_vector4& OUT_VALUE2,
83  sc_signal_bool_vector4& OUT_VALUE3,
84  sc_signal_bool_vector8& OUT_VALUE4,
85  sc_signal_bool_vector8& OUT_VALUE5,
86  sc_signal<bool>& OUT_VALID // Output port
87  )
88  :
89  reset (RESET),
90  in_value1 (IN_VALUE1),
91  in_value2 (IN_VALUE2),
92  in_value3 (IN_VALUE3),
93  in_value4 (IN_VALUE4),
94  in_value5 (IN_VALUE5),
95  in_valid (IN_VALID),
96  out_value1 (OUT_VALUE1),
97  out_value2 (OUT_VALUE2),
98  out_value3 (OUT_VALUE3),
99  out_value4 (OUT_VALUE4),
100  out_value5 (OUT_VALUE5),
101  out_valid (OUT_VALID)
102 
103  {
104  clk (CLK);
105  SC_CTHREAD( entry, clk.pos() );
106  reset_signal_is(reset,true);
107  };
108 
109  //
110 
111  void entry ();
112 
113 };
114 
115 // EOF
SC_MODULE
SC_MODULE(modulo)
Definition: modulo.h:41
sc_signal_bool_vector4
sc_signal< sc_bv< 4 > > sc_signal_bool_vector4
Definition: common.h:43
sc_signal_bool_vector8
sc_signal< sc_bv< 8 > > sc_signal_bool_vector8
Definition: common.h:44
Stats::reset
void reset()
Definition: statistics.cc:569
common.h
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:319

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